JPH0828501B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device having a MOS field effect transistor (MOSFET), and more particularly to a semiconductor device with improved characteristics of a short channel MOSFET and a method for manufacturing the same.

[Background Art] With the high integration of semiconductor devices, the gate length of MOSFET is 1
Miniaturization is progressing from μm to submicron. Along with this reduction in gate length, problems such as shallower junctions in the source / drain regions and thinner gate insulating films have arisen, but at the same time, the deterioration of MOSFET characteristics due to hot carrier injection has become a problem. ing. That is, carriers composed of hot electrons or holes generated by impact ionization in the vicinity of the drain are injected into the gate oxide film, and the hot carriers change the gate threshold voltage to change the MOSFET.
The characteristics are deteriorated, that is, the hot carrier breakdown voltage and the drain breakdown voltage are lowered.

Here, the hot carrier breakdown voltage means that when the MOSFET is operated at that voltage for a certain period of time,
This is the voltage at which the characteristic (for example, mutual conductance g _m ) drops below a certain allowable range. Further, the drain breakdown voltage is a voltage at which conduction between the drain and the source occurs (the parasitic transistor including the drain / source and the substrate is turned on) when the voltage is applied to the drain.

Therefore, attempts have been made to reduce the electric field near the drain to reduce hot carriers due to impact ionization. One of them is the MOD of LDD (Lightly Doped Drain) structure.
There is SFET. As shown in FIG. 7, this LDD structure is used in a MOSFET including a semiconductor substrate 1, a gate oxide film 2, a gate electrode 3 and source / drain regions 4 and 5,
The drain regions 4 and 5 are composed of high impurity concentration regions 4a and 5a and shallow low impurity concentration regions 4b and 5b provided on the channel side. The collision ionization in the vicinity is suppressed and the hot carriers are reduced.

By the way, this LDD structure is usually manufactured by a self-alignment method using a gate electrode, and after forming a low impurity concentration region using the gate electrode 3, side walls 6 and 6 are formed on both sides of the gate electrode 3 by a CVD film. And the like, and a high impurity concentration region is formed by using the gate electrode 3 including the side walls 6, 6. Therefore, the LD formed
As is clear from the figure, the D structure has a high impurity concentration region 4
The inner ends of a and 5a are located substantially at both ends of the sidewalls 6 and 6, and the low impurity concentration regions 4b and 5b are arranged in the region extending from both end positions of the gate electrode 3 to the lower side of the sidewalls 6 and 6. Will be.

The inventors of the present invention have conducted various experiments on such LDD structure MOSFETs. In this LDD structure MOSFET, reducing the concentration of the low impurity concentration regions 4b and 5b is effective in alleviating the electric field. It was found that there is a limit to reducing the concentration by itself due to instability of hot carriers in the low impurity concentration region and an increase in series resistance. When the present inventor has examined this point, one of the causes is that the sidewalls provided on both sides of the gate electrode 3 are
Many crystal defects that act as hot carrier traps are generated in 6, 6, and the hot carriers generated in the vicinity of the drain are more sidewalls than the gate oxide film 2.
It is injected into and accumulated here, and since the side walls 6 and 6 are provided directly above the low impurity concentration regions 4b and 5b, they greatly affect the low impurity concentration region.
It is presumed that this may cause deterioration of MOSFET characteristics.

Regarding the LDD structure, for example, IEE Transactions on Electron Devices, Vol. 29, No. 4 (IEEE TRANSACTIONS ON ELECTRON DETI
CES, VOL, ED-29, No.4,) P590-P596.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device capable of improving the hot carrier withstand voltage and drain withstand voltage in an LDD-structured MOSFET to improve the MOSFET characteristics.

Another object of the present invention is to provide an effective manufacturing method of a semiconductor device having a MOSFET having a good hot carrier breakdown voltage and drain breakdown voltage.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, in the LDD structure MOSFET, the gate electrode is configured to cover at least the low impurity concentration region of the drain region, thereby eliminating hot carrier trapping sites such as sidewalls directly above the low impurity concentration, and eliminating the hot region in the MOSFET. The carrier breakdown voltage and drain breakdown voltage can be improved.

Before forming the pattern of the gate electrode (first gate), a mask (second gate) having a narrower width is formed to form a low impurity concentration region, and then the low impurity concentration region is covered. By manufacturing the LDD structure MOSFET by patterning the gate electrode and forming a high impurity concentration region on the LDD structure, the structure of the LDD MOSFET can be easily manufactured without significantly changing the manufacturing process of the LDD MOSFET. be able to.

Reference Example 1 FIG. 1 shows a MOSFET according to a reference example of the present invention, in which an active region is formed by forming a field oxide film 17 on the main surface of a silicon substrate 11 of one conductivity type, for example, P ⁻ type. A gate oxide film 12 and a gate electrode 13 made of polycrystalline silicon are formed in this active region. In addition, the silicon substrate 11
High impurity concentration region of the opposite conductivity type (N type) to the substrate
Source / drain regions 14 and 15 formed of 14a and 15a and low impurity concentration regions 14b and 15b are formed. Further, here, the gate electrode 13 is configured to have a length so as to cover substantially the entire region of the low impurity concentration regions 14b and 15b, that is, a length such that both ends of the gate electrode 13 reach the high impurity concentration regions 14a and 15a, respectively. are doing. In the figure, 18 is a silicon oxide film formed on the gate electrode 13 and is formed shorter than the gate electrode 13, and a sidewall insulating film 1 made of a CVD silicon oxide film is formed on both sides thereof.
6,16 are formed. Further, 19 is an interlayer insulating film, and 20 and 21 are a source electrode and a drain electrode, respectively.

According to this structure, since the source / drain regions 14 and 15 form the low impurity concentration regions 14b and 15b on the channel region side, respectively, as in the conventional LDD structure, especially between the source / drain regions and near the drain. Relaxes the electric field at
It is possible to suppress the generation of hot carriers due to impact ionization and improve the hot carrier breakdown voltage. Further, in this structure, since the gate electrode 13 is formed so as to cover the low impurity concentration regions 14b and 15b, the low impurity concentration regions 14b and 15b are formed.
There is no CVD silicon oxide film with many hot carrier traps as a sidewall just above b, and even if hot carriers are generated, the hot carriers injected just above the low impurity concentration region are retained. It is not (trapped). As a result, the influence of hot carriers in the low impurity concentration region is reduced, and the characteristics of the MOSFET can be improved, such as the drain breakdown voltage being improved.

Next, a method of manufacturing the MOSFET will be described with reference to FIGS.
Will be explained.

First, as shown in FIG. 3A, a field oxide film 17 is formed on a semiconductor substrate 11 made of P ⁻ type silicon single crystal by a conventional method.
And a gate oxide film 12 is formed. Then, as shown in FIG. 3B, polycrystalline silicon 13A is grown on the entire surface and the surface thereof is thermally oxidized to form a silicon oxide film 18A. Then, using the photoresist 22 and the like, the silicon oxide film 18A is pattern-etched to a length corresponding to the effective channel length as shown in FIG. Then, using the photoresist 22 and the etched silicon oxide film 18 as a mask, impurities having a conductivity type opposite to that of the substrate, such as phosphorus, are ion-implanted at a low dose amount (for example, 1 to 5 × 10 ¹² cm ⁻² ) to reduce the amount. Impurity concentration (N ⁻ type) regions 14b and 15b are formed.

Next, as shown in FIG. 3D, a silicon oxide film 16A is grown on the entire surface of the substrate by a CVD method, and then this is subjected to a highly anisotropic dry etching method such as a reactive ion etching method, eg, RIE (reactivity By etching by ion etching, side walls 16 and 16 are formed on both sides of the silicon oxide film 18 as shown in FIG. In this case, it goes without saying that the lengths of the side walls 16 and 16 depend on the thickness of the grown CVD silicon oxide film 16A.

Then, the silicon oxide film 18 and the sidewall 1
The polycrystalline silicon 13A is etched by using the masks 6 and 16 as a mask to pattern the gate electrode 13 as shown in FIG. Then, using the gate electrode 13 as a mask, an impurity of a conductivity type opposite to that of the substrate, such as arsenic, is applied at a high dose (0.5 to 0.5).
Ion implantation at 1.0 × 10 ¹⁶ cm ^-2 ) for high impurity concentration (N
⁺ Type) regions 14a and 15a are formed. As a result, the source / drain regions 14 and 15 have the LDD structure as described above, and the low impurity concentration regions 14b and 15 are formed so as to remain on both sides of the channel region due to the formation of the high impurity concentration regions 14a and 15a.
b has a structure in which the upper portion thereof is covered with the gate electrode 13.

After that, the gate oxide film 12 is removed by etching by a conventional method to expose the main surface of the silicon substrate 11 in the source / drain regions 14 and 15, an interlayer insulating film 19 is formed thereon, and a contact hole is formed after forming a contact hole. Each drain electrode 20,21
By forming the MOSFET, the MOSFET shown in FIG. 1 can be obtained.

Reference Example 2 FIGS. 3A and 3B show another reference example of the present invention. In this reference example, the silicon oxide film of the reference example is used.
A refractory metal silicide film 23 is used instead of 18.

That is, in the case of FIG.
A refractory metal such as tungsten (or molybdenum, titanium, tantalum) is formed on A and a silicidation reaction is performed on this, or a refractory metal silicide is directly formed by sputtering or CVD. And this is photoresist
Pattern etching is performed using 22 to obtain a refractory metal silicide film 23 having a pattern formed on the polycrystalline silicon 13A as shown in FIG. Then, using the refractory metal silicide film 23 as a mask, ion implantation of impurities is performed to form the low impurity concentration regions 14b and 15b.

Then, sidewalls 16 and 16 are formed on both sides of the refractory metal silicide film 23 in exactly the same manner as in the step of FIG. Using the silicide film 23 and the sidewalls 16 as a mask, the polycrystalline silicon 13A is patterned to form the gate electrode 13 as shown in FIG. 3 (B), and the impurity is ion-implanted to form the high impurity concentration region 14a, Form 15a.

After that, if an interlayer insulating film and source / drain electrodes are formed in the same manner as in Reference Example 1, an LDD structure MOSFET is completed.

Also in this reference example, the source / drain region 1 of the LDD structure
The upper portions of the low impurity concentration regions 14b and 15b of 4, 15 are covered with the gate electrode 13, and the MOSFET characteristics can be improved similarly to the structure of FIG. In addition, since the gate electrode 13 is silicided in the MOSFET of this embodiment, high speed operation is possible.

Reference Example 3 FIGS. 4A and 4B show still another reference example, which has a structure in which the reference examples shown in FIGS. 1 and 3 are combined.

That is, as shown in FIG. 4 (A), a refractory metal silicide film 23 and a silicon oxide film 18 are laminated and grown on the polycrystalline silicon 13A, and then these are integrally patterned with a photoresist 22 to form a mask. And low impurity concentration regions 14b, 15
form b. After that, sidewalls 16 and 16 are formed on both sides of the refractory metal silicide film 23 and the silicon oxide film 18, and using this as a mask, the polycrystalline silicon 13A is patterned to form the gate electrode 13 as shown in FIG. To form.
Then, using this as a mask, the high impurity concentration regions 14a, 15a
To form a MOSFET similar to that of each of the reference examples.

In the MOSFET of the present reference example, high-speed operation is enabled by siliciding the gate electrode 13, and at the time of etching the polycrystalline silicon 13A, the silicon oxide film 18 causes etching damage due to the refractory metal silicide film.
Can protect 23.

Reference Example 4 FIGS. 5 (A) to 5 (D) show still another embodiment and its manufacturing method.

In this embodiment, first, the polycrystalline silicon 13B is grown relatively thick as shown in FIG.
Formed by D or thermal oxidation. Photoresist on it 2
Form the second mask. Then, as shown in FIG. 7B, the photoresist 22 is used as a mask to form the silicon oxide film.
18B and polycrystalline silicon 13B are etched halfway in the thickness direction. In this state, impurities are ion-implanted to form low impurity concentration regions 14b and 15b.

Next, after removing the photoresist 22, the same figure (C)
As described above, by the growth of the CVD silicon oxide film grown on the entire surface of the substrate and its anisotropic etching, the silicon oxide film 18B and the unetched polycrystalline silicon 13B are formed.
Sidewalls 16 and 16 are formed on both sides of the portion. Then, in this state, the polycrystalline silicon 13B is etched again by using the silicon oxide films 18B and 16 as masks to completely etch the thin polycrystalline silicon, and as shown in FIG. 16,16
The gate electrode 13 is formed by leaving only the lower part and the thick part sandwiched therebetween. Then, by using this gate electrode 13 as a mask, high impurity concentration regions 14a and 15a are formed by ion implantation, and a MOSFET similar to the above-mentioned reference examples is formed.
To complete.

In this reference example, only the polycrystalline silicon 13B needs to be formed, and it is not necessary to form a silicon oxide film, a metal silicide film, or the like, so that the manufacturing process can be shortened.

[Specific Examples of the Present Invention]

6 (A) and 6 (B) show a specific embodiment of the present invention.

In this embodiment, the refractory metal silicide film 23 and the silicon oxide film 18 are formed on the polycrystalline silicon 13A as shown in FIG.
Then, the refractory metal silicide film 23 and the silicon oxide film 18 are pattern-etched using the photoresist 22 as a mask, as in the case of FIG. 4 (A). In this state, the low impurity concentration regions 14b and 15b are formed.

Then, a CVD silicon oxide film is grown on the entire surface and anisotropically etched to form sidewalls 16 and 16 on both sides of the refractory metal silicide film 23 and the silicon oxide film 18 as shown in FIG. 6B. To form.

Then, using the side walls 16 and 16, polycrystalline silicon 13A is patterned to form a gate electrode 13, and in this embodiment, a CVD silicon oxide film is grown on the entire surface of the substrate again and this is formed. By anisotropic etching, side walls 24, 24 are formed on both sides of the side walls 16, 16 and the gate electrode 13 as shown in FIG. Then, the side walls 24, 24 and the gate electrode 1
High impurity concentration regions 14a and 15a are formed using 3 or the like as a mask.

Since all the films are covered with the sidewalls 16 and 24 in this embodiment, it is possible to prevent etching damage to these films during the subsequent etching of the gate oxide film 12.

〔effect〕

(1) In the LDD structure MOSFET, since the gate electrode is configured to cover the low impurity concentration region of the source / drain region, the hot carrier trapping site such as the sidewall immediately above the low impurity concentration is eliminated, MOSFET
It is possible to improve the hot carrier breakdown voltage and the drain breakdown voltage.

(2) Before forming the pattern of the gate electrode, a mask having a narrower width is formed to form a low impurity concentration region, and then the gate electrode is patterned so as to cover the low impurity concentration region, and LDD by forming high impurity concentration region
By manufacturing the MOSFET of the structure, LDDMOS
It is possible to easily manufacture the MOSFET having the above structure without significantly changing the manufacturing process of the FET.

(3) Since the metal silicide film is used as a mask for forming the low impurity concentration region, the metal silicide film is integrated with the gate electrode to reduce the resistance of the gate electrode and achieve high speed MOSFET. it can.

(4) Since the sidewalls are formed on both sides of the mask for forming the low impurity concentration region, the films forming these masks can be prevented from being damaged by etching when forming the pattern of the gate electrode.

(5) Since the polycrystalline silicon that constitutes the gate electrode is formed thick and is partially etched to form the mask and the gate electrode in the low impurity concentration region, the metal silicide film and the silicon oxide film are formed. The manufacturing process can be simplified as compared with the case of forming.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the scope of the invention. Nor.

For example, the conductivity type of each semiconductor region may be opposite. The present invention can also be applied to a complementary semiconductor device (CMOS IC) having N and P channel MOSFETs. That is, CM
It is effective when applied to N (P) channel MOSFET in OSIC. Further, also in the embodiments shown in FIGS. 1, 2, 3, and 5, on both sides of the finally formed gate electrode,
If the side wall is further formed as in the embodiment of FIG. 6, the gate electrode can be protected from etching damage at the time of etching in a later step. Further, by appropriately adjusting the length of the sidewall according to the diffusion rate of the impurities forming the high impurity concentration region, it is possible to finely adjust the relationship between the low impurity concentration region and the gate electrode covering the low impurity concentration region. In some cases, when only the drain region has the LDD structure, the low impurity concentration region of the drain region may be covered with the gate electrode.

[Field of application]

In the above description, the case where the invention made by the present inventor is mainly applied to the MOSFET element which is the field of application which is the background has been described, but the invention is not limited thereto and a semiconductor including an LDD structure MOSFET is provided. It can be applied to all semiconductor devices such as integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of a reference example according to the present invention, and FIGS. 2A to 2F are cross-sectional process diagrams for explaining a manufacturing method of the reference example of FIG. 3 (A) and 3 (B) are cross-sectional views showing main manufacturing steps of another reference example, and FIGS. 4 (A) and 4 (B) are cross-sectional views showing main manufacturing steps of still another reference example. 5 (A) to (D) are sectional views showing the main manufacturing steps of different reference examples, and FIGS. 6 (A) and 6 (B) are the main manufacturing steps of the embodiment showing the constitution of the present invention. FIG. 7 is a sectional view showing a conventional LDD structure MOSFET. 1,11 …… Semiconductor substrate, 2,12 …… Gate oxide film, 3,13 ……
Gate electrode, 4,14 ... Source region, 5,15 ... Drain region, 14a, 15a ... High impurity concentration region, 14b, 15b ... Low impurity concentration region, 16 ... Sidewall, 17 ... Field oxidation Film, 18 ... Silicon oxide film, 19 ... Interlayer insulating film, 20
Source electrode, 21 Drain electrode, 22 Photoresist, 23 Metal silicide film, 24 Sidewall.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisaro Kudo 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi, Ltd. (56) References JP-A-57-83061 (JP, A) JP-A-60 -113472 (JP, A) JP 61-201473 (JP, A) JP 61-119078 (JP, A)

Claims (1)

[Claims] 1. A step of forming a polycrystalline silicon layer to serve as a first gate on a main surface of a semiconductor substrate through an insulating film, and forming a refractory silicide layer to serve as a second gate on the polycrystalline silicon layer. A step of selectively etching the refractory silicide layer,
Patterning a gate, introducing an impurity having a first conductivity type into the substrate so as to be self-aligned with the second gate, and forming a first region having a first impurity concentration, a second gate Forming a sidewall insulating film on the first gate, patterning a first gate by selectively etching the polycrystalline silicon layer using the sidewall insulating film, forming a second gate on the first gate Forming another side wall insulating film so as to continuously cover the side wall insulating film including the side wall insulating film, and showing the first conductivity type so as to be self-aligned with the other side wall insulating film of the second gate. Introducing an impurity into the substrate to form a second region having a second impurity concentration higher than the first impurity concentration and deeper than the first region. Method of manufacturing a semiconductor device that.