JPH11297984A - Structure of ldd type mos transistor and forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the impedance, by forming a side wall from a polycrystal Si having the same conductivity type as a low concn. layer, and electrically connecting the side wall to a gate electrode. SOLUTION: The surface of a p-type Si substrate 1 is thermally oxidized to form a gate insulation film 2, an n-type polycrystal Si gate electrode 3 is formed, an insulation film 4 is formed on the surface of the gate electrode 3, an i-type impurity ion is implanted to form a low concn. layer 5 to be LDD regions, a polycrystal Si film contg. no impurity is formed and anisotropically etched to form a polycrystal Si side wall 6a, an n-type impurity ion is implanted to form a high concn. layer 7 to be source-drain regions and convert the polycrystal Si side wall to an n-type polycrystal Si side wall 6b, thereby forming an LDD structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an LD in a semiconductor device.
The present invention relates to a method for forming a D-type MOS transistor.

[0002]

2. Description of the Related Art Conventionally, in MOS type transistors, hot carriers generated by a drain avalanche near a drain are injected into a gate oxide film and trapped in the oxide film, or electrons and holes are generated with the miniaturization of the MOS transistor. Since a level is formed in the vicinity of the silicon / oxide film interface by breaking the silicon bond by the energy released by the recombination, there is a problem in that the current characteristics of the transistor deteriorate. As a countermeasure, a transistor having an LDD structure in which a low-concentration diffusion region is formed on the channel side of a source / drain diffusion layer to weaken the electric field near the drain has come to be used.

However, in an LDD transistor, the current of the transistor decreases due to the resistance caused by the low concentration layer (LDD region) that weakens the electric field. In particular, in a transistor having a short gate length, the impedance in the channel region is almost equal to the impedance in the LDD region, and the influence cannot be ignored.

Therefore, an overlapped LDD structure in which an LDD region is formed immediately below a gate electrode has been studied. According to this structure, in a bias region where the gate voltage is high, carriers are induced by the gate bias, so that resistance due to the LDD region is reduced, and deterioration of hot carriers can be suppressed without deteriorating current characteristics significantly.

Referring to FIG. 2, which is a cross-sectional view in the order of steps showing a method of forming an overlapped LDD MOS transistor, which is cited from Japanese Patent Application Laid-Open No. Hei 5-218066,
Boron is ion-implanted into one main surface 1 of a P-type silicon substrate doped with boron of 2 × 10 ¹⁵ cm ⁻³ ,
The impurity concentration of boron on one main surface is set to 1 to 5 × 10 ¹⁶ cm ⁻³ by heat treatment at 0 to 1200 ° C. LO
An element isolation region is selectively formed by the COS method, and then the silicon surface is oxidized at 800 to 900 ° C. to form a gate insulating film 2 having a thickness of 10 to 20 nm in the element formation region. A polycrystalline silicon doped with phosphorus having a thickness of 300 to 400 nm is grown, and a gate electrode 3 is formed by lithography. 7 × 10 ^{12 to} 3 × 10 phosphorus
Ion implantation is performed at a dose of ¹³ cm ⁻² to form a low concentration layer 5. Then, phosphorus doped 100-200
By depositing polycrystalline silicon having a thickness of nm and etching back the entire surface, sidewalls 6 having n-type conductivity are formed only on the side surfaces of the gate electrode. 1-5 ×
Arsenic of 10 ¹⁵ cm ⁻² is ion-implanted to form the high concentration layer 7. Thereafter, as an interlayer insulating film, 400 to 80
A process of growing a BPSG having a thickness of 0 nm, opening a contact hole, and depositing a wiring metal completes the formation of the overlapped LDD type MOS transistor.

[0006]

In the above conventional example, the actual capacitance between the substrate and the gate electrode depends on the area of the gate electrode 3 and the polysilicon sidewall 6 with respect to the substrate, and is extremely larger than the effective channel length. growing. This is LD
Even if the effect of reducing the impedance of the D part is considered, the effect on the transmission delay of a multi-stage inverter and the like is large, and not only does not improve the performance of the effective semiconductor integrated circuit, but also in the short channel device accompanying the recent miniaturization. , Causing substantial performance degradation.

[0007]

SUMMARY OF THE INVENTION The LDD type MOS of the present invention
The transistor is a MOS transistor having a gate electrode on one main surface of a semiconductor via an insulating film.
A so-called LDD transistor having a drain composed of a low-concentration layer and a high-concentration layer, wherein a sidewall provided on a side surface of the gate electrode is polycrystalline silicon having the same conductivity type as the low-concentration layer; The sidewall is electrically insulated from the gate electrode.

[0008]

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1, which is a cross-sectional view showing a method of forming an LDD MOS transistor in the order of steps, a first embodiment of the present invention is to first thermally oxidize the surface of a P-type silicon substrate 1 to perform gate insulation. A film 2 is formed, a gate electrode made of N-type polycrystalline silicon is formed using a photo-etching technique, and an insulating film 4 is formed on the surface of the gate electrode by a thermal oxidation method or a vapor phase growth method. Thereafter, ion implantation of N-type impurities is performed to form a low concentration layer 5 to be an LDD region (FIG. 1A).

Next, after forming an impurity-free polycrystalline silicon film, this polycrystalline silicon is anisotropically etched to form a side wall 6a made of polycrystalline silicon.
To form [FIG. 1 (b)].

Thereafter, high-concentration layers 7 serving as source / drain regions are formed by ion implantation of N-type impurities using the sidewalls as a mask. At the same time, the sidewalls made of polysilicon are replaced with N-type polysilicon sidewalls. 6b. Thereby, an LDD structure is formed (FIG. 1C).

Next, an interlayer insulating film 8 is formed [FIG.
(D)], an opening is formed in this, and an electrode 9 is formed [FIG.
(E)], the formation of the LDD type MOS transistor according to the present embodiment is completed.

In the above embodiment, since the sidewall of the LDD region is formed of N-type polycrystalline silicon,
The surface potential of the LDD region is increased by the work function difference compared to the oxide film sidewall LDD type MOS transistor, and the impedance of the LDD region can be reduced. Also, since the sidewall made of N-type polycrystalline silicon is electrically insulated from the gate electrode,
The capacitance between the substrate and the gate electrode can be suppressed lower than that of the gate overlap LDD.

In the above embodiment, an N-channel LDD MOS transistor is formed on the surface of a P-type silicon substrate. However, a P-well provided on the surface of a P-type or N-type silicon substrate is described. This embodiment is also applicable to the case where an N-channel type LDD type MOS transistor is formed on the surface of the substrate. Further, N well or N
P-channel LDD MOS on the surface of silicon substrate
This embodiment can be applied to the case of forming a transistor. In this case, the gate electrode may be
⁺ Type or N ⁺ type.

[0015]

As described above, the LDD type M according to the present invention is used.
In the method for forming the OS transistor, since the sidewall of the LDD region is formed of polycrystalline silicon having the same conductivity type as that of the low-concentration layer, the surface carriers of the LDD region are induced by the work function difference, and the oxide film sidewall is formed. The impedance in the LDD region can be reduced as compared with the LDD type MOS transistor. Further, since the side wall made of polycrystalline silicon having the same conductivity type as the low concentration layer in the LDD region is electrically insulated from the gate electrode, the capacitance between the substrate and the gate electrode is smaller than that of the gate overlap LDD. Can be kept low.

[Brief description of the drawings]

FIG. 1 is a sectional view of one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional gate overlap type LDD transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate insulating film 3 Gate electrode 4 Insulating film 5 Low concentration layer 6 Polycrystalline silicon sidewall 7 High concentration layer

Claims (2)

[Claims] 1. A semiconductor device comprising:
In a MOS transistor having a gate electrode, which is a so-called LDD transistor having a drain composed of a low-concentration layer and a high-concentration layer, a sidewall provided on a side surface of the gate electrode has the same conductivity type as that of the low-concentration layer. A structure of an LDD type MOS transistor, wherein the structure is made of polycrystalline silicon, and the sidewall is electrically insulated from a gate electrode. 2. The method for forming a sidewall is a method of forming a sidewall made of undoped polycrystalline silicon and then simultaneously adding impurities in a step of forming a high concentration layer by ion implantation. 2. The method for forming an LDD type MOS transistor according to claim 1, wherein: