JP2000216384A - Method of manufacturing semiconductor device and semiconductor device manufactured by the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device wherein a short channel effect is suppressed and a high speed is realized, while simplifying the manufacturing process. SOLUTION: A method of manufacturing a semiconductor device of an asymmetric LDD structure comprises the steps of forming at least a pair of gate electrodes 6 on a semiconductor substrate 1 using a resist, obliquely implanting ions for permitting formation of a first conductivity-type low concentration region 7 only in the vicinity of one gate electrode 6 using the other gate electrode 6 as a mask, where a distance a between the gate electrodes and an inclination angle θ from the surface of the semiconductor substrate 1 are set to satisfy than θ=t/(s-d), and ion-implanting a second conductivity-type impurity in the semiconductor substrate 1 perpendicularly thereto to convert the first conductivity-type low concentration region 7 to a second conductivity-type low concentration region 9a to form a second conductivity-type high concentration source/drain region 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device capable of miniaturization and high-speed operation capable of realizing high-speed operation while suppressing a short channel effect. The present invention relates to a device manufacturing method and a semiconductor device formed by the method.

[0002]

2. Description of the Related Art With the miniaturization of transistors, the short channel effect becomes remarkable.
Conventionally, in order to suppress this, as a method of reducing the electric field at the end of the source / drain region, a method of forming both the end of the source / drain region with an LDD structure has been adopted.
However, both ends of the source / drain regions have a low concentration of L
The DD structure is effective for suppressing the short-channel effect, but on the other hand, the low-concentration layer has a high resistance, so that the drive current may be reduced. When the drive current decreases, the current driving force decreases, and it is difficult to realize a high-speed transistor. Therefore, an asymmetric LDD structure in which only the end of the drain region has a low concentration layer has been proposed (Japanese Patent Laid-Open No. Sho 6
JP-A-2-132363, JP-A-4-171942, JP-A-5-2756932 and Japanese Patent Application No. 7-3.
No. 8099). For example, Japanese Unexamined Patent Publication No.
As shown in FIG. 2A, the p-type semiconductor substrate 2
After forming the gate electrode 22 and the insulating film 24 on
After the n-type low-concentration diffusion layer 23 is formed by vertically ion-implanting the n-type diffusion layer 23, as shown in FIG. A method of forming an n-type high concentration diffusion layer in the region 25 and forming a relatively long n-type low concentration diffusion layer in the drain region 27 is described.

According to this method, a semiconductor device having an asymmetric LDD structure can be formed without forming a sidewall. However, since ion implantation is performed at an angle of 30 to 60 ° from the source region 25 side,
Under the gate electrode on the source region 25 side, high-concentration n-type ions are implanted deeply. Accordingly, this causes a problem that it is difficult to prevent the short channel effect, and the transistor characteristics become unstable. Also,
Japanese Patent Application Laid-Open No. Sho 62-132363 discloses a semiconductor substrate 31.
After the gate electrode 32 is formed thereon by using the resist layer 34, as shown in FIG. 3A, ion implantation is performed from above using the gate electrode 32 and the resist layer 34 as a mask to perform high-density ion implantation. An impurity region 33 is formed, and then, as shown in FIG. 3B, the gate electrode 32 is anisotropically etched at an angle from an obliquely upper side on the drain region side to form an end of the gate electrode 32 on the drain region side. Is formed into a shape inclined inward of the length A, and further, as shown in FIG. 3C, ions are implanted from obliquely above the drain region side using this gate electrode 32 as a mask, and only at the end of the drain region. A method for forming the low concentration impurity region 35 is described.

According to this method, a semiconductor device having an asymmetric LDD structure having a low concentration diffusion layer only at the end of the drain region can be formed without forming a sidewall. However, at the time of anisotropic etching for forming an inclination in the gate electrode 32, it is necessary to protect the source region side with a resist or the like, and the number of times of photo increases by one. In addition, it is difficult to control the etching shape (shape) of the gate electrode 32, and a transistor using the same has a problem that its characteristics become unstable.

Further, Japanese Patent Application Laid-Open No. 5-27593 discloses that after a gate electrode 42 is formed on a semiconductor substrate 41,
As shown in FIG. 4A, B ⁺ is implanted from the drain region side by oblique ion implantation. At this time, since B ⁺ is blocked by the gate electrode 42, the P + region 43 is formed only on the drain region side without being injected into the source region side.
Thereafter, as shown in FIG. 4B, P ⁺ ions are implanted into the entire semiconductor substrate 41 from the vertical direction. This allows
As shown in FIG. 4C, a P
^{Since +} is not implanted, the drain region 45 itself has a P-type region 43 below the gate electrode 42, and the drain region 45 itself has an impurity concentration lower than that of the source region 44 because B ⁺ and P ⁺ cancel each other out. MOS transistors can be formed. According to this MOS transistor, the P-type region 4 is formed only under the gate electrode 42 on the drain region 45 side.
3, the punch-through phenomenon of the depletion layer is suppressed, and the breakdown voltage is increased. Therefore, it is possible to cope with miniaturization of the element itself. However, since the N-type impurity concentration on the drain region 45 side is low, the resistance value of the diffusion layer is high, and as a result, the drive current is low,
A problem arises in that it is not possible to cope with the increase in speed.

[0006]

According to the present invention, (a)
At least one pair of gate electrodes is formed on a semiconductor substrate using a resist film, and the other of the pair of gate electrodes is formed so that the first conductivity type low concentration region can be formed only near one of the gate electrodes. Oblique ion implantation is performed using the gate electrode as a mask. At this time, the total thickness t of the gate electrode and the resist film, the distance s between the gate electrodes, the width d of the first conductivity type low-concentration region from the gate electrode end, and The inclination angle θ from the surface of the semiconductor substrate is set so as to satisfy the following equation: tan θ = t / (s−d), and (b) the second conductivity type impurity is ion-implanted from a direction perpendicular to the semiconductor substrate. hand,
The low-concentration region of the first conductivity type is converted into a low-concentration region of the second conductivity type, and the low-concentration region of the second conductivity type is formed only at the end of the drain region formed by the high-concentration source / drain region of the second conductivity type. A method for manufacturing a semiconductor device having an asymmetric LDD structure having the same is provided.

Further, according to the present invention, there is provided a semiconductor device having an asymmetric LDD structure formed by the above method.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of manufacturing a semiconductor device according to the present invention, first, in a step (a), at least one pair of gate electrodes is formed on a semiconductor substrate using a resist film.
Here, the semiconductor substrate that can be used in this manufacturing method is not particularly limited as long as it is a semiconductor substrate on which a semiconductor device is usually manufactured. For example, a semiconductor substrate of silicon, germanium, or the like, GaAs, InGaAs, or the like can be used. And various others such as compound semiconductors. Among them, a silicon substrate is preferable. Note that the semiconductor substrate is
Preferably, one conductivity type impurity is doped. In this case, the first conductivity type impurities include phosphorus and arsenic in the case of P type, and boron and the like in the case of N type. The impurity concentration is not particularly limited as long as the concentration is usually contained in the semiconductor substrate constituting the transistor.
For example, about 5 × 10 ^{16 to} 3 × 10 ¹⁷ cm ⁻³ is mentioned. An element isolation film such as a LOCOS film may be formed on the semiconductor substrate.

On the semiconductor substrate, at least one pair of gate electrodes is usually formed with a gate insulating film interposed therebetween. The gate electrode at this time can be formed by a known method, for example, a photolithography and etching process using a resist film. Here, the gate electrode is formed with a distance s between the pair of gate electrodes. Also, the gate electrode
It is formed so that the total film thickness with the resist film becomes t.
In other words, the gate electrode formed here, together with the resist film, is used in a later step for the first gate electrode relative to the other gate electrode.
The inclination angle θ of the conductive type low concentration region with respect to the semiconductor substrate surface
In order to function as a mask when forming by oblique ion implantation, a pair of oblique ion implantation described later and a width d from the end of the gate electrode of the first conductivity type low-concentration region are taken into consideration. It is necessary to adjust the distance s between the gate electrodes and the total thickness t of the gate electrode and the resist film. For example, it is preferable that the relationship of tan θ = t / (s−d) is almost satisfied (FIG. 1C). reference). Specifically, the pair of gate electrodes are preferably formed in parallel with each other, and the distance s between the gate electrodes is preferably s.
Is about 0.5 to 0.75 μm. The thickness of the gate electrode is about 150 to 200 nm. The thickness of the resist film when forming the gate electrode is, for example, about 300 to 800 nm,
m. The width of the gate electrode is not particularly limited as long as it has a width normally used as a word line.
About 0.50 μm. The gate electrode is usually made of a material that functions as a word line of a semiconductor device, for example,
Metals such as aluminum, copper, silver, platinum, and high melting point metals (such as tungsten, tantalum, titanium, and molybdenum), polysilicon, silicide with high melting point metal, and polycide can be used.

In addition, oblique ion implantation is performed using the other gate electrode as a mask so that the first conductivity type low concentration region can be formed only in the vicinity of one of the pair of gate electrodes. At this time, the oblique ion implantation is performed from the other gate electrode side, that is, from one of the regions serving as the source / drain regions with respect to the one gate electrode, preferably from the drain region side, to one of the gate electrodes on the drain region side. An inclination angle (inclination angle with respect to the surface of the semiconductor substrate) is provided so that the first conductivity type impurity is implanted only in the vicinity, and the width of the first conductivity type impurity region from the gate electrode end is d.
And so on. Here, the inclination angle θ is the total thickness t of the gate electrode and the resist film, the distance s between the pair of gate electrodes, and the distance from the gate electrode end of the first conductivity type low concentration region so as to satisfy the above relational expression. The distance can be determined in consideration of the distance d, for example, about 50 to 60 °.

In other words, if an attempt is made to implant ions obliquely from the drain region side at the above-mentioned inclination angle, a shadow region is formed on the semiconductor substrate by the other gate electrode, and no ion implantation is performed in this region. Therefore, the first-conductivity-type low-concentration region can be formed only in the vicinity of one gate electrode of the semiconductor substrate on the other gate electrode side, that is, on the drain region side, within the range of the width d from the gate electrode end. Here, the vicinity of the gate electrode of the semiconductor substrate on the drain region side usually means a region having a width about the region where the sidewall spacer formed on the gate electrode is formed. For example, a sidewall spacer usually formed on the side wall of a gate electrode can be formed by etching back an insulating film having a thickness of about 200 to 240 nm over the entire surface. .
It is about 1 to 0.15 μm. Therefore, the vicinity of the gate electrode of the semiconductor substrate on the drain region side is within a region having a width d of about 0.1 to 0.15 μm from the gate electrode end (FIG. 1).
(See d in (d)).

Further, it is necessary to prevent the first conductivity type impurity from excessively entering below the gate electrode by the oblique ion implantation. Therefore, the conditions of ion implantation can be appropriately adjusted depending on, for example, the implantation angle θ, the ion species, and the like. For example, the ion species is arsenic ion or BF ^2+.
In the case of, the acceleration energy is about 10 to 20 KeV,
The injection amount is about 1 to 10 × 10 ¹⁴ cm ⁻² . Thereby, the first conductivity type low concentration region has an impurity concentration of 1 ×.
It can be formed at about 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ .

In the step (b), the semiconductor substrate is
The second conductivity type impurity is ion-implanted from a vertical direction. This
The conditions for ion implantation at this time are, for example,
It can be adjusted as appropriate, but if the ion species is BF²⁺in the case of
, The acceleration energy is about 30-50 KeV,
Is 1-2 × 10¹⁵cm^-2Degree. This
In this case, the first conductivity type low concentration region has an impurity concentration of 1 × 10¹⁷
~ 1 × 10¹⁸cm^-3Converted into low concentration region of second conductivity type
And an impurity concentration of 1 × 10¹⁹
~ 1 × 10²⁰cm^-3Second-conductivity-type high-concentration source /
A drain region can be formed. Also, ion species
Is arsenic ion, the acceleration energy is 40-60.
About KeV, injection amount is 1-5 × 10¹⁵cm^-2Degree
Can be Thereby, the first conductivity type low concentration region is formed
Concentration is 1 × 10¹⁷~ 1 × 10¹⁸cm ^-3Second conductivity type
It can be converted to a low concentration region,
The degree is 1 × 10²⁰~ 1 × 10^{twenty one}cm^-3Second conductivity type
High concentration source / drain regions can be formed
You. Thereby, the second conductivity type low concentration is formed only at the end of the drain region.
Semiconductor device with asymmetric LDD structure having degree region
Can be

In the method of manufacturing a semiconductor device according to the present invention, before, during, and after the above steps, cleaning, formation of an insulating film, formation of a protective film, channel implantation, heat treatment, formation of an interlayer insulating film, formation of a contact hole. One or more processes that are usually performed when a semiconductor device is formed, such as forming a wiring, may be performed. In particular, it is preferable to form an implantation protection oxide film between the oblique ion implantation and the vertical ion implantation in order to reduce damage to the substrate during the ion implantation. At this time, the injection protection film is preferably formed by an oxidation treatment. By this oxidation treatment, a silicon oxide film having a thickness of about 50 to 200 ° can be formed on the entire surface of the semiconductor substrate.
A thick silicon oxide film of about 400 ° can be formed. In the ion implantation in the step (b), impurities are implanted into the thick oxide region so as to have a peak near the surface of the semiconductor substrate in the ion implantation in the step (b). This is advantageous because the low-concentration region of the first conductivity type can be converted into a low-concentration region of the second conductivity type that is shallower than the source / drain regions.

An embodiment of a semiconductor device according to the present invention will be described below with reference to the drawings. First, an oxide film (not shown) having a thickness of about 200 ° is formed in order to reduce damage to the substrate at the time of channel implantation, and thereafter, channel implantation ( ¹¹ B ⁺ , implantation energy: 20 KeV, implantation amount: 1.
0 to 10 × 10 ¹² cm ⁻² ). Thereafter, pre-cleaning such as RCA cleaning is sufficiently performed, and as shown in FIG. 1A, a gate insulating film 2a (90 °) is formed on the silicon substrate 1 by gate oxidation (900 ° C.). On this gate insulating film 2a, a polysilicon film 3a is deposited (SiH ⁴ gas,
620 ° C., thickness 1000 °), and then the WSi film 4
a is deposited (360 ° C., film thickness 1000 °).

Next, as shown in FIG. 1B, a resist is applied on the obtained silicon substrate 1, and the resist is patterned by a photolithography and etching process to form a resist mask 5. Using this resist mask 5, the WSi film 4a, the polysilicon film 3a and the gate insulating film 2a are dry-etched to form a pair of gate electrodes 6 (films) having a distance s between the gate electrodes of about 0.5 to 0.75 μm. Thickness: 2000 Å, total thickness of gate electrode and resist film: 7000 及 び) and a part of wiring.

Subsequently, as shown in FIG. 1C, using the gate electrode 6 and the resist mask 5 as a mask,
⁷⁵ As ^{+ is} implanted into the surface of the silicon substrate 1 at a tilt angle θ of 50 to 60 ° from a predetermined direction, and a low concentration of about 0.1 to 0.15 μm in width d is obtained from the end of the gate electrode 6. Region 7 is formed. The implantation conditions at this time are: implantation energy: 10 to 20 KeV, implantation amount: 1.0 to 10.0 × 1.
About ¹⁴ cm ^-2 is appropriate. Thereafter, as shown in FIG. 1D, the resist mask 5 is peeled off, and the entire surface of the obtained silicon substrate 1 is oxidized to form an oxide film 8 having a thickness of about 100 °. This oxide film 8 is for reducing damage to the substrate due to ion implantation in the next step.

Next, as shown in FIG.
From the direction perpendicular to the control board 1 ⁴⁹BF²⁺Make an injection
To form a high concentration source / drain region 9
Then, the low-concentration region 7 is converted into a p-type low-concentration region 9a.
The implantation conditions at this time are: implantation energy: 40 KeV;
Amount: 1.0-2.0 × 10¹⁵cm^-2Appropriate degree
You. Subsequently, as shown in FIG. 1F, the oxide film 8 is removed.
After removing, an interlayer insulating film is formed on the entire surface of the obtained silicon substrate 1.
10 is formed, and the entire surface is smoothed by etch back.
You. After that, a contact hole is formed in the interlayer insulating film 10.
Formed on the interlayer insulating film 10 including the contact hole.
1Cu film is formed and patterned to form the metal wiring 11
To achieve. By such a method, only at the end of the drain region
Forming an asymmetric semiconductor device with low concentration regions
Can be.

[0019]

According to the present invention, first, the first conductivity type low concentration region is formed only at the drain end by using the adjacent gate electrode as a mask.
At the same time as converting the low-concentration region of the conductivity type to the low-concentration region of the second conductivity type, the source / drain region that is the high-concentration region of the second conductivity type is formed. The LDD region can be reliably formed. Thus, the manufacturing process of the semiconductor device can be simplified, and the manufacturing cost can be reduced.

Furthermore, unlike the prior art, the LDD region can be formed only at the drain end without performing any special processing on the gate electrode itself. Can be manufactured at low cost. Furthermore, since the second conductivity type high-concentration region can be formed by ion implantation in the vertical direction, it is possible to prevent impurities from flowing under the gate electrode, and furthermore, a highly reliable semiconductor device having stable characteristics. Can be manufactured. Further, the short channel effect can be suppressed while realizing the simplification of the manufacturing process as described above, and the resistance value of the source / drain region is kept low by forming the source / drain region having the same impurity concentration. As a result, a high drive current can be obtained, and high-speed operation can be achieved even when the semiconductor device is miniaturized.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional manufacturing process diagram of a main part for describing an embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic cross-sectional manufacturing process diagram of a main part for describing a conventional method of manufacturing a semiconductor device.

FIG. 3 is a schematic cross-sectional manufacturing process view of a main part for describing another conventional method for manufacturing a semiconductor device.

FIG. 4 is a schematic cross-sectional manufacturing process diagram of a main part for describing another conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 silicon substrate (semiconductor substrate) 2a, 2 gate insulating film 3a polysilicon film 4a WSi film 5 resist mask 6 gate electrode 7 low-concentration region (first-conductivity-type low-concentration region) 8 oxide film (injection protection oxide film) 9 source / Drain region (second conductivity type high concentration source /
Drain region) 9a P-type low concentration region (second conductivity type low concentration region) 10 Interlayer insulating film 11 Metal wiring

Claims (3)

[Claims] (A) forming at least one pair of gate electrodes on a semiconductor substrate using a resist film, and a first conductivity type low concentration region only in the vicinity of one of the pair of gate electrodes; Is formed by oblique ion implantation using the other gate electrode as a mask. At this time, the total thickness t of the gate electrode and the resist film, the distance s between the gate electrodes, the first conductive type low concentration region The width d from the end of the gate electrode and the inclination angle θ from the surface of the semiconductor substrate are set so as to satisfy the following equation: tan θ = t / (s−d), and (b) the angle d from the direction perpendicular to the semiconductor substrate. Forming a second conductive type high-concentration source / drain region while converting the first conductive low-concentration region into a second conductive low-concentration region by ion-implanting a second conductive type impurity; Only first The method of manufacturing a semiconductor device of the asymmetric LDD structure having a conductivity type low concentration region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein between the oblique ion implantation and the vertical ion implantation, an implantation protection oxide film is formed by oxidation treatment on the entire surface of the obtained semiconductor substrate. Method. 3. A semiconductor device having an asymmetric LDD structure formed by the method according to claim 1.