JPH07283400A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device whose reliability is high by a method wherein impurities are introduced into a semiconductor substrate by a thermal diffusion operation and a low concentration diffused layer is formed. CONSTITUTION:A gate electrode 4 is formed on a semiconductor substrate 1, fluorine ions are implanted into a gate oxide film other than the lower part of the gate electrode 4, and a conductive gate sidewall 6 which contains impurities is formed so as to come into contact with the gate electrode 4. Then, the impurities are diffused into the semiconductor substrate 1 from the sidewall 6 by a heat treatment. Thereby, the impurities are introduced into the semiconductor substrate 1 by a thermal diffusion operation, and a low concentration diffused layer is formed. Thereby, it is possible to obtain a semiconductor device in which a junction depth is shallow, in which a defect is small in a junction part and whose reliability is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art A conventional method for manufacturing a MOS transistor having an LDD structure will be described with reference to FIGS. 6A to 6G show a MOS according to the first conventional method.
It is a manufacturing process figure of a transistor.

First, an oxide film 42 and a polycrystalline silicon film 43 containing impurities are formed in this order on a semiconductor substrate 41 (FIG. 6A). Next, the polycrystalline silicon film 43 is processed into the shape of the gate electrode 44 (FIG. 6B), the impurity D is ion-implanted into the semiconductor substrate 41 using the gate electrode 44 as a mask, and the low-concentration impurity diffusion layer 45 is formed. (Fig. 6)
(C)). Then, after depositing a polycrystalline silicon film 46 containing impurities on the entire surface of the semiconductor substrate 41 (FIG. 6).
(D)), the gate electrode 44 of the polycrystalline silicon film 46
Anisotropic etching is performed so that only the periphery of
(E)), the gate sidewall 47 is formed. Next, the impurity D ′ is implanted into the semiconductor substrate 41 by ion implantation (see FIG. 6).
(F)), heat treatment is performed to form the high-concentration impurity diffusion layers 48 in the source / drain regions, whereby the MOS transistor having the LDD structure is completed (FIG. 6 (g)).

Next, FIGS. 7A to 6E are manufacturing process diagrams of a MOS transistor according to the second conventional method. This is a conventional technique.

First, an oxide film 52 and a polycrystalline silicon film 53 containing impurities are formed in this order on a semiconductor substrate 51, and then the polycrystalline silicon 53 is processed into a gate electrode 54 shape (FIG. 7A). . Next, the impurity D is ion-implanted into the semiconductor substrate 51 using the gate electrode 54 as a mask to form a low-concentration impurity diffusion layer 55 (FIG. 7B). Then, after depositing a polycrystalline silicon film containing impurities on the entire surface of the semiconductor substrate 51, anisotropic etching is performed so that only the periphery of the gate electrode 54 of the polycrystalline silicon film remains as the gate sidewall 57 (FIG. 7 ( c)). Next, the refractory metal film 58 is deposited on the entire surface of the semiconductor substrate 51, and the impurity D ′ is introduced into the refractory metal film 58 by ion implantation (FIG. 7D). Further, heat treatment is performed to form a high melting point silicide layer 59 in the source / drain regions, and a high concentration impurity diffusion layer 60 is formed from the high melting point metal film 58 containing the impurity D ′ (FIG. 7E). A MOS transistor having an LDD structure is completed.

A method of manufacturing a semiconductor device having the conventional LDD structure as described above is disclosed in, for example, Japanese Patent Laid-Open No. 63-12217.
No. 4 and Japanese Patent Laid-Open No. 4-305938.

[0007]

The above-described conventional method of manufacturing a semiconductor device having an LDD structure has the following problems with the miniaturization of semiconductor elements.

First, the semiconductor device having the LDD structure is
Hot electrons generated by the high electric field layer below the side wall of the gate electrode are injected into the side wall, and the electric field causes depletion of the low concentration diffusion layer to further increase the resistance. Further, when impurities are implanted by a conventional ion implanter, it is difficult for the ions to go straight into the semiconductor substrate beyond the intended junction depth, deeply penetrate into the semiconductor substrate, and implant the ions in a shallow region. Therefore, in the conventional ion implantation method, the junction depth may be deeper than expected. As a result, the actual welding depth and the welding depth of the design value differ,
There is concern that the effective channel length may fluctuate and the threshold voltage may fluctuate.

Further, when ions are implanted into the semiconductor substrate by the conventional ion implantation method, crystal defects are generated in the semiconductor substrate, and it is difficult to heat the semiconductor substrate after the ion implantation to recover the crystal defects. Junction leakage current increases due to the above-described crystal defects of the semiconductor substrate, which causes deterioration of the characteristics of the semiconductor circuit. In particular, it is a serious problem when implanting boron, which is a light element and has a large diffusion coefficient, into a semiconductor substrate by ion implantation.

Therefore, an object of the present invention is to provide a highly reliable semiconductor device and its manufacturing method. A second object of the present invention is to contribute to lowering the resistance of the source / drain layer of the semiconductor device. Further, a third object of the present invention is to provide a semiconductor device capable of reducing the junction depth of the impurity diffusion layer.

[0011]

According to the present invention, the above object is to provide an insulating film containing fluorine formed on a semiconductor substrate, and an impurity containing film containing impurities formed on the insulating film. An impurity diffusion layer formed in the semiconductor substrate below the insulating film at least in a region where the impurity containing film and the insulating film are in contact with each other, and containing the same impurity as the impurity containing film. A method of forming an impurity diffusion layer in a semiconductor device and a semiconductor substrate, the method comprising: forming an insulating film containing fluorine on the semiconductor substrate; and forming an impurity containing film containing impurities on the insulating film. And a heat treatment is performed on the semiconductor substrate so that the impurity-containing film and the insulating film contact each other in the region where the impurity-containing film and the insulating film are in contact with each other. It is achieved by providing a method of manufacturing a semiconductor device characterized by comprising an impurity diffusion step of diffusing impurities.

[0012]

As described above, according to the present invention, by performing the heat treatment on the film containing fluorine on the semiconductor substrate and the film containing the first impurity formed on the film containing fluorine, By forming the shallow impurity diffusion layer containing the first impurity in the semiconductor substrate, a semiconductor device with few crystal defects causing an increase in leak current can be obtained. Furthermore,
Since hot electrons generated from the impurity diffusion layer formed under the side wall of the gate electrode are not injected into the gate electrode from the side wall of the gate electrode, the resistance of the impurity diffusion layer can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIGS. 1A to 1I are manufacturing process diagrams of a MOS transistor according to the first embodiment of the present invention. First, the thickness of the semiconductor substrate 11 is 10 nm to 20 nm.
The oxide film 12 having a thickness of about 10 is formed by a thermal oxidation method, and a thickness of 10 is formed on the oxide film 12 by a chemical vapor deposition method (CVD method).
A polycrystalline silicon film 13 having a thickness of 0 nm to 300 nm is deposited (FIG. 1 (a)). Next, the polycrystalline silicon film 13 is processed into the shape of the gate electrode 14 using a patterning technique, and fluorine ions are implanted into the semiconductor substrate 11 shown in FIG. 1B using an ion implantation method. After that, the oxide film 12 other than immediately below the gate electrode 14 is etched to a thickness of 0 nm by using an etching method.
Etching is performed to have a thickness of 10 nm. By adjusting the film thickness of the oxide film 12 in this step, the junction depth of the low-concentration diffusion layer 20 described in a later step can be adjusted. Depending on the case, the film thickness of the oxide film 12 is 0 to 10 nm.
You may etch so that it may become thicknesses other than.

From the state of FIG. 1B, a silicon oxide film (BSG) containing 1% to 20% of boron is formed by the CVD method.
A film 15 is deposited on the semiconductor substrate 11 (FIG. 1).
(C)). Then, using anisotropic etching technology, BS
The G film 15 is processed into the shape of the sidewall 17 of the gate electrode 14.
At this time, the oxide film 12 formed except for the oxide film 12 formed immediately below the gate electrode 14 and directly below the side wall 17 of the gate electrode 14 is removed, and the surface of the semiconductor substrate 11 is exposed (FIG. 1D). .

Next, titanium 16 which is a refractory metal is deposited on the semiconductor substrate 11 by a known sputtering method (FIG. 1 (e)), and the acceleration energy is 10 keV to 30 keV so that boron can enter the titanium film 16. Then, boron is ion-implanted into the semiconductor substrate 11 under the condition that the doping amount is about 3E15 cm ^{2 to} 1E16 cm ² (FIG. 1F).

The semiconductor substrate 11 has a temperature of 900 ° C. to 1200 ° C.
By performing heat treatment for 5 seconds to 60 seconds at a temperature, the titanium silicide layer 18 is formed at the interface between the titanium film 16 and the semiconductor substrate 11 and the interface between the titanium film 16 and the gate electrode 14. At the same time, in the semiconductor substrate 11 just below the titanium silicide layer 18, the boron contained in the titanium film 16 is diffused to form a high concentration diffusion layer 19.
Further, in the region immediately below the side wall 15 of the gate electrode 14 of the semiconductor substrate 11, the boron contained in the BSG film of the side wall 15 is diffused to form the low concentration diffusion layer 20. Further, boron diffuses from the titanium film 16 and the BSG film, and the resistance of the polycrystalline silicon (gate electrode) is reduced. In addition, since the fluorine contained in the oxide film 12 formed immediately below the side wall 17 has an action of promoting the diffusion of boron from the side wall 17 into the semiconductor substrate 11, the low concentration diffusion layer 20 having a shallow junction depth. Can be formed. Here, the oxide film 12 may contain chlorine instead of fluorine (FIG. 1G).

The non-silicided titanium film 16 deposited on the side wall 17 of the semiconductor substrate 11 is removed by an etching technique (FIG. 1 (h)), and the side wall 17 containing boron at a high concentration and the oxidation immediately below the side wall 17. The film 12 is removed by an etching technique, and an oxide film containing no impurities is deposited again by the CVD method to complete a P-type MOS transistor (not shown).

Although the above embodiment shows the method of manufacturing the P-type MOS transistor, when manufacturing the N-type MOS transistor, an oxide film (PS) containing phosphorus is used instead of the BSG film.
G film) may be used, and arsenic may be implanted into the titanium film 16 instead of boron in the step of FIG.

The impurity concentration of the low-concentration diffusion layer 20 can be controlled by the impurity concentration in the sidewall oxide film 15 containing impurities and the film thickness of the oxide film 12 below the sidewall, in addition to the heat treatment condition. . Further, although titanium is used as the refractory metal in the above-mentioned embodiment, tungsten or molybdenum may be used instead.

On the other hand, the step shown in FIG. 2 may be carried out after the step shown in FIG. 1G without carrying out the step shown in FIG. 2 (a) and 2 (b) are manufacturing process diagrams of a MOS transistor including a wiring layer according to the present invention.

After the step of FIG. 1G, the semiconductor substrate 11
Photoresist 22 is formed on the entire surface of the gate electrode 14
Only the photoresist 22 formed above is removed (FIG. 2A). Then, the titanium film 16 formed on the gate electrode 14 is removed by using an etching method. After that, an interlayer insulating film 23 is formed on the semiconductor substrate 11, and contact holes 24 are further formed on the source / drain regions by using a known etching method. The bottom surface of the contact hole 24 is in contact with the titanium film 16. Next, the wiring 25 that covers the inner surface of the contact hole 24 is formed (FIG. 2B). By leaving the titanium film 16 partially, it is possible to reduce the resistance of the diffusion layer.
Further, by using the titanium film 16 as a part of the electrode, the contact hole is shifted and the element isolation region 21 is removed.
Since it can be formed on the upper side, the element can be miniaturized in the lateral direction.

Second embodiment of MOS according to the present invention
A method of manufacturing a transistor will be described with reference to FIG. First, implantation is formed on the semiconductor substrate 11 into an oxide film having a thickness of about 10 nm to 20 nm by a thermal oxidation method, and the oxide film 12 having a thickness of 100 is formed by a known chemical vapor deposition method (CVD method).
nm-300 nm Boron Polycrystalline Silicon Film 1
3 is deposited (FIG. 3A). Next, the polycrystalline silicon film 13 is processed into the shape of the gate electrode 14 by using a patterning technique (FIG. 3B), and fluorine ions are formed in a region other than the oxide film 12 immediately below the gate electrode 14 by an ion implantation method. It is introduced into the formed oxide film 27 (FIG. 3C).

Thereafter, a polycrystalline silicon film 28 containing boron having a thickness of 100 nm to 300 nm is deposited by the CVD method (FIG. 3 (d)), and the polycrystalline silicon film 28 is gated by an anisotropic etching technique. The side wall 29 of 14 is processed (FIG. 3E). At this time, the gate electrode 1
4 and the oxide film 27 formed just below the side wall of the gate electrode 14 is removed.

Next, the titanium film 16 which is a refractory metal
Is deposited on the semiconductor substrate 11 by a sputtering method (FIG. 3 (f)), and boron ions are accelerated at an energy of 10 keV to 30 so that the boron enters the titanium film 16.
Ion implantation is performed under the conditions of keV and a doping amount of 3E15 cm ^{2 to} 1E16 cm ² (FIG. 3G). Further, the temperature of the semiconductor substrate 11 is 900 ° C. to 1200 ° C., and the time is 5 seconds to
By performing heat treatment for 60 seconds, the titanium film 16
A titanium silicide layer 18 is formed at the interface between the semiconductor substrate 11 and the semiconductor substrate 11, and at the interface between the titanium film 16 and the gate electrode 14. At the same time, in the semiconductor substrate 11 immediately below the titanium silicide layer 18, the boron contained in the titanium film 16 is diffused to form a high concentration diffusion layer 19. Further, since the diffusion of fluorine is promoted by the fluorine contained in the oxide film 27 immediately below the side wall 29 of the gate electrode 14, the low concentration diffusion layer 20 is formed in the region immediately below the side wall 29 of the gate electrode 14 of the semiconductor substrate 11 (FIG. 3 (h)). Here, since the fluorine contained in the oxide film 27 formed immediately below the gate side wall 29 containing boron promotes the diffusion of boron in the gate side wall 29 into the semiconductor substrate 11, the bonding into the semiconductor substrate 11 is performed. It is possible to form the low concentration diffusion layer 20 having a shallow depth. The oxide film 27 may contain chlorine instead of fluorine.

Subsequently, the titanium film 16 which has not been silicided is removed by an etching technique (FIG. 3).
(I)).

Here, since the side wall 29 of the gate electrode 14 made of a polycrystalline silicon film has conductivity, it functions as a part of the gate electrode, and the gate overlap width can be controlled by the processing size of the side wall. The impurity concentration of the low concentration diffusion layer 20 can be controlled by controlling the impurity concentration contained in the sidewall 29 of the gate electrode 14.

Further, the refractory silicide layer on the source / drain regions can prevent an increase in source / drain resistance which is a problem in a fine MOS transistor.
In the second embodiment, the impurities are introduced into the polycrystalline silicon film during the film deposition, but the impurities may be introduced by ion implantation after the film deposition. Although titanium is used as the refractory metal, tungsten, molybdenum, or the like may be used instead.

MOS of the third embodiment according to the present invention
A method of manufacturing a transistor will be described with reference to FIG. First, an oxide film 2 having a thickness of about 10 nm to 20 nm is formed on a semiconductor substrate 1 by a thermal oxidation method, and a polycrystalline silicon film containing boron having a thickness of 100 nm to 300 nm is formed on the oxide film 2 by a chemical vapor deposition method. 3 is deposited (FIG. 4A).

Next, the polycrystalline silicon film 3 is processed into a shape of the gate electrode 4 by using a patterning technique (FIG. 4).
(B)). Then, the photoresist film A is applied to the semiconductor substrate 1
Then, the photoresist film A is removed so that only the region extending over the source region and the gate electrode 4 remains. After that, fluorine ions are implanted into the oxide film 2 in the drain region by the ion implantation method (FIG. 4C), and the remaining photoresist film A is removed.

Next, a polycrystalline silicon film 6 containing boron having a thickness of 100 nm to 300 nm is deposited by a CVD method (FIG. 4 (d)), and the polycrystalline silicon film is formed into a gate electrode by using an anisotropic etching technique. 4 side wall shape is processed. At this time, the oxide film 2 other than immediately below the gate electrode and the side wall is removed, and the surface of the semiconductor substrate 1 is exposed (FIG. 4E).
After that, a silicon oxide film containing 1% to 20% of boron (B
An SG film) 7 is deposited on the semiconductor substrate 1 by a known CVD method (FIG. 4 (f)).

A temperature of 900 ° C. to 1 is applied to the semiconductor substrate 1 described above.
By performing heat treatment at 200 ° C. for a time of 5 seconds to 60 seconds, the region of the substrate 1 in contact with the BSG film 7 is
Boron is further diffused, and the high concentration diffusion layer 8 is formed. Further, in the region immediately below the gate side wall 6, fluorine contained in the oxide film 2 promotes the diffusion of boron from the gate side wall, so that the low concentration diffusion layer 9 is formed in the substrate 1 (FIG. 4G). Here, since the fluorine of the fluorine-containing oxide film 5 formed immediately below the gate side wall 6 containing boron has a function of promoting diffusion of boron in the gate side wall 6 into the semiconductor substrate, the semiconductor substrate 1 It is possible to form the low-concentration diffusion layer 9 having a shallow junction depth therein. It should be noted that instead of containing fluorine in the oxide film 2, chlorine may be contained.

Since the polycrystalline silicon film on the gate side wall 6 has conductivity, it functions as a part of the gate electrode, and the gate overlap width can be controlled by the processing size of the side wall. The concentration of the low concentration layer can also be controlled by the concentration of impurities contained in the gate sidewall 6.

In the above embodiment, the impurity is introduced into the polycrystalline silicon film at the time of depositing the film, but it may be introduced by ion implantation after the film is deposited. Further, in the above-mentioned embodiment, the oxide film etching of the region other than the gate electrode after the fluorine ion implantation is performed using the gate electrode as a mask. However, the resist mask X used when forming the gate electrode (see FIG. 5A). Is not removed even during fluorine ion implantation (Fig. 5 (b)).
It may be used as a mask for subsequent oxide film etching (see FIG. 5C).

[0035]

As is apparent from the above description, the semiconductor element having the LDD structure formed by the conventional ion implantation method causes the increase of the leak current because the crystal defects are generated in the semiconductor substrate. The diffusion layer having a deep junction depth may change the channel length and the threshold value may change. However, according to the semiconductor device and the method for manufacturing the same according to the present invention, the low concentration and high concentration source / drain diffusion layers may be formed. In both cases, impurities can be introduced from the outside of the semiconductor substrate by thermal diffusion to have a shallow junction depth, and a diffusion layer having no crystal defect that causes an increase in leak current can be formed.

In the semiconductor device having the conventional LDD structure, host electrons generated by the high electric field layer below the side wall of the gate electrode may be injected into the side wall. Although the depletion proceeded and the resistance was further increased, according to the present invention, hot electrons generated from the lower portion of the side wall of the gate electrode are not injected from the side wall. Further, the semiconductor device including the insulating film containing fluorine and the film containing the first impurity on the insulating film is heat-treated to contain the first impurity having a shallow junction depth immediately below the insulating film. Since the impurity diffusion layer can also be formed, it is possible to prevent an increase in leak current and prevent hot electrons from being injected into the gate electrode from the side wall of the gate electrode.

[Brief description of drawings]

1A to 1H are manufacturing process diagrams of a MOS transistor according to a first embodiment of the present invention.

2A and 2B are manufacturing process diagrams of a MOS transistor including a wiring layer according to the present invention.

3A to 3I are manufacturing process diagrams of a MOS transistor according to a second embodiment of the present invention.

4A to 4G are manufacturing process diagrams of a MOS transistor according to a third embodiment of the present invention.

5A to 5C are manufacturing process diagrams of a gate electrode which is a modification of the first to third embodiments of the present invention.

6 (a) to 6 (g) are diagrams showing M according to the first conventional method.
FIG. 6 is a manufacturing process diagram of an OS transistor.

7 (a) to 7 (e) are diagrams showing M according to a second conventional method.
FIG. 6 is a manufacturing process diagram of an OS transistor.

[Explanation of symbols]

 1 semiconductor substrate 2 oxide film 3 polycrystalline silicon film 4 gate electrode 6 gate sidewall 7 BSG film 8 high concentration diffusion layer 9 low concentration diffusion layer 11 semiconductor substrate 12 oxide film 13 polycrystalline silicon film 14 gate electrode 15 BSG film 16 titanium film 17 Gate Side Wall 18 Titanium Silicide Layer 19 High Concentration Diffusion Layer 20 Low Concentration Diffusion Layer 21 Element Isolation Region 22 Photoresist 23 Interlayer Insulation Film 24 Contact Hole 25 Wiring 27 Oxide Film 28 Polycrystalline Silicon Film 29 Gate Sidewall 41 Semiconductor Substrate 42 Oxide Film 43 Polycrystalline Silicon Film 44 Gate Electrode 45 Low Concentration Impurity Diffusion Layer 46 Polycrystalline Silicon Film 47 Gate Sidewall 48 High Concentration Impurity Diffusion Layer 51 Semiconductor Substrate 52 Oxide Film 53 Polycrystalline Silicon Film 54 Gate Electrode 55 Low Concentration Impurity Diffusion Layer 57 Gate Side wall 58 High melting Metal 59 refractory silicide layer 60 high concentration impurity diffusion layer

Claims (2)

[Claims] 1. An insulating film containing fluorine formed on a semiconductor substrate, an impurity containing film containing impurities formed on the insulating film, and a region where at least the impurity containing film and the insulating film are in contact with each other. And an impurity diffusion layer formed in the semiconductor substrate below the insulating film and containing the same impurities as the impurity-containing film. 2. A method of forming an impurity diffusion layer in a semiconductor substrate, the method comprising: forming an insulating film containing fluorine on the semiconductor substrate; and forming an impurity containing film containing impurities on the insulating film. And diffusing the impurities into the semiconductor substrate from the impurity-containing film through the insulating film in a region where the impurity-containing film and the insulating film are in contact with each other by subjecting the semiconductor substrate to a heat treatment. A method of manufacturing a semiconductor device, comprising: an impurity diffusion step.