JP2001085676A - Mos transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LDD(lightly doped drain) MOS transistor for preventing the switching speed of a MOS transistor from decreasing, and a method for manufacturing the LDD MOS transistor. SOLUTION: The transistor is equipped with a first conductivity-type semiconductor substrate 112, first insulating layers 130A and 130B that are formed on the substrate 112, a trench that is formed in the gate formation region of the substrate 112 and the first insulating layers 130A and 130B, a source and a drain that are formed by setting second conductivity-type upper and lower parts to high concentration regions 126A and 126B and lower ones 120A and 120B, respectively, side wall spacer 145 of a second insulating layer that is formed at both the side wall parts of the trench, a gate oxide film 144 that is formed at the trench bottom being sandwiched between the side wall spacers 145, and a gate 148a that is formed inside the trench on the gate oxide film 144.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method for manufacturing the same, and more particularly, to an improved L transistor.
The present invention relates to a MOS transistor having DD (Lightly Doped Drain) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS.
FIG. 14 is a cross-sectional view for describing a manufacturing step of the transistor. In FIG. 4A, the semiconductor substrate 12 for manufacturing an integrated circuit has a <100> direction, and the concentration of the P-type dopant in the substrate 12 is about 10 ¹⁶ ions / cm ³ .

In FIG. 5B, a gate oxide film 14 is formed on the upper surface of a substrate 12 by a thermal oxidation method, and the gate oxide film 14 has a thickness of 60 to 120 °. In FIG. 5C, LPCVD (Low Pressure Che)
A polysilicon layer 16 is formed on the upper surface of the gate oxide film 14 by a physical vapor deposition method, and the polysilicon layer 16 has a thickness of 2000 to 3000 degrees. The polysilicon layer 16 is doped with phosphorus (P) by an in-situ (In-Situ) method.

In FIG. 6D, photolithography and anisotropic dry etching (Anisotropic) are performed.
The polysilicon layer 16 is patterned by Dry Etch. For patterning with sub-micron accuracy, it is preferable to use an I-line stepper exposure technique using a mercury lamp. The upper portion of the gate oxide film 14 is removed in a region where the polysilicon layer 16 is removed.
The lower portion of the gate oxide film 14 is left so that the substrate 12 is not etched during the anisotropic dry etching process. The patterned polysilicon layer 16 has a thickness of 2000
It has a width of 〜１０10000Å.

In FIG. 6E, LDD regions 20A and 20B are formed by implanting ions into substrate 12 using polysilicon layer 16 as an ion implantation mask. As a result, only the active region covered with the gate oxide film 14 having no polysilicon layer 16 thereon is ion-implanted. The ion beam directed to the substrate 12 has a concentration of 10 ¹³ ions / cm ² and 20 to ⁸ ions.
Contains phosphorus ions (P) having an energy of 0 KeV. As a result, the LDD regions 20A and 20B become 10 ¹⁷ i
N-type doped with a dopant concentration on the order of ons / cm ³ and has a junction depth of 100-300 °.
The LDD regions 20A and 20B are self-aligned with the polysilicon layer 16, the width of the polysilicon layer 16 plays an important role in defining the channel length, and the polysilicon layer 16 and the LDD regions 20A and 20B are MOSFETs respectively. Gate, source, and drain.

The LDD regions 20A and 20B are formed under the polysilicon layer 16 by random scattering of the ion-implanted dopant.
Is formed. The lateral spread of the LDD region (Lateral Strangle) is represented by the overlap distance D1, and the left end of the polysilicon layer 16 and the LDD
The lateral distance between the right end of the region 20A and the lateral distance between the right end of the polysilicon layer 16 and the left end of the LDD region 20B are shown. Further, the lateral spread is LD
This is about 60% of the junction depth of the D regions 20A and 20B. L
Since the DD regions 20A and 20B have a junction depth of 100-300 °, the lateral extent (distance D1) is about 60-180 °.

[0007] In FIG. 7 (F), an oxide film 22 is formed on the surface of the gate oxide film 14 and the polysilicon layer 16 above the substrate 12. The oxide film 22 is formed by a CVD method at a temperature of 300 to 400 ° C. As a result, the oxide film 22
It has a thickness of 6000 to 12000 °. In FIG. 7G, RIE (Reactive Ion Etc)
h), the oxide film 22 is etched to form the polysilicon layer 1.
6 and regions that partially cover the LDD regions 20A and 20B, respectively.
Form B. At this time, the oxide film 14 outside the polysilicon layer 16 and the sidewall spacers 22A and 22B,
Similarly to 22, the oxide film 22 on the polysilicon layer 16 is removed by RIE.

In FIG. 8H, an oxide film 24 is formed by a thermal oxidation process, and the spacer oxide film is densified during the thermal oxidation process. The thermal oxidation process is 850-
It proceeds at a temperature of 950 ° C., and the thermal oxidation process time is 40-60
Minutes. Oxide film 24 has a thickness of 60 to 150 °. Further, since the regions 20A and 20B are exposed to high temperature for a relatively long time, the regions 20A and 20B are diffused by heat and spread laterally by about several hundreds of square meters. As a result, the overlapping distance D1 increases to the overlapping distance D2. The overlap distance D2 is a lateral distance between the left end of the polysilicon layer 16 and the right end of the diffused LDD region 20A, and the distance L2 diffused from the right end of the polysilicon 16 layer.
The lateral distance from the left end of the DD area 20B is shown. The oxide film 24 is mainly formed on the substrate 12 and the polysilicon layer 16, while negligible oxide film 24 is formed on the surfaces of the sidewall spacers 22A and 22B.
The oxide films on the side wall spacers 22A and 22B are not shown.

In FIG. 1I, a polysilicon layer 16 is formed.
Then, ions are implanted into the substrate 12 using the sidewall spacers 22A and 22B as an ion implantation mask to form heavily doped regions 26A and 26B. In this case, ions are implanted only into the active region covered with the oxide film 24 outside the polysilicon layer 16 and the sidewall spacers 22A and 22B, and 10 ¹⁵ ion
An ion beam containing arsenic (As) ions having a concentration of s / cm ² and an energy of 20 to 80 KeV is applied to the substrate 1.
Join 2 As a result, the regions 26A and 26B have 10 ²⁰
N-type (N ⁺ ) is doped at about 10 to ²¹ ions / cm ³ , and the regions 26A and 26B are formed at 1500 to 2500 °
Having a junction depth of After this ion implantation, an annealing step is performed to activate the regions 26A and 26B. That is, RTA (Rapid Theme) at 1000 ° C. for 10 seconds.
In a step (rm Anneal), the ion-implanted high-concentration dopant is activated, and the regions 20A, 20B, 2
The implanted dopants in 6A and 26B are further diffused into the substrate. Diffusion occurs in both the lateral direction and the vertical direction of the substrate 12, but due to the short RTA process time,
Fine diffusion of about 0 to 50 ° occurs. In the manner described above, region 26A merges with region 20A, and region 26B merges with region 20B, such that regions 20A and 26A form the source and regions 20B and 26B form the drain.

[0010]

However, in the conventional method of manufacturing an LDDMOS transistor using ion implantation described above, a low-temperature region is formed by a high-temperature thermal oxidation process for forming a source and a drain after forming a low-concentration region. Density region (Lightly Doped Region)
n) spreads laterally under the gate, resulting in an increase in the overlap region between the gate oxide film facing the gate electrode and the LDD region. Therefore, during the operation of the device, the superimposition region increases the capacitance, and the switching speed (Switch) is increased.
There is a problem such as a reduction in the speed (chingSpeed).

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an LDDMOS transistor which does not reduce the switching speed of elements and a method of manufacturing the same.

[0012]

Therefore, in the MOS transistor according to the first aspect of the present invention, a semiconductor substrate of a first conductivity type, a first insulating layer formed on the substrate, A trench formed in a gate formation region of the first insulating layer, a source and a drain having an upper portion of a second conductivity type formed as a high-concentration region and a lower portion formed as a low-concentration region below the substrate surface excluding the trench region; A spacer of a second insulating layer formed on both side walls of the trench, a gate oxide film formed on the bottom of the trench sandwiched between the spacers, and a gate formed inside the trench on the gate oxide film And was configured.

In this configuration, the gate does not overlap with the low concentration regions of the source and drain regions with the gate oxide film interposed therebetween. In the MOS transistor according to the second aspect of the present invention, the bottom of the trench is formed in a region deeper than the bottom of the low concentration region. According to a third aspect of the present invention, there is provided a method of forming a low-concentration region of a second conductivity type by ion implantation into a semiconductor substrate of a first conductivity type. Forming a two-conductivity-type high-concentration region; forming a first insulating layer on the substrate; patterning a gate-forming region on the first insulating layer; and etching the gate-forming region to form the low-concentration region. Forming a trench exposing the high-concentration region, forming spacers of a second insulating layer on both side walls of the trench, and forming a gate oxide film on the bottom of the trench sandwiched between the spacers And forming a gate inside the trench.

Further, in the manufacturing method according to the present invention, the high concentration region is formed between the surface of the substrate and the low concentration region. In the manufacturing method according to the fifth aspect of the present invention, the source and the drain are formed in the high concentration region and the low concentration region.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are cross-sectional views illustrating a process of manufacturing an NMOS transistor according to an embodiment of the present invention. In FIG. 1A, a second conductive layer is formed in an active region of a P-type semiconductor substrate 112 having a <100> direction and having a P-type dopant concentration of about 10 ¹⁶ ions / cm ^3. N-type low-concentration region (hereinafter referred to as an N ⁻ region) 120 and a second conductivity type N
A high-concentration region (hereinafter, referred to as an N ⁺ region) 126 is formed. Here, the N ⁻ region 120 is formed by phosphorus (P) ion implantation, and the N ⁺ region 126 is formed by arsenic (As) ion implantation. Then, the N ⁺ region 126 is
N such that the upper than the region 120 ^- on the second surface N ^-
The junction depth of region 120 is formed deeper than that of N ⁺ region 126.

Referring to FIG. 1B, after an insulating film 130 is formed on the entire surface of the substrate 112, a gate forming region is patterned by photolithography. In the gate forming region, a region excluding the insulating films 130A and 130B as the first insulating layer in the insulating film 130 made of a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ) is removed. Is an area where the N ⁺ region 126 is exposed.

In FIG. 2C, the substrate 112 is etched by isotropic etching to form insulating films 130A and 130B.
Then, a trench 141 is formed in the gate formation region of the substrate 112. The depth of the trench 141 is 2,000-700.
0 °, which is larger than the junction depth of the N ⁻ regions 120A and 120B, and the bottom of the trench 141 faces the substrate 112 having a P-type dopant concentration of 10 ¹⁶ ions / cm ³ .

In FIG. 2D, a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si) is formed on the surface of the trench 141 and on the insulating films 130A and 130B by the CVD method.
₃ N ₄₎ made of an insulating layer, preferably silicon nitride film (S
An insulating layer of i ₃ N ₄ ) is formed. The insulating layer is etched back by RIE to form a sidewall spacer 145 as a second insulating layer on both side walls of the trench 141 and the insulating films 130A and 130B as the first insulating layer. Next, a gate oxide film 144 made of a silicon oxide film (SiO ₂ )
Is formed at the bottom of the trench 141 by a thermal oxidation method or a CVD method. Then, in order to suppress the punch-through phenomenon between the source and the drain and adjust the threshold voltage, ions are implanted into the substrate 112 below the trench 141, respectively.

In the above process, the side wall spacer 1
The bottom of 45 is located at the edge of the trench 141. Although not shown, the gate oxide film 144 formed by the CVD method is also formed on the sidewall spacer 145 and the insulating films 130A and 130B. In FIG. 3E, polysilicon or tungsten, titanium,
Transition metals such as tantalum or silicides such as tungsten, titanium, cobalt, molybdenum, and tantalum (Sili)
The conductive layer 148 made of the gate oxide film 14
4. Sidewall spacer 145 and insulating film 130
A, formed on 130B.

In FIG. 3F, the upper part of the conductive layer 148 is formed by a CMP (Chemical Mechanical).
Polishing) to remove the insulating film 130A, 1
Expose 30B. Conductive layer 148 in trench 141
Form a gate layer 148a. Thereafter, the dopant in the N ⁻ regions 120A and 120B is activated in the heat treatment step to cause some diffusion in the vertical direction and the side direction of the substrate 112, but does not diffuse below the gate oxide film 144. In this manner, regions 126A and 126B fuse with regions 120A and 120B, respectively, so that
Regions 120A and 126A form the source, and
B and 126B form a drain.

As described above, the MOS transistor according to the present embodiment is
Transistor is N of source and drain ^-Regions 120A, 1
20B and the gate, with the gate oxide film 144 interposed
Capacitor that reduces switching speed because it does not overlap with
To maximize the effective gate length.
The vertical electric field and the
Generated by horizontal electric field due to drain and drain voltage
The carrier can be controlled and the element characteristics are poor.
And a reduction in element life can be prevented.

In this embodiment, an N-channel MOS
Although the transistor has been described, a P-channel MOS transistor may be used.

[0023]

As described above, according to the present invention, since the low-concentration regions of the source and drain do not overlap with the gate with the gate oxide film interposed therebetween, it is possible to prevent the generation of capacitance that reduces the switching speed, and to reduce the effective gate. By maximizing the length, hot carriers generated by a vertical electric field due to a gate voltage and a horizontal electric field due to a drain voltage during operation of a transistor can be controlled, and deterioration of element characteristics and a reduction in element life can be prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of a manufacturing process of an NMOS transistor according to the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process following FIG. 1;

FIG. 3 is a sectional view illustrating a manufacturing process following FIG. 2;

FIG. 4 is a cross-sectional view illustrating a manufacturing process of an NMOS transistor according to the related art.

FIG. 5 is a sectional view illustrating a manufacturing process following FIG. 4;

FIG. 6 is a sectional view illustrating a manufacturing process following FIG. 5;

FIG. 7 is a sectional view illustrating a manufacturing process following FIG. 6;

FIG. 8 is a sectional view illustrating a manufacturing process following FIG. 7;

[Explanation of symbols]

112 substrate 120A, 120B N ⁻ region 126A, 126B N ⁺ region 141 Trench 144 Gate oxide film 145 Sidewall spacer 148a Gate layer

Claims (5)

[Claims] A semiconductor substrate of a first conductivity type; a first insulating layer formed on the substrate; a trench formed in a gate forming region of the substrate and the first insulating layer; A source and a drain in which an upper portion of the second conductivity type is formed as a high-concentration region and a lower portion is formed as a low-concentration region below the surface of the substrate; a spacer of a second insulating layer formed on both side walls of the trench; A MOS transistor comprising: a gate oxide film formed at the bottom of the trench sandwiched between spacers; and a gate formed inside the trench on the gate oxide film. 2. The MOS transistor according to claim 1, wherein a bottom of said trench is formed in a region deeper than a bottom of said low concentration region. 3. A step of forming a low-concentration region of the second conductivity type by ion-implanting into a semiconductor substrate of the first conductivity type; and forming a high-concentration region of the second conductivity type by ion-implanting into the substrate. Forming a first insulating layer on the substrate, patterning a gate forming region on the first insulating layer, and etching the gate forming region to expose the low-concentration region and the high-concentration region. Forming a trench; forming spacers of a second insulating layer on both side walls of the trench; forming a gate oxide film at a bottom of the trench sandwiched between the spacers; Forming a gate on the MOS transistor. 4. The method according to claim 3, wherein the high-concentration region is formed between the surface of the substrate and the low-concentration region. 5. The M according to claim 3, wherein a source and a drain are formed in the high concentration region and the low concentration region.
A method for manufacturing an OS transistor.