CN108376647B - Shielded gate field effect transistor and method of manufacturing the same - Google Patents
Shielded gate field effect transistor and method of manufacturing the same Download PDFInfo
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- CN108376647B CN108376647B CN201810351456.0A CN201810351456A CN108376647B CN 108376647 B CN108376647 B CN 108376647B CN 201810351456 A CN201810351456 A CN 201810351456A CN 108376647 B CN108376647 B CN 108376647B
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- 230000005669 field effect Effects 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000005684 electric field Effects 0.000 abstract description 13
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000003313 weakening effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention relates to a shielded gate field effect transistor and a manufacturing method thereof, belonging to the technical field of semiconductors. Because the step groove is formed firstly in the manufacturing method of the shielded gate field effect transistor, the bottom oxide layer is formed at the bottom of the groove, and the shielded gate oxide layer is formed on the surface of the groove, the thickness of the oxide layer at the bottom of the shielded gate field effect transistor formed by the method is thicker than that of other positions, and the purpose of weakening the electric field at the bottom of the shielded gate can be achieved, so that the bottom of the shielded gate is prevented from being broken down, the appearance of the gate structure is changed, the current conduction path is optimized, and the durability of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to the technical field of field effect transistors, and particularly relates to a shielded gate field effect transistor and a manufacturing method thereof.
Background
With the rapid development of electronic information technology, especially the rapid development of fashion consumer electronics and portable products, the demand of power devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) is increasing, MOSFETs are mainly divided into a lateral MOSFET and a longitudinal MOSFET, the lateral MOSFET has the obvious advantage of better integration and can be more easily integrated on a process platform in the prior art, but because a voltage-resistant drift region is spread on the surface, the lateral MOSFET has the greatest defect, occupies a larger area, represents the cost, and the higher voltage-resistant device has more obvious disadvantages, while the longitudinal MOSFET well avoids the problem, so that the ultrahigh voltage discrete device still has a longitudinal direction as a main component.
Fig. 1 shows a conventional trench vertical field effect transistor. In order to meet the requirement of high frequency application, the requirement of capacitance is higher and higher, and the trench type field effect transistor with the shielded gate structure is widely applied, and the basic structure is shown as fig. 2. The weakness of this structure becomes more and more pronounced as the voltage application increases, and as shown in fig. 3, the bottom of the shield gate is the location where the electric field of the device is strongest and is easily broken down. Therefore, how to reduce the electric field at the bottom of the shielding grid and prevent the shielding grid from being broken down becomes a problem to be solved in the field.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a shielded gate field effect transistor which can weaken the electric field at the bottom of a shielded gate by optimizing the thickness of an oxide layer at the bottom of the shielded gate, thereby avoiding the bottom of the shielded gate from being broken down, simultaneously adjusting the appearance of a gate structure of a device, optimizing a current conduction path, improving the durability of the device, and having the advantages of simple structure, simple and convenient production process and low cost, and a manufacturing method thereof.
In order to achieve the above object, a method for manufacturing a shielded gate field effect transistor of the present invention comprises the steps of:
(1) an N-region is generated on an N + substrate serving as a drain electrode by utilizing an epitaxial growth process;
(2) arranging a mask on the N-region for carrying out first etching to form a groove in the N-region;
(3) arranging a mask on the inner wall of the groove to carry out secondary etching to deepen the groove;
(4) arranging a mask plate on the inner wall of the deepened groove to perform third etching, deepening the groove to form a stepped groove and forming the bottom of the groove;
(5) forming a bottom dielectric layer at the bottom of the groove;
(6) removing the mask and part of the bottom dielectric layer;
(7) forming a shielding gate dielectric layer on the surface of the groove;
(8) carrying out polycrystalline deposition and back etching on the shielding grid in the groove;
(9) depositing a dielectric layer to cover the groove;
(10) performing device gate etching, gate oxidation, polysilicon deposition and etching to form a gate at the top of the trench;
(11) injecting and annealing a P-body region at the top of the N-region to form the P-body region;
(12) performing N + injection along the channel at the top of the P-body region;
(13) and forming a source electrode on the top of the device by utilizing a back-end process.
In the manufacturing method of the shielded gate field effect transistor, the mask is silicon nitride.
In the manufacturing method of the shielded gate field effect transistor, the step (5) is specifically to form a bottom oxide layer at the bottom of the trench through thermal oxygen growth.
In the manufacturing method of the shielded gate field effect transistor, the step (7) is specifically to form a shielded gate oxide layer on the surface of the trench through thermal oxygen growth.
In the manufacturing method of the shielded gate field effect transistor, the step (9) is to deposit an oxide layer to cover the groove.
In the manufacturing method of the shielded gate field effect transistor, the step (13) is specifically that an interlayer dielectric layer is arranged by utilizing a back-end process, and a source electrode is formed on the top of the device by P + injection and metal connecting wires.
The invention also provides a shielded gate field effect transistor manufactured by the manufacturing method, wherein the thickness of the bottom dielectric layer is 0.7-1.7 mu m.
By adopting the shielded gate field effect transistor and the manufacturing method thereof, the stepped groove is formed firstly, the bottom oxide layer is formed at the bottom of the groove, and the shielded gate oxide layer is formed on the surface of the groove, so that the thickness of the oxide layer at the bottom of the shielded gate is thicker than other positions, the purpose of weakening the electric field at the bottom of the shielded gate is achieved, the bottom breakdown of the shielded gate is avoided, the appearance of the gate structure is changed, the current conduction path is optimized, and the durability of the device is improved.
Drawings
Fig. 1 is a schematic diagram of a conventional trench vertical field effect transistor.
Fig. 2 is a schematic diagram of a trench field effect transistor with a shielded gate structure in the prior art.
Fig. 3 is a schematic diagram of a bottom breakdown point of a shielded gate of a trench fet with a shielded gate structure in the prior art.
Fig. 4 is a flow chart of the shielded gate field effect transistor and the manufacturing method thereof according to the present invention.
FIG. 5 is a schematic view of the EPI growth process in the shielded gate field effect transistor and the method of fabricating the same according to the present invention.
FIG. 6 is a schematic diagram of a first etching process in the shielded gate field effect transistor and the method of fabricating the same according to the present invention.
FIG. 7 is a schematic diagram of a second etching process in the shielded gate field effect transistor and the method for fabricating the same according to the present invention.
Fig. 8 is a schematic diagram of a third etching process in the shielded gate field effect transistor and the method for manufacturing the same according to the present invention.
FIG. 9 is a schematic diagram of a bottom oxide layer formed in a shielded gate field effect transistor and a method of fabricating the same according to the present invention.
FIG. 10 is a schematic diagram of a shielded gate field effect transistor and a method for fabricating the same according to the present invention with the mask and a portion of the bottom oxide layer removed.
Fig. 11 is a schematic view of a shielded gate field effect transistor and a method for manufacturing the same according to the present invention, wherein a shielded gate oxide layer is formed on the surface of a trench.
Fig. 12 is a schematic diagram of a shielded gate field effect transistor and method of making the same according to the present invention with shield gate poly deposition and etch back in the trench.
FIG. 13 is a schematic diagram of a shielded gate field effect transistor and a method of fabricating the same according to the present invention in which an oxide layer is deposited to cover the trench.
Fig. 14 is a schematic diagram of the shielded gate field effect transistor and the method for manufacturing the same according to the present invention, wherein the device gate etching, gate oxidation, polysilicon deposition and etching are performed.
FIG. 15 is a schematic diagram of P-body implantation and annealing in the shielded gate field effect transistor and method of fabricating the same according to the present invention.
FIG. 16 is a schematic diagram of a shielded gate field effect transistor and a method of fabricating the same according to the present invention with an N + implant.
Fig. 17 is a schematic structural diagram of a shielded gate field effect transistor according to the present invention.
Fig. 18 is a bottom electric field distribution comparison diagram of the shielded gate field effect transistor of the present invention and a conventional shielded gate field effect transistor.
FIG. 19 is a schematic diagram of the current path in the JFET region of the shielded gate field effect transistor of the present invention.
Detailed Description
In order to clearly understand the technical contents of the present invention, the following examples are given in detail.
Fig. 4 is a schematic flow chart of a shielded gate field effect transistor and a method for manufacturing the same according to the present invention.
In one embodiment, the method of manufacturing a shielded gate field effect transistor includes the steps of:
(1) as shown in fig. 5, an N-region is generated on an N + substrate as a drain using an epitaxial growth process;
(2) as shown in fig. 6, a silicon nitride mask is arranged on the N-region to perform a first etching to form a trench in the N-region;
(3) as shown in fig. 7, a silicon nitride mask is arranged on the inner wall of the trench to perform a second etching to deepen the trench;
(4) as shown in fig. 8, a mask is further disposed on the inner wall of the deepened trench for the third etching, and then the trench is deepened to form a step trench and the bottom of the trench;
(5) as shown in fig. 9, a bottom dielectric layer is formed at the bottom of the trench;
(6) as shown in fig. 10, removing the mask and a part of the bottom dielectric layer;
(7) as shown in fig. 11, a shielding gate dielectric layer is formed on the surface of the trench;
(8) as shown in fig. 12, performing poly deposition and etching back of the shield gate in the trench;
(9) as shown in fig. 13, depositing a dielectric layer to cover the trench;
(10) as shown in fig. 14, performing device gate etching, gate oxidation, polysilicon deposition and etching to form a gate electrode on the top of the trench;
(11) as shown in fig. 15, P-body implantation and annealing are performed on the top of the N-region to form a P-body region;
(12) as shown in fig. 16, N + implant is performed along the channel at the top of the P-body region;
(13) as shown in fig. 17, a source is formed on top of the device using a back end of line process.
In a preferred embodiment of the present invention,
specifically, the step (5) is to form a bottom oxide layer at the bottom of the trench by thermal oxygen growth.
And (7) specifically, forming a shielding gate oxide layer on the surface of the trench through thermal oxygen growth.
And (9) specifically, depositing an oxide layer to cover the groove.
And (13) specifically, setting an interlayer dielectric layer by utilizing a back-end process, and forming a source electrode on the top of the device by P + injection and metal connecting lines.
The invention also provides a shielded gate field effect transistor manufactured by the manufacturing method, and the structure of the shielded gate field effect transistor is shown in fig. 17. In a preferred embodiment, the thickness of the bottom dielectric layer is 0.7 to 1.7 μm.
In the application of the present invention, the thickness of the oxide layer at the bottom of the shielding gate can be different according to different applications. The invention can cover a wide application range of 20V-250V, taking 100V application as an example, the thickness of an oxide layer at the bottom of a shielding grid in the traditional technology is approximately in the range of 0.5-0.7 um, and the thickness of the invention is approximately 1.2-2 times of the thickness of the traditional technology;
increasing the thickness of the bottom oxide layer can, on the one hand, take up a larger electric field and thus achieve a higher breakdown voltage. The bottom electric field distribution of the present invention is comparable to that of the conventional structure as shown in fig. 18. The thicker bottom silicon dioxide in the invention can effectively reduce the electric field intensity in the N-epitaxial layer (silicon) (the electric field intensity E1 of the invention is less than the electric field intensity E2 of the traditional structure), and further can reach the critical electric field later, thereby obtaining higher breakdown voltage.
On the other hand, the parasitic capacitance between the drain electrode and the source electrode can be further reduced by increasing the thickness of the bottom oxide layer; according to the theory of plate capacitance, C ═ ea/d, where e is the dielectric constant of the dielectric layer silica, a is the area, and d is the dielectric layer thickness, so C isdsDecreases with increasing dielectric layer thickness d.
Meanwhile, as shown in fig. 19, the shielded gate field effect transistor of the invention changes the appearance of the gate structure, so that the current path of the JFET region is wider and the resistance is smaller.
By adopting the shielded gate field effect transistor and the manufacturing method thereof, the stepped groove is formed firstly, the bottom oxide layer is formed at the bottom of the groove, and the shielded gate oxide layer is formed on the surface of the groove, so that the thickness of the oxide layer at the bottom of the shielded gate is thicker than other positions, the purpose of weakening the electric field at the bottom of the shielded gate is achieved, the bottom breakdown of the shielded gate is avoided, the appearance of the gate structure is changed, the current conduction path is optimized, and the durability of the device is improved.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (8)
1. A method of fabricating a shielded gate field effect transistor, the method comprising the steps of:
(1) an N-region is generated on an N + substrate serving as a drain electrode by utilizing an epitaxial growth process;
(2) arranging a mask on the N-region for carrying out first etching to form a groove in the N-region;
(3) arranging a mask on the inner wall of the groove to carry out secondary etching to deepen the groove;
(4) arranging a mask plate on the inner wall of the deepened groove to perform third etching, deepening the groove to form a stepped groove and forming the bottom of the groove;
(5) forming a bottom dielectric layer at the bottom of the groove;
(6) removing the mask and part of the bottom dielectric layer;
(7) forming a shielding gate dielectric layer on the surface of the groove;
(8) carrying out polycrystalline deposition and back etching on the shielding grid in the groove;
(9) depositing a dielectric layer to cover the groove;
(10) performing device gate etching, gate oxidation, polysilicon deposition and etching to form a gate at the top of the trench;
(11) injecting and annealing a P-body region at the top of the N-region to form the P-body region;
(12) performing N + implantation along the groove at the top of the P-body area;
(13) and forming a source electrode on the top of the device by utilizing a back-end process.
2. The method of claim 1, wherein the mask is silicon nitride.
3. The method of claim 1, wherein step (5) is embodied as,
and forming a bottom oxide layer at the bottom of the trench by thermal oxygen growth.
4. The method of claim 1, wherein step (7) is embodied as,
and forming a shielding gate oxide layer on the surface of the trench through thermal oxygen growth.
5. The method of manufacturing a shielded gate field effect transistor according to claim 1, wherein the step (9) is embodied as,
and depositing an oxide layer to cover the groove.
6. The method of manufacturing a shielded gate field effect transistor according to claim 1, wherein the step (13) is embodied as,
and (3) setting an interlayer dielectric layer, injecting P + and forming a source electrode on the top of the device by utilizing a back-end process.
7. A shielded gate field effect transistor formed by the method of any one of claims 1 to 6.
8. The shielded gate field effect transistor of claim 7 wherein the thickness of the bottom dielectric layer is 0.7 to 1.7 μm.
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| CN112864019A (en) * | 2019-11-28 | 2021-05-28 | 苏州东微半导体股份有限公司 | Method for manufacturing semiconductor power device and semiconductor power device |
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| JPH09283535A (en) * | 1996-04-18 | 1997-10-31 | Toyota Motor Corp | Manufacture of semiconductor device |
| KR20010019154A (en) * | 1999-08-25 | 2001-03-15 | 김영환 | Manufacturing Method for MOS Transistor |
| CN101889327A (en) * | 2007-12-04 | 2010-11-17 | 威世通用半导体公司 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
| CN106783620A (en) * | 2016-12-05 | 2017-05-31 | 西安龙腾新能源科技发展有限公司 | Hyperconjugation VDMOS device structure of anti-EMI filter and preparation method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09283535A (en) * | 1996-04-18 | 1997-10-31 | Toyota Motor Corp | Manufacture of semiconductor device |
| KR20010019154A (en) * | 1999-08-25 | 2001-03-15 | 김영환 | Manufacturing Method for MOS Transistor |
| CN101889327A (en) * | 2007-12-04 | 2010-11-17 | 威世通用半导体公司 | Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands |
| CN106783620A (en) * | 2016-12-05 | 2017-05-31 | 西安龙腾新能源科技发展有限公司 | Hyperconjugation VDMOS device structure of anti-EMI filter and preparation method thereof |
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