WO2022037457A1 - Sic power device and manufacturing method therefor - Google Patents

Sic power device and manufacturing method therefor Download PDF

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Publication number
WO2022037457A1
WO2022037457A1 PCT/CN2021/112087 CN2021112087W WO2022037457A1 WO 2022037457 A1 WO2022037457 A1 WO 2022037457A1 CN 2021112087 W CN2021112087 W CN 2021112087W WO 2022037457 A1 WO2022037457 A1 WO 2022037457A1
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Prior art keywords
ion implantation
implantation region
dielectric layer
gate
layer
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PCT/CN2021/112087
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French (fr)
Chinese (zh)
Inventor
李立均
林科闯
郭元旭
彭志高
陶永洪
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厦门市三安集成电路有限公司
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Publication of WO2022037457A1 publication Critical patent/WO2022037457A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the technical field of semiconductors, and in particular, to a SiC power device and a manufacturing method thereof.
  • silicon carbide As an important third-generation semiconductor material, silicon carbide has the advantages of high forbidden band width, high critical breakdown electric field, and high thermal conductivity. Silicon carbide power devices have very broad application prospects in new energy vehicles, photovoltaic power generation, high-speed rail and other fields.
  • SiC MOSFETs Silicon carbide metal oxide semiconductor field effect transistors
  • SiC MOSFETs have one to two orders of magnitude higher number of interface states than silicon-based MOSFETs due to the gate oxide process.
  • the gate operating voltage of the SiC MOSFET is much higher than the gate operating voltage of the Si-based MOSFET when the SiC MOSFET is conducting forward, which makes the electric field of the gate oxide layer higher when the SiC MOSFET works, resulting in The lifetime and reliability of the gate oxide is much lower than that of Si MOSFETs.
  • the length of the gate electrode due to the alignment error of the process, the length of the gate electrode usually exceeds the P-channel, and a part of it covers the top of the N+ doped region.
  • the surface of the N+ ion implantation region is in the The accumulation state has a serious electric field concentration effect, so that the electric field strength of the gate oxide layer located between the gate edge and the N+ ion implantation region is much larger than that in the gate oxide layer at other positions.
  • the gate oxide layer between the N+ ion implanted regions is severely degraded, so that it breaks down early, which becomes a weak point of the SiC MOSFET and shortens the service life of the device body.
  • the purpose of the present invention is to overcome the deficiencies of the prior art, and to provide a SiC power device and a manufacturing method thereof.
  • a SiC power device comprising a drain electrode, a substrate and an epitaxial layer arranged from bottom to top, and a gate electrode and a source electrode arranged above the epitaxial layer; an implantation area, the upper middle area of the P- ion implantation area is provided with a P+ ion implantation area and an N+ ion implantation area, and the N+ ion implantation area is located on both sides or around the P+ ion implantation area; the gate The electrode extends from two sides or around the upper part of the epitaxial layer to the end located above the N+ ion implantation region, wherein the gate is located between the part outside the N+ ion implantation region and the epitaxial layer.
  • an additional dielectric layer is arranged between the part located in the N+ ion implantation region and the N+ ion implantation region, and the thickness of the additional dielectric layer is greater than the thickness of the gate oxide layer; the The source electrode is in contact with the P+ ion implantation region and part of the N+ ion implantation region and extends above the gate electrode, and an interlayer dielectric layer is provided between the source electrode and the gate electrode.
  • the end of the gate oxide layer corresponds to the edge of the N+ ion implantation region
  • the additional dielectric layer extends from the end of the gate oxide layer to the inside of the N+ ion implantation region, and the thickness gradually increases. large to form a slope.
  • the end of the gate is located on the slope.
  • the additional dielectric layer includes the slope and a platform extending from the slope to a high point toward the inner side of the N+ ion implantation region, and an end of the gate is located on the platform.
  • the slope of the slope is 5° ⁇ 85°.
  • the thickness of the platform is 1.5 to 100 times the thickness of the gate oxide layer.
  • the material of the additional dielectric layer is the same as the material of the gate oxide layer.
  • the manufacturing method of the above-mentioned SiC power device comprises the following steps:
  • An additional dielectric layer is formed in the N+ ion implantation region by a local oxidation process or a chemical vapor deposition process;
  • step 4 depositing an interlayer dielectric layer on the top surface of the structure formed in step 4);
  • a source electrode is formed on the top surface of the structure formed in step 6), and a drain electrode is formed on the bottom surface.
  • step 2) the local oxidation process includes the following steps:
  • the edge of the oxidation window is located inside the edge of the N+ ion implantation region, and in step 2.3), the additional dielectric layer is from the edge of the oxidation window to the N+ ion implantation.
  • the edge of the zone forms a slope.
  • step 2) the additional dielectric layer is formed by a chemical vapor deposition process, and then the edge of the additional dielectric layer is etched to form a slope.
  • the portion of the gate terminal that enters the range of the N+ ion implantation region is located on the additional dielectric layer, and the thickness of the additional dielectric layer is greater than that of the gate oxide layer, thereby increasing the gap between the gate terminal and the N+ ion implantation region.
  • the thickness of the dielectric layer between the SiC power devices reduces the maximum electric field strength of the electric field gathering region at the gate edge when the SiC power device operates, and improves the gate-source reliability of the SiC power device.
  • FIG. 1 is a schematic structural diagram of the SiC MOSFET power device of Embodiment 1;
  • Fig. 2 is the process flow schematic diagram of the SiC MOSFET power device of embodiment 1;
  • Fig. 3 is the structural schematic diagram of the SiC MOSFET power device of the comparative example
  • Example 4 is the electric field simulation test results of Example 1 and the comparative example, wherein 4A is the electric field distribution of the gate oxide layer between the N+ ion implantation region and the gate terminal when the device of Example 1 is working; 4B is the operation of the device of the comparative example , the electric field distribution of the gate oxide layer between the N+ ion implantation region and the gate terminal; 4C is the gate oxide layer between the N+ ion implantation region and the gate terminal when the devices of Example 1 (curve a) and the comparative example (curve b) work. Comparing the electric field of the oxide layer, it can be seen that Example 1 greatly reduces the electric field peak value when the device is working;
  • FIG. 6 is a schematic structural diagram of the SiC MOSFET power device of Example 3.
  • FIG. 6 is a schematic structural diagram of the SiC MOSFET power device of Example 3.
  • a SiC MOSFET power device 1 with high reliability gate-source includes a drain 100, an N+SiC substrate 101 and an N-SiC epitaxial layer 102 arranged from bottom to top, and the middle of the upper part of the epitaxial layer 102
  • the region is provided with a P-ion implantation region 103
  • the upper middle region of the P-ion implantation region 103 is provided with a P+ ion implantation region 105 and an N+ ion implantation region 104
  • the N+ ion implantation region 104 is located on both sides of the P+ ion implantation region 105 or around.
  • a gate electrode 108 and a source electrode 110 are arranged above the epitaxial layer 102, wherein: the gate electrode 108 extends from two sides or around the top of the epitaxial layer 102 to the end located above the N+ ion implantation region 104, and the gate electrode 108 is located in the N+ ion implantation region.
  • a gate oxide layer 107 is provided between the part outside 104 and the epitaxial layer 102, and an additional dielectric layer 106 is provided between the part located within the N+ ion implantation region 104 and the N+ ion implantation region 104, and the thickness of the additional dielectric layer 106 greater than the thickness of the gate oxide layer 107 ; the source electrode 110 is in contact with the P+ ion implantation region 105 and part of the N+ ion implantation region 104 and extends above the gate electrode 108 .
  • the P- ion implantation region 103 and the N+ ion implantation region 104 together form the channel region of the device, the ohmic metal and the N+ ion implantation region 104 form a source ohmic contact, and the P+ ion implantation region 105 forms an ohmic contact with the source metal.
  • the N+ ion implantation region 104 and the P+ ion implantation region 105 have the same potential to suppress the turn-on of the parasitic transistor of the MOSFET.
  • the materials of the gate oxide layer 107 and the additional dielectric layer 106 are both SiO 2 .
  • the gate oxide layer 107 extends from both sides of the epitaxial layer 102 to the edge of the N+ ion implantation region 104 , and the additional dielectric layer 106 extends from the end of the gate oxide layer 107 to the inside of the N+ ion implantation region 104 , and the thickness gradually increases to form a slope 1061 .
  • the slope of the ramp 1061 ranges from 5° to 85°, eg, 20° to 60°.
  • the end of the gate 108 is located on the slope 1061, so that the portion of the end of the gate 108 entering the N+ ion implantation region 104 is located on the additional dielectric layer 106 which is thicker relative to the gate oxide layer 107, which increases the size of the connection between the end of the gate 108 and the N+ ion implantation region 104.
  • the thickness of the dielectric layer between the ion implantation regions 104 reduces the maximum electric field strength of the fringe electric field gathering region of the gate 108 during operation of the SiC MOSFET, thereby improving the gate-source reliability of the SiC MOSFET.
  • the setting of the slope avoids the problem of stress concentration at the tip caused by the sudden change of thickness, and further improves the reliability.
  • Step 1 referring to 2a, growing an epitaxial layer 102 on the substrate 101, and forming a P- ion implantation region 103, an N+ ion implantation region 104 and a P+ ion implantation region 105 on the epitaxial layer through an ion implantation process;
  • Step 2 referring to 2b, depositing a first oxide layer 111 (eg, SiO 2 ) with a thickness of 20-50 nm; depositing silicon nitride to form a mask layer 112 , etching the mask layer 112 to form an oxide window 112 a, and the edge of the oxide window 112 a is located at The inner side of the N+ ion implantation region 104, that is, there is a certain distance from the edge of the N+ ion implantation region 104; with reference to 2c, the structure within the oxidation window 112a is partially oxidized to form the additional dielectric layer 106.
  • a first oxide layer 111 eg, SiO 2
  • the oxidation range extends laterally from the edge of the oxidation window 112a and the oxidation degree gradually decreases, and the additional dielectric layer 106 formed by controlling the oxidation time and temperature forms the structure of the slope 1061 from the edge of the oxidation window 112a to the edge of the N+ ion implantation region 104; Referring to 2d, remove the mask layer 112 and the first oxide layer 111;
  • a gate oxide layer 107 is formed on the outside of the N+ ion implantation region by an oxidation process; in this embodiment, the gate oxide layer 107 and the additional dielectric layer 106 are both formed by an oxidation process, with the same materials and no obvious boundaries. Therefore, it can also be considered that the thickness of the end of the gate oxide layer 107 increases to form the additional dielectric layer 106;
  • Step 4 referring to 2f, depositing polysilicon and etching the polysilicon to form the gate 108, so that the boundary of the gate 108 is located on the slope 1061 of the additional dielectric layer 106;
  • Step 5 referring to 2g, deposit an interlayer dielectric layer 109 on the top surface of the above structure, and the material of the interlayer dielectric layer 109 is, for example, SiN, SiO 2 , etc.;
  • Step 6 referring to 2h, etching the interlayer dielectric layer 109 and the additional dielectric layer 106 to form source contact holes 109a that expose the P+ ion implantation region 105 and part of the N+ ion implantation region 104;
  • Step 7 referring to 2i, depositing metal on the top surface of the above structure to form the source electrode 110, and the bottom surface to form the drain electrode 100.
  • the thickness of the gate oxide layer 107 is a conventional thickness, which is 20-100 nm, for example, 50 nm, and the slope of the slope 1061 is 45°.
  • the thickness of the gate oxide layer 107 is uniformly extended into the N+ ion implantation region (ie, the position of the additional dielectric layer).
  • the electric field simulation of Example 1 and the comparative example is carried out. It can be seen from FIG. 4 that the structure of the present invention significantly reduces the high electric field peak value caused by the fringe electric field gathering effect of the gate 108 .
  • the additional dielectric layer 106 includes a slope 1061 and a platform extending from the slope 1061 to a high point to the inside of the N+ ion implantation region 104
  • the gate 108 ′ crosses the ramp and ends on the platform 1062 .
  • the thickness of the platform 1062 is the overall thickness of the additional dielectric layer 106.
  • the structure of this embodiment is realized by setting the distance between the edge of the oxidation window 112a and the edge of the N+ ion implantation region 104 in Embodiment 1 and adjusting the oxidation parameters.
  • the thickness of the platform 1062 is 1.5-100 times the thickness of the gate oxide layer 107, for example, 6 times can achieve better results.
  • a SiC MOSFET power device 3 with high reliability gate source is different from Embodiment 1 in that the additional dielectric layer 106 ′ is not formed by a local oxidation process, but is deposited on the surface of the epitaxial layer 102 by a CVD process A thick SiO2 layer is then formed by etching to form an additional dielectric layer 106' with an angled slope 1061'.

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Abstract

Disclosed in the present invention is a SiC power device, comprising a drain, a substrate, and an epitaxial layer which are disposed from bottom to top, and a gate and a source which are disposed above the epitaxial layer. The epitaxial layer is provided with a P- ion implantation area, a P+ ion implantation area, and an N+ ion implantation area; a gate oxide layer is provided between the part of the gate located outside the N+ ion implantation area and the epitaxial layer, and an additional dielectric layer is provided between the part of the end of the gate located in the N+ ion implantation area and the N+ ion implantation area; the thickness of the additional dielectric layer is greater than the thickness of the gate oxide layer. Also disclosed in the present invention is a manufacturing method for the structure above. According to the present invention, the thickness of the dielectric layer between the edge of the gate and the N+ ion implantation area is increased, the maximum electric field of the dielectric layer between the edge of the gate and the N+ ion implantation area during forward conduction of the device is reduced, and the gate-source reliability is improved.

Description

一种SiC功率器件及其制造方法A kind of SiC power device and its manufacturing method 技术领域technical field
本发明涉及半导体技术领域，尤其涉及一种SiC功率器件及其制造方法。The present invention relates to the technical field of semiconductors, and in particular, to a SiC power device and a manufacturing method thereof.
背景技术Background technique
碳化硅作为重要的第三代半导体材料具有高禁带宽度、高临界击穿电场、高热导率等优势。碳化硅功率器件在新能源汽车、光伏发电、高铁等领域有着非常广阔的应用前景。As an important third-generation semiconductor material, silicon carbide has the advantages of high forbidden band width, high critical breakdown electric field, and high thermal conductivity. Silicon carbide power devices have very broad application prospects in new energy vehicles, photovoltaic power generation, high-speed rail and other fields.
碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET)由于栅氧工艺的影响，界面态数量比硅基MOSFET高一到两个数量级。为了获得较小的正向导通电阻，SiC MOSFET正向导通时栅极工作电压要远高于Si基MOSFET的栅极工作电压，这就使得SiC MOSFET工作时栅氧化层的电场较高，导致了栅氧化层的寿命和可靠性远低于Si MOSFET。同时对于平面型MOSFET，由于工艺的对准误差，通常栅电极长度会超过P沟道，有一部分覆盖到N+掺杂区域的上方，在栅极正向电压情况下，N+离子注入区域的表面处于积累状态，具有严重的电场聚集效应，使得位于栅极边缘和N+离子注入区域之间的栅氧化层的电场强度远远大于其他位置栅氧化层中的电场强度，在高电场下，栅极与N+离子注入区域之间的栅氧化层退化严重，以致提前击穿，成为SiC MOSFET的一个薄弱点，缩短了器件本体的使用寿命。Silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) have one to two orders of magnitude higher number of interface states than silicon-based MOSFETs due to the gate oxide process. In order to obtain a smaller forward conduction resistance, the gate operating voltage of the SiC MOSFET is much higher than the gate operating voltage of the Si-based MOSFET when the SiC MOSFET is conducting forward, which makes the electric field of the gate oxide layer higher when the SiC MOSFET works, resulting in The lifetime and reliability of the gate oxide is much lower than that of Si MOSFETs. At the same time, for planar MOSFETs, due to the alignment error of the process, the length of the gate electrode usually exceeds the P-channel, and a part of it covers the top of the N+ doped region. In the case of the gate forward voltage, the surface of the N+ ion implantation region is in the The accumulation state has a serious electric field concentration effect, so that the electric field strength of the gate oxide layer located between the gate edge and the N+ ion implantation region is much larger than that in the gate oxide layer at other positions. The gate oxide layer between the N+ ion implanted regions is severely degraded, so that it breaks down early, which becomes a weak point of the SiC MOSFET and shortens the service life of the device body.
技术解决方案technical solutions
本发明的目的在于克服现有技术存在的不足，提供一种SiC功率器件及其制造方法。The purpose of the present invention is to overcome the deficiencies of the prior art, and to provide a SiC power device and a manufacturing method thereof.
为了实现以上目的，本发明的技术方案为：In order to achieve the above purpose, the technical scheme of the present invention is:
一种SiC功率器件，包括由下至上设置的漏极、衬底和外延层，以及设于所述外延层上方的栅极和源极；所述外延层的上部的中间区域设有P-离子注入区，所述P-离子注入区的上部的中间区域设有P+离子注入区和N+离子注入区，且所述N+离子注入区位于所述P+离子注入区的两侧或周围；所述栅极由所述外延层的上方的两侧或周围延伸至末端位于所述N+离子注入区的上方，其中所述栅极位于所述N+离子注入区之外的部分与所述外延层之间设有栅氧化层，位于所述N+离子注入区之内的部分与所述N+离子注入区之间设有附加介质层，且所述附加介质层的厚度大于所述栅氧化层的厚度；所述源极与所述P+离子注入区和部分N+离子注入区接触且延伸至所述栅极上方，所述源极和所述栅极之间设有层间介质层。A SiC power device, comprising a drain electrode, a substrate and an epitaxial layer arranged from bottom to top, and a gate electrode and a source electrode arranged above the epitaxial layer; an implantation area, the upper middle area of the P- ion implantation area is provided with a P+ ion implantation area and an N+ ion implantation area, and the N+ ion implantation area is located on both sides or around the P+ ion implantation area; the gate The electrode extends from two sides or around the upper part of the epitaxial layer to the end located above the N+ ion implantation region, wherein the gate is located between the part outside the N+ ion implantation region and the epitaxial layer. There is a gate oxide layer, an additional dielectric layer is arranged between the part located in the N+ ion implantation region and the N+ ion implantation region, and the thickness of the additional dielectric layer is greater than the thickness of the gate oxide layer; the The source electrode is in contact with the P+ ion implantation region and part of the N+ ion implantation region and extends above the gate electrode, and an interlayer dielectric layer is provided between the source electrode and the gate electrode.
可选的，所述栅氧化层的末端与所述N+离子注入区的边缘相对应，所述附加介质层由所述栅氧化层的末端向所述N+离子注入区内侧延伸，且厚度渐次增大以形成斜坡。Optionally, the end of the gate oxide layer corresponds to the edge of the N+ ion implantation region, and the additional dielectric layer extends from the end of the gate oxide layer to the inside of the N+ ion implantation region, and the thickness gradually increases. large to form a slope.
可选的，所述栅极的末端位于所述斜坡上。Optionally, the end of the gate is located on the slope.
可选的，所述附加介质层包括所述斜坡和由所述斜坡至高点向所述N+离子注入区内侧延伸的平台，所述栅极的末端位于所述平台上。Optionally, the additional dielectric layer includes the slope and a platform extending from the slope to a high point toward the inner side of the N+ ion implantation region, and an end of the gate is located on the platform.
可选的，所述斜坡的坡度为5°～85°。Optionally, the slope of the slope is 5°˜85°.
可选的，所述平台的厚度是所述栅氧化层厚度的1.5～100倍。Optionally, the thickness of the platform is 1.5 to 100 times the thickness of the gate oxide layer.
可选的，所述附加介质层的材料与所述栅氧化层的材料相同。Optionally, the material of the additional dielectric layer is the same as the material of the gate oxide layer.
上述SiC功率器件的制造方法包括以下步骤：The manufacturing method of the above-mentioned SiC power device comprises the following steps:
1)于衬底上生长外延层，通过多次离子注入于外延层上形成P-离子注入区、N+离子注入区和P+离子注入区；1) growing an epitaxial layer on the substrate, and forming a P- ion implantation region, an N+ ion implantation region and a P+ ion implantation region on the epitaxial layer by multiple ion implantation;
2)通过局部氧化工艺或化学气相沉积工艺于N+离子注入区之内形成附加介质层；2) An additional dielectric layer is formed in the N+ ion implantation region by a local oxidation process or a chemical vapor deposition process;
3)于N+离子注入区外侧形成栅氧化层；3) forming a gate oxide layer outside the N+ ion implantation region;
4)于栅氧化层和附加介质层上形成栅极；4) forming a gate on the gate oxide layer and the additional dielectric layer;
5)于步骤4)形成的结构顶面沉积层间介质层；5) depositing an interlayer dielectric layer on the top surface of the structure formed in step 4);
6)蚀刻层间介质层和附加介质层形成裸露P+离子注入区和部分N+离子注入区的源极接触孔；6) Etch the interlayer dielectric layer and the additional dielectric layer to form source contact holes that expose the P+ ion implantation region and part of the N+ ion implantation region;
7)分别于步骤6)形成的结构的顶面形成源极，底面形成漏极。7) A source electrode is formed on the top surface of the structure formed in step 6), and a drain electrode is formed on the bottom surface.
可选的，步骤2)中，所述局部氧化工艺包括以下步骤：Optionally, in step 2), the local oxidation process includes the following steps:
2.1)沉积厚度为20-50nm的第一氧化层；2.1) deposit a first oxide layer with a thickness of 20-50nm;
2.2)形成掩膜层，蚀刻所述掩膜层形成氧化窗口；2.2) forming a mask layer, and etching the mask layer to form an oxidation window;
2.3)对所述氧化窗口之内的结构进行局部氧化，形成所述附加介质层；2.3) Partially oxidize the structure within the oxidation window to form the additional dielectric layer;
2.4)去除所述掩膜层和第一氧化层。2.4) Remove the mask layer and the first oxide layer.
可选的，步骤2.2)中，所述氧化窗口的边缘位于所述N+离子注入区的边缘的内侧，步骤2.3)中，所述附加介质层由所述氧化窗口的边缘至所述N+离子注入区的边缘形成斜坡。Optionally, in step 2.2), the edge of the oxidation window is located inside the edge of the N+ ion implantation region, and in step 2.3), the additional dielectric layer is from the edge of the oxidation window to the N+ ion implantation. The edge of the zone forms a slope.
可选的，步骤2)中，通过化学气相沉积工艺形成所述附加介质层，然后蚀刻所述附加介质层的边缘形成斜坡。Optionally, in step 2), the additional dielectric layer is formed by a chemical vapor deposition process, and then the edge of the additional dielectric layer is etched to form a slope.
有益效果beneficial effect
本发明的有益效果为：The beneficial effects of the present invention are:
通过附加介质层的设置，栅极末端进入N+离子注入区范围内的部分位于附加介质层上，附加介质层的厚度大于栅氧化层的厚度，从而增大了栅极末端与N+离子注入区之间的介质层的厚度，减小了SiC功率器件工作时的栅极边缘电场聚集区的最大电场强度，提高了SiC功率器件的栅源可靠性。Through the setting of the additional dielectric layer, the portion of the gate terminal that enters the range of the N+ ion implantation region is located on the additional dielectric layer, and the thickness of the additional dielectric layer is greater than that of the gate oxide layer, thereby increasing the gap between the gate terminal and the N+ ion implantation region. The thickness of the dielectric layer between the SiC power devices reduces the maximum electric field strength of the electric field gathering region at the gate edge when the SiC power device operates, and improves the gate-source reliability of the SiC power device.
附图说明Description of drawings
图1为实施例1的SiC MOSFET功率器件的结构示意图；1 is a schematic structural diagram of the SiC MOSFET power device of Embodiment 1;
图2为实施例1的SiC MOSFET功率器件的工艺流程示意图；Fig. 2 is the process flow schematic diagram of the SiC MOSFET power device of embodiment 1;
图3为对比例的SiC MOSFET功率器件的结构示意图；Fig. 3 is the structural schematic diagram of the SiC MOSFET power device of the comparative example;
图4为实施例1和对比例的电场仿真模拟测试结果，其中4A为实施例1的器件工作时，N+离子注入区与栅极末端之间的栅氧化层电场分布；4B为对比例器件工作时，N+离子注入区与栅极末端之间的栅氧化层电场分布；4C为实施例1(曲线a)与对比例(曲线b)器件工作时N+离子注入区与栅极末端之间的栅氧化层电场的对比，可以看出实施例1极大的减小了器件工作时的电场峰值；4 is the electric field simulation test results of Example 1 and the comparative example, wherein 4A is the electric field distribution of the gate oxide layer between the N+ ion implantation region and the gate terminal when the device of Example 1 is working; 4B is the operation of the device of the comparative example , the electric field distribution of the gate oxide layer between the N+ ion implantation region and the gate terminal; 4C is the gate oxide layer between the N+ ion implantation region and the gate terminal when the devices of Example 1 (curve a) and the comparative example (curve b) work. Comparing the electric field of the oxide layer, it can be seen that Example 1 greatly reduces the electric field peak value when the device is working;
图5为实施例2的SiC MOSFET功率器件的结构示意图；5 is a schematic structural diagram of the SiC MOSFET power device of Embodiment 2;
图6为实施例3的SiC MOSFET功率器件的结构示意图。FIG. 6 is a schematic structural diagram of the SiC MOSFET power device of Example 3. FIG.
本发明的实施方式Embodiments of the present invention
以下结合附图和具体实施例对本发明做进一步解释。本发明的各附图仅为示意以更容易了解本发明，其具体比例可依照设计需求进行调整。文中所描述的图形中相对元件的上下关系以及正面/背面的定义，在本领域技术人员应能理解是指构件的相对位置而言，因此皆可以翻转而呈现相同的构件，此皆应同属本说明书所揭露的范围。The present invention will be further explained below with reference to the accompanying drawings and specific embodiments. The accompanying drawings of the present invention are only schematic diagrams to facilitate the understanding of the present invention, and the specific proportions thereof can be adjusted according to design requirements. Those skilled in the art should understand that the upper and lower relationship of the relative elements in the graphics described in the text and the definition of the front/back side refer to the relative positions of the components, so they can all be turned over to present the same components, which shall belong to the same category. the scope disclosed in the specification.
实施例1Example 1
参考图1，一种具有高可靠性栅源的SiC MOSFET功率器件1，包括由下至上设置的漏极100、N+SiC衬底101和N-SiC外延层102，外延层102的上部的中间区域设有P-离子注入区103，P-离子注入区103的上部的中间区域设有P+离子注入区105和N+离子注入区104，且N+离子注入区104位于P+离子注入区105的两侧或周围。外延层102上方设有栅极108和源极110，其中：栅极108由外延层102的上方的两侧或周围延伸至末端位于N+离子注入区104的上方，栅极108位于N+离子注入区104之外的部分与外延层102之间设有栅氧化层107，位于N+离子注入区104之内的部分与N+离子注入区104之间设有附加介质层106，且附加介质层106的厚度大于栅氧化层107的厚度；源极110与P+离子注入区105和部分N+离子注入区104接触且延伸至栅极108上方，源极110和栅极108之间设有层间介质层109。Referring to FIG. 1, a SiC MOSFET power device 1 with high reliability gate-source includes a drain 100, an N+SiC substrate 101 and an N-SiC epitaxial layer 102 arranged from bottom to top, and the middle of the upper part of the epitaxial layer 102 The region is provided with a P-ion implantation region 103, the upper middle region of the P-ion implantation region 103 is provided with a P+ ion implantation region 105 and an N+ ion implantation region 104, and the N+ ion implantation region 104 is located on both sides of the P+ ion implantation region 105 or around. A gate electrode 108 and a source electrode 110 are arranged above the epitaxial layer 102, wherein: the gate electrode 108 extends from two sides or around the top of the epitaxial layer 102 to the end located above the N+ ion implantation region 104, and the gate electrode 108 is located in the N+ ion implantation region. A gate oxide layer 107 is provided between the part outside 104 and the epitaxial layer 102, and an additional dielectric layer 106 is provided between the part located within the N+ ion implantation region 104 and the N+ ion implantation region 104, and the thickness of the additional dielectric layer 106 greater than the thickness of the gate oxide layer 107 ; the source electrode 110 is in contact with the P+ ion implantation region 105 and part of the N+ ion implantation region 104 and extends above the gate electrode 108 .
其中，P-离子注入区103与N+离子注入区104共同形成器件的沟道区，欧姆金属与N+离子注入区104形成源极欧姆接触，P+离子注入区105与源极金属形成欧姆接触，将N+离子注入区104和P+离子注入区105等电位，抑制MOSFET寄生三极管的开启。栅氧化层107和附加介质层106的材料均为SiO 2。栅氧化层107由外延层102两侧延伸至N+离子注入区104的边缘，附加介质层106由栅氧化层107的末端向N+离子注入区104内侧延伸，且厚度渐次增大以形成斜坡1061。斜坡1061的坡度范围为5°到85°，例如20°到60°。栅极108的末端位于斜坡1061上，从而栅极108末端进入N+离子注入区104范围内的部分位于相对于栅氧化层107更厚的附加介质层106上，增大了栅极108末端与N+离子注入区104之间的介质层的厚度，减小了SiC MOSFET工作时的栅极108边缘电场聚集区的最大电场强度，提高SiC MOSFET的栅源可靠性。其中斜坡的设置，避免了厚度突变造成的尖端应力集中等问题，进一步提高了可靠性。 Among them, the P- ion implantation region 103 and the N+ ion implantation region 104 together form the channel region of the device, the ohmic metal and the N+ ion implantation region 104 form a source ohmic contact, and the P+ ion implantation region 105 forms an ohmic contact with the source metal. The N+ ion implantation region 104 and the P+ ion implantation region 105 have the same potential to suppress the turn-on of the parasitic transistor of the MOSFET. The materials of the gate oxide layer 107 and the additional dielectric layer 106 are both SiO 2 . The gate oxide layer 107 extends from both sides of the epitaxial layer 102 to the edge of the N+ ion implantation region 104 , and the additional dielectric layer 106 extends from the end of the gate oxide layer 107 to the inside of the N+ ion implantation region 104 , and the thickness gradually increases to form a slope 1061 . The slope of the ramp 1061 ranges from 5° to 85°, eg, 20° to 60°. The end of the gate 108 is located on the slope 1061, so that the portion of the end of the gate 108 entering the N+ ion implantation region 104 is located on the additional dielectric layer 106 which is thicker relative to the gate oxide layer 107, which increases the size of the connection between the end of the gate 108 and the N+ ion implantation region 104. The thickness of the dielectric layer between the ion implantation regions 104 reduces the maximum electric field strength of the fringe electric field gathering region of the gate 108 during operation of the SiC MOSFET, thereby improving the gate-source reliability of the SiC MOSFET. The setting of the slope avoids the problem of stress concentration at the tip caused by the sudden change of thickness, and further improves the reliability.
参考图2，以下具体说明上述功率器件1的制造方法。Referring to FIG. 2 , the manufacturing method of the above-mentioned power device 1 will be specifically described below.
步骤1，参考2a，于衬底101上生长外延层102，通过离子注入工艺于外延层上形成P-离子注入区103、N+离子注入区104和P+离子注入区105；Step 1, referring to 2a, growing an epitaxial layer 102 on the substrate 101, and forming a P- ion implantation region 103, an N+ ion implantation region 104 and a P+ ion implantation region 105 on the epitaxial layer through an ion implantation process;
步骤2，参考2b，沉积厚度为20-50nm的第一氧化层111(例如SiO 2 )；沉积氮化硅形成掩膜层112，蚀刻掩膜层112形成氧化窗口112a，氧化窗口112a的边缘位于N+离子注入区104内侧，即与N+离子注入区104边缘具有一定的距离；参考2c，对氧化窗口112a之内的结构进行局部氧化形成附加介质层106，具体可参考Si中的LOCOS工艺。其中，氧化范围由氧化窗口112a边缘横向延伸且氧化程度逐渐减少，通过控制氧化时间及温度使得形成的附加介质层106由氧化窗口112a的边缘至N+离子注入区104的边缘形成斜坡1061的结构；参考2d，去除掩膜层112和第一氧化层111； Step 2, referring to 2b, depositing a first oxide layer 111 (eg, SiO 2 ) with a thickness of 20-50 nm; depositing silicon nitride to form a mask layer 112 , etching the mask layer 112 to form an oxide window 112 a, and the edge of the oxide window 112 a is located at The inner side of the N+ ion implantation region 104, that is, there is a certain distance from the edge of the N+ ion implantation region 104; with reference to 2c, the structure within the oxidation window 112a is partially oxidized to form the additional dielectric layer 106. For details, refer to the LOCOS process in Si. Wherein, the oxidation range extends laterally from the edge of the oxidation window 112a and the oxidation degree gradually decreases, and the additional dielectric layer 106 formed by controlling the oxidation time and temperature forms the structure of the slope 1061 from the edge of the oxidation window 112a to the edge of the N+ ion implantation region 104; Referring to 2d, remove the mask layer 112 and the first oxide layer 111;
步骤3，参考2e，通过氧化工艺于N+离子注入区外侧形成栅氧化层107；本实施例中，栅氧化层107和附加介质层106均是采用氧化工艺形成的，材料相同，无明显边界，因此，也可以认为是栅氧化层107末端厚度增加形成附加介质层106；In step 3, referring to 2e, a gate oxide layer 107 is formed on the outside of the N+ ion implantation region by an oxidation process; in this embodiment, the gate oxide layer 107 and the additional dielectric layer 106 are both formed by an oxidation process, with the same materials and no obvious boundaries. Therefore, it can also be considered that the thickness of the end of the gate oxide layer 107 increases to form the additional dielectric layer 106;
步骤4，参考2f，沉淀多晶硅并蚀刻多晶硅形成栅极108，使得栅极108的边界位于附加介质层106的斜坡1061上；Step 4, referring to 2f, depositing polysilicon and etching the polysilicon to form the gate 108, so that the boundary of the gate 108 is located on the slope 1061 of the additional dielectric layer 106;
步骤5，参考2g，沉积层间介质层109于上述结构的顶面，层间介质层109的材料为例如SiN，SiO 2等； Step 5, referring to 2g, deposit an interlayer dielectric layer 109 on the top surface of the above structure, and the material of the interlayer dielectric layer 109 is, for example, SiN, SiO 2 , etc.;
步骤6，参考2h，蚀刻层间介质层109和附加介质层106形成裸露P+离子注入区105和部分N+离子注入区104的源极接触孔109a；Step 6, referring to 2h, etching the interlayer dielectric layer 109 and the additional dielectric layer 106 to form source contact holes 109a that expose the P+ ion implantation region 105 and part of the N+ ion implantation region 104;
步骤7，参考2i，沉积金属于上述结构的顶面形成源极110，底面形成漏极100。Step 7, referring to 2i, depositing metal on the top surface of the above structure to form the source electrode 110, and the bottom surface to form the drain electrode 100.
本实施例中，栅氧化层107的厚度为常规厚度，为20-100nm，例如50nm，斜坡1061的坡度为45°。参考图3，作为对比例，未设置附加介质层，栅氧化层厚度均匀的延伸至N+离子注入区之内(即附加介质层的位置)。对实施例1和对比例进行电场仿真模拟，由图4可见，本发明的结构明显降低了栅极108边缘电场聚集效应带来的高电场峰值。In this embodiment, the thickness of the gate oxide layer 107 is a conventional thickness, which is 20-100 nm, for example, 50 nm, and the slope of the slope 1061 is 45°. Referring to FIG. 3 , as a comparative example, no additional dielectric layer is provided, and the thickness of the gate oxide layer is uniformly extended into the N+ ion implantation region (ie, the position of the additional dielectric layer). The electric field simulation of Example 1 and the comparative example is carried out. It can be seen from FIG. 4 that the structure of the present invention significantly reduces the high electric field peak value caused by the fringe electric field gathering effect of the gate 108 .
实施例2Example 2
参考图5，一种具有高可靠性栅源的SiC MOSFET功率器件2，与实施例1的差别在于，附加介质层106包括斜坡1061和由斜坡1061至高点向N+离子注入区104内侧延伸的平台1062，栅极108’越过斜坡且末端设于平台1062上。平台1062的厚度即为附加介质层106整体的厚度，通过实施例1中氧化窗口112a的边缘与N+离子注入区104的边缘之间距离的设置以及氧化参数的调控等实现本实施例的结构。平台1062的厚度为栅氧化层107厚度的1.5-100倍，例如6倍可以实现较好的效果。Referring to FIG. 5 , a SiC MOSFET power device 2 with high reliability gate-source, the difference from Embodiment 1 is that the additional dielectric layer 106 includes a slope 1061 and a platform extending from the slope 1061 to a high point to the inside of the N+ ion implantation region 104 At 1062 , the gate 108 ′ crosses the ramp and ends on the platform 1062 . The thickness of the platform 1062 is the overall thickness of the additional dielectric layer 106. The structure of this embodiment is realized by setting the distance between the edge of the oxidation window 112a and the edge of the N+ ion implantation region 104 in Embodiment 1 and adjusting the oxidation parameters. The thickness of the platform 1062 is 1.5-100 times the thickness of the gate oxide layer 107, for example, 6 times can achieve better results.
实施例3Example 3
参考图6，一种具有高可靠性栅源的SiC MOSFET功率器件3，与实施例1的差别在于，附加介质层106’不是采用局部氧化工艺形成，而是采用CVD工艺于外延层102表面沉积厚的SiO 2层，然后通过蚀刻的方法形成具有一定角度斜坡1061’的附加介质层106’。 Referring to FIG. 6 , a SiC MOSFET power device 3 with high reliability gate source is different from Embodiment 1 in that the additional dielectric layer 106 ′ is not formed by a local oxidation process, but is deposited on the surface of the epitaxial layer 102 by a CVD process A thick SiO2 layer is then formed by etching to form an additional dielectric layer 106' with an angled slope 1061'.
上述实施例仅用来进一步说明本发明的一种SiC功率器件及其制造方法，但本发明并不局限于实施例，凡是依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均落入本发明技术方案的保护范围内。The above embodiments are only used to further illustrate a SiC power device of the present invention and its manufacturing method, but the present invention is not limited to the embodiments, and any simple modifications and equivalent changes made to the above embodiments according to the technical essence of the present invention and modification, all fall within the protection scope of the technical solution of the present invention.

Claims (11)

  1. 一种SiC功率器件，其特征在于：包括由下至上设置的漏极、衬底和外延层，以及设于所述外延层上方的栅极和源极；所述外延层的上部的中间区域设有P-离子注入区，所述P-离子注入区的上部的中间区域设有P+离子注入区和N+离子注入区，且所述N+离子注入区位于所述P+离子注入区的两侧或周围；所述栅极由所述外延层的上方的两侧或周围延伸至末端位于所述N+离子注入区的上方，其中所述栅极位于所述N+离子注入区之外的部分与所述外延层之间设有栅氧化层，位于所述N+离子注入区之内的部分与所述N+离子注入区之间设有附加介质层，且所述附加介质层的厚度大于所述栅氧化层的厚度；所述源极与所述P+离子注入区和部分N+离子注入区接触且延伸至所述栅极上方，所述源极和所述栅极之间设有层间介质层。A SiC power device is characterized in that: it comprises a drain electrode, a substrate and an epitaxial layer arranged from bottom to top, and a gate electrode and a source electrode arranged above the epitaxial layer; There is a P- ion implantation region, and the upper middle region of the P- ion implantation region is provided with a P+ ion implantation region and an N+ ion implantation region, and the N+ ion implantation region is located on both sides of or around the P+ ion implantation region. ; the gate extends from two sides or around the top of the epitaxial layer to the end located above the N+ ion implantation region, wherein the gate is located outside the N+ ion implantation region and the epitaxial A gate oxide layer is arranged between the layers, an additional dielectric layer is arranged between the part located in the N+ ion implantation region and the N+ ion implantation region, and the thickness of the additional dielectric layer is greater than that of the gate oxide layer. thickness; the source electrode is in contact with the P+ ion implantation region and part of the N+ ion implantation region and extends above the gate electrode, and an interlayer dielectric layer is provided between the source electrode and the gate electrode.
  2. 根据权利要求1所述的SiC功率器件，其特征在于：所述栅氧化层的末端与所述N+离子注入区的边缘相对应，所述附加介质层由所述栅氧化层的末端向所述N+离子注入区内侧延伸，且厚度渐次增大以形成斜坡。The SiC power device according to claim 1, wherein the end of the gate oxide layer corresponds to the edge of the N+ ion implantation region, and the additional dielectric layer extends from the end of the gate oxide layer to the edge of the N+ ion implantation region. The inner side of the N+ ion implantation region is extended, and the thickness is gradually increased to form a slope.
  3. 根据权利要求2所述的SiC功率器件，其特征在于：所述栅极的末端位于所述斜坡上。The SiC power device according to claim 2, wherein the end of the gate is located on the slope.
  4. 根据权利要求2所述的SiC功率器件，其特征在于：所述附加介质层包括所述斜坡和由所述斜坡至高点向所述N+离子注入区内侧延伸的平台，所述栅极的末端位于所述平台上。The SiC power device according to claim 2, wherein the additional dielectric layer comprises the slope and a platform extending from the slope to a high point to the inside of the N+ ion implantation region, and the end of the gate is located at on the platform.
  5. 根据权利要求2所述的SiC功率器件，其特征在于：所述斜坡的坡度为5°～85°。The SiC power device according to claim 2, wherein the slope of the slope is 5°˜85°.
  6. 根据权利要求4所述的SiC功率器件，其特征在于：所述平台的厚度是所述栅氧化层厚度的1.5～100倍。The SiC power device according to claim 4, wherein the thickness of the platform is 1.5-100 times the thickness of the gate oxide layer.
  7. 根据权利要求1所述的SiC功率器件，其特征在于：所述附加介质层的材料与所述栅氧化层的材料相同。The SiC power device according to claim 1, wherein the material of the additional dielectric layer is the same as the material of the gate oxide layer.
  8. 权利要求1～7任一项所述SiC功率器件的制造方法，其特征在于包括以下步骤：The manufacturing method of the SiC power device according to any one of claims 1 to 7, characterized in that it comprises the following steps:
    1)于衬底上生长外延层，通过多次离子注入于外延层上形成P-离子注入区、N+离子注入区和P+离子注入区；1) growing an epitaxial layer on the substrate, and forming a P- ion implantation region, an N+ ion implantation region and a P+ ion implantation region on the epitaxial layer by multiple ion implantation;
    2)通过局部氧化工艺或化学气相沉积工艺于N+离子注入区之内形成附加介质层；2) An additional dielectric layer is formed in the N+ ion implantation region by a local oxidation process or a chemical vapor deposition process;
    3)于N+离子注入区外侧形成栅氧化层；3) forming a gate oxide layer outside the N+ ion implantation region;
    4)于栅氧化层和附加介质层上形成栅极；4) forming a gate on the gate oxide layer and the additional dielectric layer;
    5)于步骤4)形成的结构顶面沉积层间介质层；5) depositing an interlayer dielectric layer on the top surface of the structure formed in step 4);
    6)蚀刻层间介质层和附加介质层形成裸露P+离子注入区和部分N+离子注入区的源极接触孔；6) Etch the interlayer dielectric layer and the additional dielectric layer to form source contact holes that expose the P+ ion implantation region and part of the N+ ion implantation region;
    7)分别于步骤6)形成的结构的顶面形成源极，底面形成漏极。7) A source electrode is formed on the top surface of the structure formed in step 6), and a drain electrode is formed on the bottom surface.
  9. 根据权利要求8所述的制造方法，其特征在于：步骤2)中，所述局部氧化工艺包括以下步骤：The manufacturing method according to claim 8, wherein: in step 2), the local oxidation process comprises the following steps:
    2.1)沉积厚度为20-50nm的第一氧化层；2.1) deposit a first oxide layer with a thickness of 20-50nm;
    2.2)形成掩膜层，蚀刻所述掩膜层形成氧化窗口；2.2) forming a mask layer, and etching the mask layer to form an oxidation window;
    2.3)对所述氧化窗口之内的结构进行局部氧化，形成所述附加介质层；2.3) Partially oxidize the structure within the oxidation window to form the additional dielectric layer;
    2.4)去除所述掩膜层和第一氧化层。2.4) Remove the mask layer and the first oxide layer.
  10. 根据权利要求9所述的制造方法，其特征在于：步骤2.2)中，所述氧化窗口的边缘位于所述N+离子注入区的边缘的内侧，步骤2.3)中，所述附加介质层由所述氧化窗口的边缘至所述N+离子注入区的边缘形成斜坡。The manufacturing method according to claim 9, wherein in step 2.2), the edge of the oxidation window is located inside the edge of the N+ ion implantation region, and in step 2.3), the additional dielectric layer is formed by the The edge of the oxidation window forms a slope to the edge of the N+ ion implanted region.
  11. 根据权利要求8所述的制造方法，其特征在于：步骤2)中，通过化学气相沉积工艺形成所述附加介质层，然后蚀刻所述附加介质层的边缘形成斜坡。The manufacturing method according to claim 8, wherein in step 2), the additional dielectric layer is formed by a chemical vapor deposition process, and then the edge of the additional dielectric layer is etched to form a slope.
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