CN102479713A - MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and manufacturing method thereof - Google Patents
MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and manufacturing method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 230000005669 field effect Effects 0.000 title abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 238000005516 engineering process Methods 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 9
- 238000013459 approach Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000003628 erosive effect Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 abstract 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 1
- 102000013275 Somatomedins Human genes 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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Abstract
The embodiment of the invention discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a manufacturing method thereof. The method comprises the following steps: forming a gate oxide layer and a polysilicon gate on the surface of an epitaxial layer; forming a source region in the surface of the epitaxial layer; and oxidizing the source region and forming an oxide in a gap between the polysilicon gate on the surface of the source region and the source region. The embodiment of the invention also provides the MOSFET comprising the epitaxial layer, the source region formed in the surface of the epitaxial layer as well as the gate oxide layer and the polysilicon gate which are formed on the surface of the epitaxial layer, wherein an oxide layer formed by using a thermal oxide growth process is arranged in the gap between the source region and the polysilicon gate on the surface of the source region of the MOSFET. In the embodiment of the invention, the gap between the edge of the polysilicon gate and the source region is filled with the oxide formed on the surface of the source region, and meanwhile, the thickness of the gate oxide layer at the edge of a gate region is also increased, therefore, the possibility that the gate oxide layer at the edge of the gate region is broken down can be lowered.
Description
Technical field:
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of MOSFET manufacturing approach and a kind of MOSFET.
Background technology:
Along with the develop rapidly of semiconductor fabrication, semiconductor device is in order to reach arithmetic speed faster.Bigger memory data output and more function, semiconductor wafer develops towards higher component density, high integration direction, the requirement of its physical structure and manufacturing process is also come high.
With MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor; Metal oxide semiconductor field effect tube) be example, existing manufacturing process generally includes following step: on the epi-layer surface of semiconductor wafer, form gate oxide and polysilicon layer successively; Successively through the coating photoresist, steps such as mint-mark grid region graphic structure, polysilicon gate etching, removal photoresist form the grid region figure at polysilicon surface on photoresist; Adopt ion injection and impurity to push away trap, form the tagma; In the tagma, form the source region; The somatomedin layer; In dielectric layer, form the contact hole that leads to grid region, source region; Carry out the local interlinkage of metal connecting line and accomplish metallization.As shown in Figure 1, the partial structurtes sketch map of a kind of common MOSFET that the existing manufacturing process of serving as reasons obtains specifically comprises: epitaxial loayer 101, polysilicon gate 102, gate oxide 103, source region 104 and tagma 105.
Through research to the partial structurtes sketch map of MOSFET shown in Figure 1; The inventor finds: among this MOSFET, can there be space 106 in the marginal position in its grid region between polysilicon gate 102 and the source region 104 usually; And under the ideal situation, space 106 should be a gate oxide.Space 106 is in follow-up vapor deposition processing procedure; Serve as dielectric film; The dielectric oxide that vapor deposition forms is filled 106 zones, space; Because the conduction intensity of dielectric oxide will far be weaker than the gate oxide that is formed by thermal oxidation, so grid oxygen punch-through takes place in the gate oxide at edge, grid region possibly, and MOSFET is scrapped.
Summary of the invention
For solving the problems of the technologies described above, the object of the present invention is to provide manufacturing approach and a kind of MOSFET of a kind of MOSFET, with the problem of the gate oxide generation grid oxygen punch-through that solves edge, MOSFET grid region, thus the useful life of improving MOSFET.
For realizing above-mentioned purpose, the invention provides following technical scheme:
A kind of MOSFET manufacturing approach comprises:
On epi-layer surface, form gate oxide and polysilicon gate;
In epi-layer surface, form the source region;
Carry out the source region oxidation, in the space on the surface, source region between polysilicon gate and the source region, form oxide.
Preferably, in epi-layer surface, form after the source region, carry out also comprising before the oxidation of source region:
Semiconductor wafer is annealed.
Preferably,
The oxide thickness that forms on the surface, source region is 1 to 3 times of gate oxide thickness.
Preferably,
Temperature when semiconductor wafer is annealed is 800～900 degrees centigrade, and the annealing duration is 14～16 minutes.
Preferably,
Adopt thermal oxide growth technology to carry out the source region oxidation, the duration is 14～16 minutes.
Preferably, before the source region forms, also comprise:
In said polysilicon gate both sides, push away trap through ion injection and impurity, form the tagma;
Said source region is formed in the said tagma.
Preferably, before forming gate oxide and polysilicon layer, also comprise:
On the epi-layer surface of semiconductor wafer, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
Preferably, after removing protective oxide film, also comprise:
The epi-layer surface of oxide-semiconductor wafer;
Photoetching is formed with the source region figure in the oxide on epi-layer surface;
Oxide on the erosion removal epi-layer surface.
Preferably, after forming the source region, also comprise:
On the semiconductor wafer epi-layer surface, form dielectric layer;
In dielectric layer, form the contact hole that leads to grid region, source region respectively;
Metallize at said contact hole, obtain grid, source electrode;
Form drain electrode at the semiconductor wafer substrate back side.
The present invention also provides a kind of MOSFET, comprises epitaxial loayer, is formed at the interior source region of epi-layer surface, is formed at gate oxide and polysilicon gate on the epi-layer surface;
On the surface, source region of said MOSFET, in the space between polysilicon gate and the source region, be provided with the oxide layer that adopts thermal oxide growth technology to form.
Preferably, said thickness of oxide layer is 1～3 times of gate oxide thickness.
The technique effect of the technical scheme that the embodiment of the invention provided is; Among the MOSFET; The oxide that the surface, source region forms has been filled the gap between polysilicon gate edge and the source region, has increased the thickness of the gate oxide at edge, grid region simultaneously, therefore; Can reduce the breakdown possibility of gate oxide at edge, grid region, improve the useful life that makes MOSFET.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the partial structurtes sketch map of MOSFET of the prior art;
The partial structurtes sketch map of the MOSFET that Fig. 2 provides for the embodiment of the invention one;
The partial structurtes sketch map of the MOSFET that Fig. 3 provides for the embodiment of the invention two.
Embodiment
Among the existing MOSFET, the marginal position in its grid region can have the space usually between polysilicon gate and the source region, and under the ideal situation, this space should be a gate oxide.This space normally forms in the gate oxide corrosion process; In follow-up vapor deposition processing procedure; Can form dielectric oxide in this space; Because the conduction intensity of dielectric oxide will far be weaker than the gate oxide that is formed by thermal oxidation, in the void area that is covered with dielectric oxide grid oxygen punch-through takes place possibly therefore, MOSFET is scrapped.
The embodiment of the invention provides a kind of MOSFET manufacturing approach for this reason, and after the source region formed, dielectric layer comprised: semiconductor wafer is annealed before forming; Carry out the source region oxidation, on the surface, source region, comprise in the space between polysilicon gate and the source region, form oxide.
The embodiment of the invention also provides a kind of MOSFET, on the surface, source region of said MOSFET, in the space between polysilicon gate and the source region, is provided with the oxide layer that adopts thermal oxide growth technology to form.
It more than is core concept of the present invention; To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention carried out clear, intactly description, obviously; Described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one:
Present embodiment provides a kind of MOSFET manufacturing approach, and this method is after the source region forms, and dielectric layer comprises before forming:
On epi-layer surface, form gate oxide and polysilicon gate;
In epi-layer surface, form the source region;
Carry out the source region oxidation, in the space on the surface, source region between polysilicon gate and the source region, form oxide.
Need to prove that the epitaxial loayer in the present embodiment can be the N that on semiconductor wafer, forms
-～N
+The type structure, the thickness of epitaxial loayer can confirm that epitaxial loayer can be positioned at the front or the back side of semiconductor wafer according to the concrete application requirements of device.
In this step, form gate oxide concrete grammar can for: adopt thermal oxidation technology on the epi-layer surface of semiconductor wafer substrate, to form gate oxide, the gate oxide in the present embodiment comprises silica at least, and its thickness can be 20～50 dusts.Form polysilicon layer concrete grammar can for: the semiconductor wafer that will comprise gate oxide changes low-pressure chemical vapor phase deposition equipment over to; And in the process cavity of equipment, feed silane; After silane decomposed, polysilicon was deposited on the gate oxide surface, and wherein the thickness of polysilicon layer is about 5000 dusts.After the polysilicon deposit is accomplished, can also carry out the polysilicon doping operation.
In photoresist layer, form the grid region figure through behind exposure and the developing procedure, and be mask with the photoresist layer, remove grid region figure outside gate oxide and polysilicon layer through etching process, the formation grid region.In this step, specifically can pass through isotropic plasma etching polysilicon gate, also can accomplish by wet chemical etching technique technology.
As shown in Figure 2, the partial structurtes sketch map of the MOSFET after the source region oxidation that provides for present embodiment, wherein, 201 is epitaxial loayer, and 202 is polysilicon gate, and 203 is gate oxide, and 204 is the source region, 205 is the tagma, 207 oxides for forming on the surface, source region.In the present embodiment, said epitaxial loayer 201 can be N
-～N
+Type doped structure, said source region 204 are can be for the N+ type mixes, and can mix for the P-type in said tagma 205.
Concrete parameter when semiconductor wafer is annealed in annealing furnace can for: temperature is 800～900 degrees centigrade, and annealing is 14～16 minutes the duration, in annealing process, can also in annealing furnace, feed nitrogen, adopts n 2 annealing technology.A kind of preferable annealing way does, temperature is controlled at 850 degrees centigrade during annealing, and the duration is 15 minutes.
Generally speaking; Gate oxide is to adopt thermal oxide growth technology to form, therefore for make oxide that the source region forms electrically and gate oxide approaching, in the present embodiment; Adopt thermal oxide growth technology to carry out the source region oxidation; Specifically can be in the oxidation reaction chamber, passing through hydrogen and oxygen, the duration can be 14～16 minutes, preferable is 15 minutes.
In the technical scheme that present embodiment provided, the thickness of the oxide that forms on the surface, source region is generally 1～3 times of gate oxide, and its thickness can also be controlled through the doping impurity concentration in control source region.
In the present embodiment; The oxide that the surface, source region forms has been filled the gap between polysilicon gate edge and the source region, has increased the thickness of the gate oxide at edge, grid region simultaneously, therefore; Can reduce the breakdown possibility of gate oxide at edge, grid region, improve the useful life that makes MOSFET.
Embodiment two:
Present embodiment provides a kind of concrete MOSFET manufacturing approach, on the basis of the method that embodiment one provides, in the present embodiment, before the source region forms, can also comprise:
In said polysilicon gate both sides, push away trap through ion injection and impurity, form the tagma;
Said source region is formed in the said tagma.
With the polysilicon gate is mask, in said polysilicon gate both sides, carry out ion and inject, and impurity pushes away trap, the formation tagma.In the subsequent step, the source region forms through implanted dopant in the tagma.
In the present embodiment, before forming gate oxide and polysilicon layer, can also in semiconductor wafer, be formed for protecting the conductive protection zone of device realization device isolation, its implementation can comprise:
On the epi-layer surface of semiconductor wafer substrate, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
Wherein, protective oxide film can be in the high-temperature technology chamber aerating oxygen, obtain with silicon generation oxidation reaction; Mainly as the oxide screen; In the control ion implantation process, impurity injects the scope and the degree of depth, and the protection epi-layer surface is avoided staiing; Prevent in ion implantation process, to the silicon chip excessive damage.
In addition,, after above-mentioned removal protective oxide film, form before grid oxide layer and the polysilicon layer, can also comprise in order in a semiconductor wafer, to define a plurality of active areas respectively:
Step 41, the epi-layer surface of oxide-semiconductor wafer substrates;
Step 42, photoetching is formed with the source region figure in the oxide of epi-layer surface;
Step 43, the oxide of erosion removal epi-layer surface.
Can be implemented in a plurality of active areas of formation in the semiconductor wafer through above-mentioned steps, and then form a plurality of semiconductor device.
The method that the embodiment of the invention provided after forming the source region, can also comprise:
Step 51 forms dielectric layer on the epi-layer surface of semiconductor wafer substrate;
Step 52 forms the contact hole that leads to grid region, source region respectively in dielectric layer;
Step 53 metallizes, and obtains grid, source electrode;
Step 54 forms drain electrode at the semiconductor wafer substrate back side.
Specifically can be referring to MOSFET partial structurtes sketch map shown in Figure 3, wherein, 201 is the epitaxial loayer of semiconductor wafer; 202 is the grid region that forms behind the polysilicon gate etching, and 203 is gate oxide, and 205 is the tagma; 204 is the source region, and 207 is the oxide on surface, source region, and 210 is the drain region; 208 is dielectric layer, and 209 for being filled with the through hole of metal material.
Concrete, said epitaxial loayer 201 is to be N
-～N
+The type doped structure, said source region 204 is to be N
+Type mixes, and said tagma 205 can be P
-Type mixes, and is formed by following mode: with the grid region figure is mask, injects the boron ion, and carries out impurity and push away trap, forms P
-The tagma that type mixes.
Embodiment three:
Corresponding to said method embodiment, present embodiment also provides a kind of MOSFET.
Said MOSFET comprises epitaxial loayer, is formed at the interior source region of epi-layer surface, is formed at gate oxide and polysilicon gate on the epi-layer surface;
On the surface, source region of said MOSFET, in the space between polysilicon gate and the source region, be provided with the oxide layer that adopts thermal oxide growth technology to form.
Preferable, said thickness of oxide layer can be 1～3 times of gate oxide thickness.
Because present embodiment is to use said method embodiment to obtain device architecture embodiment, its similarity can cross-references, repeats no more.
In the embodiment of the invention; The oxide that the surface, source region forms has been filled the gap between polysilicon gate edge and the source region, has increased the thickness of the gate oxide at edge, grid region simultaneously, therefore; Can reduce the breakdown possibility of gate oxide at edge, grid region, improve the useful life that makes MOSFET.
Each embodiment adopts the mode of going forward one by one to describe in this specification, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the present invention.Multiple modification to these embodiment will be conspicuous concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from the spirit or scope of the present invention in other embodiments among this paper.Therefore, the present invention will can not be restricted to these embodiment shown in this paper, but will meet and principle disclosed herein and features of novelty the wideest corresponding to scope.
Claims (10)
1. MOSFET manufacturing approach is characterized in that:
On epi-layer surface, form gate oxide and polysilicon gate;
In epi-layer surface, form the source region;
Carry out the source region oxidation, in the space on the surface, source region between polysilicon gate and the source region, form oxide.
2. method according to claim 1 is characterized in that, in epi-layer surface, forms after the source region, carries out also comprising before the oxidation of source region:
Semiconductor wafer is annealed.
3. method according to claim 2 is characterized in that:
Temperature when semiconductor wafer is annealed is 800～900 degrees centigrade, and the annealing duration is 14～16 minutes.
4. method according to claim 1 is characterized in that:
Adopt thermal oxide growth technology to carry out the source region oxidation, the duration is 14～16 minutes, and the oxide thickness that forms on the surface, source region is 1 to 3 times of gate oxide thickness.
5. method according to claim 1 is characterized in that:
Before the source region forms, also comprise:
In said polysilicon gate both sides, push away trap through ion injection and impurity, form the tagma;
Said source region is formed in the said tagma.
6. method according to claim 1 is characterized in that, before forming gate oxide and polysilicon layer, also comprises:
On the epi-layer surface of semiconductor wafer, form protective oxide film;
Form the conductive protection regional graphics through photoetching process at protective oxide film;
The ion injection in the conductive protection zone, impurity push away trap, form well region;
Remove protective oxide film.
7. method according to claim 6 is characterized in that, after removing protective oxide film, also comprises:
The epi-layer surface of oxide-semiconductor wafer;
Photoetching is formed with the source region figure in the oxide on epi-layer surface;
Oxide on the erosion removal epi-layer surface.
8. method according to claim 1 is characterized in that, after forming the source region, also comprises:
On the semiconductor wafer epi-layer surface, form dielectric layer;
In dielectric layer, form the contact hole that leads to grid region, source region respectively;
Metallize at said contact hole, obtain grid, source electrode;
Form drain electrode at the semiconductor wafer substrate back side.
9. a MOSFET comprises epitaxial loayer, is formed at the interior source region of epi-layer surface, is formed at gate oxide and polysilicon gate on the epi-layer surface, it is characterized in that:
On the surface, source region of said MOSFET, in the space between polysilicon gate and the source region, be provided with the oxide layer that adopts thermal oxide growth technology to form.
10. MOSFET according to claim 9 is characterized in that:
Said thickness of oxide layer is 1～3 times of gate oxide thickness.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010564084.3A CN102479713B (en) | 2010-11-29 | 2010-11-29 | MOSFET manufacture method and MOSFET |
| PCT/CN2011/083107 WO2012072020A1 (en) | 2010-11-29 | 2011-11-29 | Metal-oxide-semiconductor field-effect transistor (mosfet) and method for fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112065A (en) * | 2019-05-10 | 2019-08-09 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
| CN112103336A (en) * | 2020-08-19 | 2020-12-18 | 厦门市三安集成电路有限公司 | SiC power device and manufacturing method thereof |
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|---|---|---|---|---|
| CN1338781A (en) * | 2000-08-10 | 2002-03-06 | 三洋电机株式会社 | Insulated gate semiconductor device and manufacture thereof |
| US20090072306A1 (en) * | 2007-09-03 | 2009-03-19 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| WO2010119789A1 (en) * | 2009-04-13 | 2010-10-21 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
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| JP2009070849A (en) * | 2007-09-10 | 2009-04-02 | Rohm Co Ltd | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1338781A (en) * | 2000-08-10 | 2002-03-06 | 三洋电机株式会社 | Insulated gate semiconductor device and manufacture thereof |
| US20090072306A1 (en) * | 2007-09-03 | 2009-03-19 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| WO2010119789A1 (en) * | 2009-04-13 | 2010-10-21 | ローム株式会社 | Semiconductor device and method for manufacturing semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110112065A (en) * | 2019-05-10 | 2019-08-09 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
| CN112103336A (en) * | 2020-08-19 | 2020-12-18 | 厦门市三安集成电路有限公司 | SiC power device and manufacturing method thereof |
| WO2022037457A1 (en) * | 2020-08-19 | 2022-02-24 | 厦门市三安集成电路有限公司 | Sic power device and manufacturing method therefor |
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| CN102479713B (en) | 2015-09-09 |
| WO2012072020A1 (en) | 2012-06-07 |
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