KR100949665B1 - Method for fabricating semiconductor device - Google Patents

Abstract

To provide a method for manufacturing a semiconductor device capable of forming an ultra-low-flow junction using a solid phase diffusion (SPD) method, a method of manufacturing a semiconductor device for achieving the above object is provided on a substrate. Stacking an insulating film and a semiconductor layer; Forming holes at predetermined intervals in the semiconductor layer and the first insulating layer so that one region of the substrate is exposed; Forming a doped sidewall insulating film in the holes; Forming a gate insulating film and a gate electrode between the holes by removing the first insulating film and the semiconductor layer outside the hole; And a step of forming an LDD region and a source / drain region of an ultra shallow junction in the substrate on both sides of the gate electrode by a heat treatment process using a solid phase diffusion method.

Sidewall Insulation, Gate Electrode, SPD, Crow Junction, Rapid Heat Treatment

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 silicon substrate 11 first insulating film

11a: gate insulating film 12: semiconductor layer

12a: gate electrode 13: first photosensitive film

14 hole 15 second insulating film

15a: sidewall insulating film 16: LDD region

17a / 17b: source / drain regions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming an ultra-low junction by a solid phase diffusion (SPD) method.

In general, in the manufacturing process of a semiconductor integrated device (IC), IC manufacturing technology has been scaled down in sub-micron units in order to obtain good performance and high integration of circuit operation.

The scale-down of a semiconductor device can be balanced with device characteristics only when the horizontal dimension and the vertical dimension are reduced simultaneously.

Without considering this, reducing the size of the device reduces the channel length between the source and drain, resulting in unwanted changes in device characteristics.

The representative characteristic change is the occurrence of a short channel effect.

In order to solve the short channel effect, it is necessary to perform vertical scale down (reducing the thickness of the gate insulating layer and reducing the junction depth) at the same time as the horizontal scale down (reduction of the gate length).

In addition, accordingly, the applied voltage must be lowered, the substrate doping concentration must be increased, and in particular, the control of the doping profile of the channel region must be made efficiently.

However, the size of semiconductor devices is decreasing, but the operating power required by electronic products is not yet lowered. Therefore, in the scaled down semiconductor devices, especially MOS devices, as the size decreases, the two junctions become very close. It can penetrate into this channel. This phenomenon is called charging sharing. In general, since the source and the drain actually share the channel charge to be controlled by the gate, the effect of lowering the electrical potential by interacting with the source-channel junction due to the increase of the bias is shown. Will bring. This is called Drain Induced Barrier Lowering (DIBL). As the source junction barrier decreases, electrons are easily injected into the channel, which no longer controls the gate voltage.

In the scaled-down device as described above, electrons injected from the source are accelerated severely under a high potential gradient of the drain, thereby making the structure vulnerable to hot carrier generation.

And the electric field of the junction of the drain biased in the reverse direction can cause impact ionization and carrier propagation. The resulting holes cause substrate currents, some of which move into the source, lowering the source barrier and injecting electrons into the p region from the source. Accordingly, n-p-n transistor operation may occur in the source-channel-drain region, thereby preventing the gate from controlling the current.

In addition, in an MOS device having a sub-micron or smaller gate length, an ultra-low source having an abrupt doping profile and a depth of several tens of nm to suppress short channel effects. There is a need for ultra shallow source-drain formation and extended junction technology.

In response to such a demand, an impurity doping method using a method such as ultra low energy ion implantation and laser annealing has been conventionally used.

However, the method of doping impurity ions by accelerating ions (ion acceleration process) essentially causes lattice defects in silicon bonding, resulting in junction leakage current.

This increase in junction leakage current adversely affects the system as a result of increased reliability and reduced power consumption of the device.

Thus, although a subsequent heat treatment process is necessary to activate the doped impurities on the silicon substrate and remove unnecessary lattice defects, it is difficult to remove the complete lattice defects even by high temperature heat treatment.

For the above reason, when fabricating a device having a gate length of sub micron or less (approximately 100 nm or less), there are physical limitations in reducing hot carrier effects and short channel effects.

The present invention has been proposed to solve the above problems of the prior art, and provides a method of manufacturing a semiconductor device that can be applied to a submicron device by forming an ultra-low junction using a solid phase diffusion (SPD) method Its purpose is to.

According to an aspect of the present invention for achieving the above technical problem, the step of laminating a first insulating film and a semiconductor layer on a substrate; Forming holes at predetermined intervals in the semiconductor layer and the first insulating layer so that one region of the substrate is exposed; Forming a doped sidewall insulating film in the holes; Forming a gate insulating film and a gate electrode between the holes by removing the first insulating film and the semiconductor layer outside the hole; A method of fabricating a semiconductor device is provided by forming an LDD region and a source / drain region of an ultra-low junction in the substrate on both sides of the gate electrode by a heat treatment process using a solid phase diffusion method.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

The present invention is characterized in that the ultra-low junction in the source / drain is formed using a solid phase diffusion (SPD) method rather than an ion implantation method. First, as shown in FIG. The first insulating film 11 and the semiconductor layer 12 are deposited on the substrate. At this time, the semiconductor layer 12 is formed of polysilicon.

As shown in FIG. 1B, the first photosensitive film 13 is coated on the semiconductor layer 12, and the first photosensitive film 13 is selectively patterned so that one region is exposed by the exposure and development processes.

In this case, the first photoresist layer 13 is patterned so that a portion for forming the sidewall insulation layer is exposed later.                     

As shown in FIG. 1C, the semiconductor layer 12 and the first insulating layer 11 are etched to expose a region of the silicon substrate 10 using the patterned first photoresist layer 13 as a mask, and the holes have a predetermined interval. (14) form.

Thereafter, the first photosensitive film 13 is removed.

As shown in FIG. 1D, the second insulating film 15 is deposited on the entire surface of the silicon substrate 10 including the hole 14 and the semiconductor layer 12.

In this case, the second insulating layer 15 is formed by depositing doped Phospho-Silica Glass (PSG) or Boron Phospho-Silica Glass (BPSG) by chemical vapor deposition, or spin-doped silicon oxide liquid doped with ions other than P or B. It can also be coated and applied.

As shown in FIG. 1E, the second insulating film 15 is planarized by a chemical mechanical polishing process (CMP) until the semiconductor layer 12 is exposed to form a square sidewall insulating film 15a in the hole 14. . The sidewall insulating layer 15a is for a solid phase diffusion (SPD) process later.

Thereafter, a second photosensitive film (not shown) is coated on the semiconductor layer 12 including the sidewall insulating film 15a, and the second photosensitive film is left on the semiconductor layer 12 including the sidewall insulating film 15a by an exposure and development process. Pattern.

Next, the semiconductor layer 12 and the first insulating film 11 are etched using the second photoresist film as a mask to form a gate insulating film 11a and a gate electrode 12a. At this time, the gate insulating film 11a and the gate electrode 12a are formed between the square sidewall insulating film 15a.                     

Next, a high concentration of n-type or p-type ions (tilt) ions are implanted into the silicon substrate 10 using the gate electrode 12a and the sidewall insulating film 15a for the SPD as a mask.

As shown in FIG. 1F, the heat treatment temperature is controlled during the rapid thermal process using the SPD method, thereby simultaneously activating the low concentration doped region and the high concentration doped region to simultaneously activate both edges of the gate electrode 12a. LDD regions 16 and source / drain regions 17a / 17b having an inclined doping profile are formed in the silicon substrate 10 at the edges.

As a result, ultra-low junctions are formed in the silicon substrate 10 on both sides of the gate electrode 12a and the sidewall insulating film 15a.

The lightly doped region is formed by diffusion of phosphorus (P) ions or boron (B) ions doped into the sidewall insulating film 15a formed of PSG or BPSG onto the silicon substrate 10.

In the above, the LDD region 16 and the source / drain regions 17a and 17b may be separately separated from each other in the heat treatment step.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing the semiconductor device of the present invention described above has the following effects.

First, since the source / drain regions of the device form an ultra shallow junction, the junction leakage current due to the scale down of the device can be reduced.

Second, since the depth and doping concentration of the shallow junction can be adjusted in the solid phase rather than the ion implantation, the lattice defect problem can be prevented from occurring.

By using the SPD method as described above, it is possible to form an ultra shallow junction in a deep submicron device, thereby effectively preventing a hot carrier effect and a short channel effect.

Claims (7)

Stacking a first insulating film and a semiconductor layer on the substrate; Forming holes at predetermined intervals in the semiconductor layer and the first insulating layer so that one region of the substrate is exposed; Forming a sidewall insulating film doped with impurities in the holes; Forming a gate insulating film and a gate electrode between the holes by removing the first insulating film and the semiconductor layer outside the hole; And Forming an LDD region of ultra-low junction in the substrate on both sides of the gate electrode by diffusing impurities in the sidewall insulating layer to the substrate by a heat treatment process using a solid phase diffusion method; Method of manufacturing a semiconductor device comprising a. The method of claim 1, The formation of the sidewall insulating layer may include forming a second insulating layer on the entire surface of the substrate including the hole and the semiconductor layer; Planarizing the second insulating film by a chemical mechanical polishing process until the semiconductor layer is exposed. The method of claim 2, And the second insulating film is formed of PSG, BPSG or other doped silicon oxide solution. The method of claim 3, wherein The silicon oxide liquid is spin-coated to form a semiconductor device manufacturing method. The method of claim 1, Before forming the LDD region And implanting impurities into the substrate by using the gate electrode and the sidewall insulating layer as a mask. The method of claim 1, Forming the hole may include applying a first photoresist film on the semiconductor layer, and selectively patterning the first photoresist film so that one region is exposed through an exposure and development process; And etching the semiconductor layer using the patterned first photoresist film as a mask so that the substrate is exposed. The method of claim 1, Forming the gate insulating film and the gate electrode by applying a second photosensitive film on the semiconductor layer including the sidewall insulating film; Patterning the second photoresist film so as to remain only on the semiconductor layer including the sidewall insulating film by an exposure and development process; And etching the semiconductor layer and the first insulating layer so that the substrate is exposed by using the patterned second photoresist layer as a mask.

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