KR100260688B1 - Mosfet with raised sti isolation self-aligned to the gate stack - Google Patents

Abstract

The present invention relates to a semiconductor structure comprising a transistor having gate conductors having first and second edges bounded by raised isolation structures (ie, STIs). The source diffusion is self aligned with respect to the third edge of the gate electrode and the drain diffusion is self aligned with respect to the fourth edge of the gate electrode.

Description

A Morse field effect transistor having a raised separation structure and a method of forming the same

The present invention relates generally to semiconductor isolation techniques. Specifically, it relates to shallow trench isolation (STI) structures in insulating material raised above the surface of a semiconductor. In particular, it relates to isolation structures for transistors that reduce leakage in DRAM cells.

Modern CMOS technology employs field effect transistors that are adjacent or bordered by trenches. The trenches are used for shallow trench isolation (STI) or provide a location for the trench capacitor.

Parasitic leakage paths are created by bringing the semiconductor device closer to an edge or corner, which is one of the types of trenches. tea. T. Furukawa and Jay. a. In one leakage mechanism disclosed by JA Mandelman in "Process and Device Simulation of Trench Isolation Corner Parasitic Device", Proceedings of the Electrochemical Society Meeting, October 9-14, 1988, the gate electric field near the trench corner The increase results in a parasitic leakage path. If the corner radius of curvature is small and the gate conductor is close, the electric field increases. The problem may be exacerbated by sharpening of corners during processing and thinning of the gate dielectric layer near the corners. Also, the worst case scenario for corner field increase is that the gate conductor layer wraps around the trench corners. This occurs when the oxide fill in the isolation trench becomes concave below the silicon surface during etching of the oxide as it forms the isolation trench.

As a result of the increased electric field, the corner has a threshold voltage Vt lower than that of the flat portion of the semiconductor device. Thus, parallel paths to current conduction are formed. However, in the semiconductor device width used in modern technology, the flat portion of the upper portion of the semiconductor device transmits most of the on-current. Trench corner conduction is a parasitic current that typically only contributes to subthreshold leakage currents. This parasitic leakage current flowing along the corner is most easily known as the hill in the subcritical current curve of the narrow MOSFET.

Andre Bryant, W. W. Haensch, S. S. Geissler, Jack Mandelman, D. D. Poindexter, M. "The Current-Carrying Corner Inherent to Trench Isolation", published in August 1993 by M. Steger, IEEE Electron Device Letters, Vol. 14, No. As in 8, in applications such as DRAMs that require narrow channel widths to achieve high density, corner devices often dominate on-current. This parallel current transfer corner element is a major MOSFET contributor to standby current and leakage current in DRAM cells in low standby power logic circuit applications. Moreover, increased field due to field crowding at corners may affect dielectric layer integrity.

D. D. Foty, J. J. Mandelman, T. In the paper "Behavior of an NMOS Trench-Isolated Corner Parasitic Device at Low Temperature", published in October 1989 by T. Furukawa, in the Proceedings of the Electrochemical Society Meeting, It is suggested that the performance is not improved by the flat subcritical curve. Therefore, the corner parasitic elements may have many problems compared to the flat elements at low temperatures.

This problem of corner leakage current is typically controlled by increasing the critical injection dose, but this can degrade device performance. Therefore, another method for controlling corner leakage current is needed.

tea. "A Deep-Submicron Isolation Technology with T-shaped Oxide (TSO) Structure" by T. Ishijima et al., Proceedings of the IEDM, 1990, p. 257 discloses the problem of trench sidewall conversion. This paper describes the use of a channel stop boron implant along the sidewalls of trenches and aligned pairs of photomasks to form T-type oxides adjacent to the corners of the isolation trenches. The disclosed isolation structure supplies boron to remove the device from the trench sidewalls and raise Vt along the sidewalls. However, when these two-mask-and-implant schemes include tolerances of photomask alignment, the separation extends, making this solution undesirable. M. M. The patent pending "A Corner Protected Shallow Trench Isolation Device", currently pending by MM Armacost et al., Provides a way to protect the corners without expanding the separation, but the corner problem is a sharp point. The problem and the problem of thinning oxide still exist. Thus, there is a need for improved means for controlling corner parasitic currents, which is provided by the following invention.

An object of the present invention is to prevent leakage current at the corners of a semiconductor element without degrading the performance of the element.

Another object of the present invention is to prevent the gate conductor layer from wrapping around the trench corners.

Another object of the present invention is to prevent the gate dielectric layer adjacent to the corner from thinning.

Another object of the present invention is to prevent corners from being sharpened.

It is another object of the present invention to provide a transistor having individual segments of the gate conductor layer formed on separate wiring levels and a gate connector in the form of a spacer rail.

Yet another object of the present invention is to allow the gate conductor layer to be confined to the active device region and the separator self-aligned with respect to the gate conductor layer.

It is yet another object of the present invention to provide a wiring level that is a subminimum dimension conductive spacer rail that interconnects the individual gate segments of the transistor array.

This object of the invention is achieved by a semiconductor structure comprising a transistor having a gate comprising segments of individual gate conductor layers on a thin film dielectric. The gate conductor extends substantially simultaneously with the thin film dielectric. The gate conductor has a top surface having first and second edges facing each other and third and fourth edges facing each other. The raised separator bounds the first and second edges of the gate conductor. The source is self aligned with respect to the third edge and the drain is self aligned with respect to the fourth edge. The conductive wiring level is in contact with the top surface.

Another aspect of the invention provides a substrate having a top surface, the substrate having a gate stack comprising a gate dielectric layer and a gate conductor layer, removing a first portion of the gate stack and etching a trench in the substrate. Exposing a raised separator, depositing and planarizing an insulator on the top surface of the gate stack, removing a second portion of the gate stack for a source / drain region and adjoining the source / drain region. Exposing sidewalls of the gate stack, forming spacers adjacent the exposed sidewalls of the gate stack, and forming source / drain diffusions in the exposed portions of the source / drain regions. It is to provide a method of forming a FET.

These objects, features and advantages of the invention will be apparent from the drawings and description.

The foregoing objects, features, and advantages of the present invention will become apparent from the following detailed description of the invention, as illustrated in the accompanying drawings.

1 through 8 are cross-sectional views showing the structure at some stages in the process for manufacturing the semiconductor structure of the first aspect of the present invention.

9-13 are cross-sectional views showing the structure at some stages in the process for manufacturing the semiconductor structure of the second aspect of the present invention.

Explanation of symbols for main parts of the drawings

10 substrate 14 gate dielectric layer

16: gate conductor 18: gate cap dielectric

20: Raised Deep Trench 30: Raised STI

36: spacer 44: groove

The present invention provides a transistor having a gate formed from an individual segment of a gate conductor. This gate conductor is limited to an active device region having a thin film gate dielectric layer. STI is self aligned with respect to the gate conductor. The gate dielectric layer and gate conductor are formed as blanket layers on the wafer before the isolation trenches are etched, so that corners are sharpened and the gate dielectric layer is avoided from thinning. The conductive wiring level is in contact with this segment gate, and the wiring level can be microscopically sized as a result of directional etching of the conductor along the sidewalls.

STIs and processes for forming them are disclosed in US Pat. No. 5,173,439 by Dash et al., Which is incorporated herein by reference.

As used herein, the term "horizontal" is defined as a plane parallel to the conventional planar surface of the semiconductor chip or wafer, regardless of the direction the semiconductor chip actually has. The term "vertical" refers to a direction perpendicular to the horizontal plane defined above. "On", "side" (used in "sidewall"), "higher", "lower", "over", "under" Prepositions, such as ", are defined with respect to a conventional flat surface formed on the top surface of the semiconductor chip or wafer, regardless of the direction the semiconductor chip actually has.

The single crystal semiconductor wafer used in the process steps illustrated in FIGS. 1-13 is formed from materials such as silicon, germanium, gallium arsenide. Since silicon is the most widely used and most of its etching properties are known, silicon will be used in the following examples. The wafer may already have undergone implants, diffusion, oxidation, and other process steps before being introduced into the process sequences described below.

1-8 illustrate steps of a process for fabricating a transistor or DRAM cell in accordance with an aspect of the present invention. Referring now to FIG. 1, a "blanket" Vt channel implantation is performed in a region on the substrate 10 that may include an extended portion or substantially the entire chip of the chip. For example, if an array of devices is formed, the blanket implant region will substantially comprise the entire area of the array. Subsequently, the gate stack 12 is formed from a series of layers including the gate dielectric layer 14, the gate conductor 16, and the gate cap dielectric 18 in the same region. First, the blanket gate dielectric 14 is thermally grown or deposited. Next, the gate conductor 16 is blanket deposited. The gate conductor 16 is made of polysilicon. Gate conductor 16 may be in-situ doped during the deposition process or may be implanted after the deposition process to provide proper gate doping. Finally, a cap dielectric 18 of blanket Si ₃ N ₄ is deposited on top of gate conductor 16 to a thickness suitable for use as a planar etch stop layer.

In the next step, the photoresist is applied, exposed and developed to define the area where the trench is to be formed. The trenches may be STIs or storage capacitors. This pattern is first etched into the gate cap dielectric 18. The resist is then removed and etching continues in the gate conductor 16 and the exposed gate dielectric layer 14 using a pattern in the nitride gate cap dielectric 18. Finally, the etching is extended to the silicon substrate 10 to form a raised deep trench for the capacitor as shown in FIG. 2 or a raised shallow trench 30 for the STI as shown in FIG. ). The term "raised trench" refers to the trench extending beyond the surface of the substrate 10 to the top of the gate stack. In this process, a single masking step defines the edge between the trench and the gate stack and provides a complete alignment between them. Thus, the gate is bounded by raised trenches on two opposite sides. However, since the gate dielectric and the gate conductor are formed as a blanket layer before the trench is etched, the corners are not sharp, the gate dielectric is not thinned, and no wrap around the gate occurs.

As shown in FIG. 3, the storage node insulator 22 and the storage electrode 24 are described in detail herein by reference. M. It is formed in the raised deep trench 20, as disclosed in U.S. Patent 5,264,716 (called "'716 patent") by D. M. Kenney, "Diffused Buried Plate Trench Dram Cell Array." In summary, the storage node insulator 22 is formed by thermal oxide growth, silicon nitride deposition, and oxidizing the surface layer of the nitride. The raised deep trench 20 is then filled with doped polysilicon and used as the storage electrode 24 of the capacitor. Grooves may be formed in the polysilicon to form an insulating collar 26. 3 illustrates a cell at this stage in a semiconductor manufacturing process.

In the same process as that described above for raised deep trenches, raised shallow trench isolations (raised STIs) 30 are formed. Referring to FIG. 4, after the photomasking and gate stack etching steps described above, a silicon etch step is used on the silicon substrate 10 to form a shallow trench for the raised STI 30. The passivation oxide is then thermally grown along the surface of the silicon thus exposed. TEOS is then deposited to fill the shallow trenches (top of deep trench 20). Next, a planarization step of stopping on the nitride cap of the gate stack is performed. Thus, the raised STI is provided close to the sidewall of the gate stack. Of course, the raised STI 30 may intersect the deep trench 20 in the same manner as disclosed for the standard STI in the '716 patent.

Next, the source / drain regions of the active region are defined using the process described above for the raised deep trench 20 and the raised STI 30. Referring to FIG. 5 perpendicular to the cross section of FIG. 4, the gate segment 32 of the desired pattern is formed using the photomasking step and the gate stack etching step as described above. This etching step leaves only polysilicon on the channel region 34 below the gate dielectric 14, and defines the channel length of the transistor in the fabrication process. This diffuses for source / drain over silicon on the two sides of the exposed gate stack. The other two sides of the gate stack are bounded by raised storage trenches 20 or raised STIs 30.

In the next step, the dielectric sidewall spacers 36 illustrated in FIG. 6 are grown or deposited on two exposed edges of the gate stack 32. Spacers 36 are typically formed of thermally grown oxide along the sidewalls of gate conductor 16 and etched silicon nitride directionally, leaving nitride spacers formed along the sidewall to remove nitride formed along the horizontal surface. do. After the spacers 36 are formed, the source / drain regions 38 of the transistors 39 are formed by diffusion or ion implantation. The diffusion or implant is bounded by self-aligned and raised STI 30 or raised storage trench 20 relative to spacers 36 formed along the edge of gate stack 32. Diffusion for the source / drain regions 38 may be provided by depositing a doped glass layer or a doped polysilicon layer. The doped layer can then be planarized and masked and etched to define the NMOS and PMOS regions. The wafers are then activated and enter the heat treatment step. The diffused region or doped polysilicon may be silicided to have a low resistance value. The use of doped polysilicon as a doping source for the source / drain region 38 has the advantage of providing a shallow volume of material while providing a large volume of material for the source / drain region 38. Shallow junctions reduce short channel effects. The larger size of the material allows for silicidation without the risk of increasing junction leakage currents.

The following steps provide node straps, wordline connectors and bitline contacts, which are described by patent-pending Wendell Noble, which is incorporated herein by reference. A Five Square Folded-Bitline DRAM Cell "(" Noble Patent Application "). In summary, the intrinsic polysilicon mandrel is deposited and a contact opening is formed therein. Strongly doped polysilicon is then deposited to form a strap between the node polysilicon and the node diffusions. Selective etching is then used to remove the intrinsic polysilicon and leave the strongly doped straps.

As illustrated in FIGS. 7 and 8, the microscopic word line interconnect wiring 40 is formed as a spacer along the groove 44 of the sidewall 42 in the second intrinsic polysilicon main shaft 46. do. Insulating layer 48 is deposited and planarized to cap layer 18, followed by intrinsic polysilicon spindle 46 (FIG. 7). The grooves 44 in the major axis 46 are formed photolithographically aligned so that the sidewalls 42 extend over a portion of the gate conductor 16. The etching to form the grooves 44 extends down through the major axis 46 to expose the nitride cap layer 18 over the gate segment. A portion of the nitride cap layer 18 exposed in the groove 44 by directional etching is removed from the gate conductor layer 16. Next, a conductor, such as tungsten, aluminum, or doped polysilicon, is deposited and directionally etched, leaving a micro-sized conductive sidewall spacer rail 40 in contact with the gate conductor 16 along the sidewall 42 ( 8).

9-13 illustrate another aspect of the present invention, illustrating the steps of interconnecting the gate segments of transistor 139 with conductive wiring level 140 separated by raised STI 30. Transistor 139 may be part of a logic circuit, an SRAM, or other semiconductor circuit. In this aspect of the invention, conductive wiring level 140 is formed prior to the steps illustrated in FIG. After planarizing the dielectric of the raised STI 30 (FIG. 4), the planarization continues, and the planarization stops on the surface of the gate conductor 16 as shown in FIG. Next, as shown in FIG. 10, a second conductor used for the conductive wiring level 140, such as doped polysilicon or tungsten, is deposited. Conductive wiring level 140 is formed of a low resistive material, such as metal or metal silicide. The conductive wiring level 140 is suitable for metals such as tungsten, molybdenum, titanium, and aluminum. Low resistive materials may be deposited by methods well known to those skilled in the art, such as chemical vapor deposition. It may also be formed from strongly doped polysilicon. Next, the insulating layer 150 can also be deposited. Then, using the source / drain defining the mask as described above (FIG. 5) and etching two conductors (gate conductor 116 and conductive wiring level 140), as shown in FIG. 11, Gate conductor 116 is substantially confined to the active region of each transistor and conductive interconnect level 140 extends over STI 30 to interconnect transistors or cells. The dielectric spacer 152 formed in the next step (FIG. 12) coats both the gate segments and the conductive wiring level interconnects. Although the interconnect wiring in this aspect of the invention is not micro sized, this aspect still provides other advantages of the invention described below while providing a simpler manufacturing process.

In the aspects of the invention illustrated in FIGS. 9-13, a medium dose of dopant such as arsenic or boron (less than 1 × 10 ¹⁴ cm ⁻² ) prior to forming the spacer 152 (FIG. 11) Injecting to form a source / drain extension for the source / drain 138. Subsequently, after the spacer 152 is formed (FIG. 12), intrinsic polysilicon (or intrinsic amorphous silicon) is deposited for the raised source / drain 154 as shown in FIG. 13. The dopant for the raised source / drain is implanted at low energy to prevent damaging the underlying single crystal silicon. The dopant is then diffused from the polysilicon to form a very shallow junction 156 without damage. A refractory metal such as titanium is then deposited and annealed to form silicide 158 in polysilicon of the raised source / drain 154. In this way, a very shallow junction 156 is formed having both low resistance and very low leakage current associated with the silicide. The junction thus formed may have a low depth of about 500 mm 3. Of course, other methods of doping polysilicon of the raised source / drain 154, such as in situ doping, may be used.

The device and isolation structure of the present invention described above provides several key advantages. First, the STI and storage trench corner leakage problems are: (1) because gate dielectric layers are formed on a flat surface before the device edges are defined, the problem of sharpened corners and thinning of the dielectric is eliminated, and (2) gates Problems are reduced because the gating of the sidewalls of the channel or its corners by this gate is eliminated because bounded by raised separators that do not wrap around the corners.

Second, because the polysilicon gate 116 does not extend out of the region below the STI 30, the doped region and STI thickness conditions under the STI 30 may be flexible.

Third, as disclosed in the Noble's application, when the word line conductors interconnecting the gate segments are micro-sized spacer rails, the layout distance between individual device gates can actually be reduced. In the DRAM cell disclosed in Noble's application, it is possible to save DRAM cell area by, for example, about 37.5%.

While the invention has been described and illustrated in detail with reference to the accompanying drawings and some embodiments, it can be seen that various other modifications are possible without departing from the scope of the invention. For example, various materials may be used for the main shaft 46, rail 40, or conductive wiring level 140. The present invention can implement n- or P-channel transistors with corresponding variations in doping of polysilicon straps and node polysilicon. It is intended that the invention be limited only by the appended claims. The embodiments given are intended to be illustrative only rather than exclusive.

The present invention relates to a semiconductor structure comprising a transistor having gate conductors having first and second edges bounded by raised isolation structures (ie, STIs). The source diffusion is self aligned with respect to the third edge of the gate electrode and the drain diffusion is self aligned with respect to the fourth edge of the gate electrode.

Claims (20)

As a semiconductor structure, A segment of a thin film dielectric and an individual gate conductor, wherein the gate conductor extends substantially simultaneously with the thin film dielectric, and has an upper surface having first and second edges facing each other and third and fourth edges facing each other A transistor having a gate comprising: A raised separation structure bounding the first and second edges, A source self-aligned to the third edge and a drain self-aligned to the fourth edge, ④ conductive wiring level in contact with the upper surface Semiconductor structure comprising a. The method of claim 1, The gate conductor is blanket deposited on a blanket thin film insulator on a flat surface and defined using a masking process. The method of claim 1, The thin film insulator has a uniform thickness and extends into the raised isolation structure. The method of claim 1, The raised isolation structure includes a shallow trench isolation. The method of claim 1, The raised isolation structure includes a trench capacitor. The method of claim 1, Wherein the source and drain comprise raised sources / drains. The method of claim 1, Wherein the raised source and drain are formed from one of deposited polysilicon or deposited amorphous silicon. The method of claim 1, Wherein the raised source and drain are formed by selective silicon growth. The method of claim 1, The raised source and drain further include silicide. The method of claim 1, Wherein the raised source and drain comprise a very shallow junction. In a semiconductor structure, A gate dielectric comprising a segment of a thin film dielectric and an individual gate conductor, the gate conductor substantially extending simultaneously with the thin film dielectric and having an upper surface having first and second edges facing each other. With transistors, (Ii) has a substantially vertical sidewall abutting the first and second edges, the separation structure delimiting the first and second edges, The dielectric having a substantially uniform thickness and extending into the raised isolation structure. In the method of forming a FET, Providing a substrate having a gate stack comprising a gate dielectric layer and a gate conductor layer, the gate stack comprising a top surface; (2) removing the first portion of the gate stack and etching the trench in the substrate to expose it for the raised separator; (3) depositing an insulator and planarizing the top surface of the stack; ④ removing the second portion of the gate stack for the source / drain regions and exposing sidewalls of the gate stack adjacent to the source / drain regions; (5) forming a spacer adjacent said exposed sidewall of said gate stack; ⑥ forming a source / drain diffusion in the exposed portions of the source and drain regions FET forming method comprising a. The method of claim 12, Said step (6) is achieved by forming a raised source / drain and diffusing it from said raised source and drain. The method of claim 13, The raised source / drain deposits amorphous or polycrystalline silicon, planarizing the silicon, and etching the silicon, wherein the etching step is performed within the exposed portion of the source / drain region. Forming a portion of the silicon; The method of claim 14, And dope the silicon. The method of claim 14, And the planarization step is achieved by polishing. The method of claim 14, And wherein said planarization step is accomplished by planarizing etch. The method of claim 13, Wherein the raised source / drain is formed by forming selective silicon seeded from the source / drain region. The method of claim 13, And siliciding the raised source and drain. In the method of forming an integrated circuit, (1) forming a gate electrode on the semiconductor substrate, the gate electrode including first and second edges; (2) forming a separator on the substrate, the separator being in contact with the first and second edges; (3) defining the third and fourth edges by etching the electrodes; ④ forming a diffusion region in the substrate that is in contact with the third and fourth edges Integrated circuit forming method comprising a.

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