KR100200080B1 - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A semiconductor device disclosed to reduce collector resistance and to provide a high performance bipolar transistor includes: a semiconductor layer formed on a substrate of a first conductivity type; A second conductivity type well region formed at a predetermined position on the surface of the semiconductor layer and having an impurity concentration decreasing vertically downward from the surface; A buried region of a second conductivity type formed adjacent between the well region and the substrate and having a higher impurity concentration than an adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad in contact with the exposed area of the buried area and extending to a predetermined portion of the periphery of the opening including the opening, the conductive pad having a uniform thickness; And a metal electrode in contact with the extension of the conductive pad.

Description

Semiconductor device and manufacturing method thereof

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a bipolar transistor and a method for manufacturing the same.

Recently, BiCMOS technology combining the CMOS technology with the advantages of high integration and low power consumption and the bifora technology with the advantage of high speed operation has been actively studied. BiCMOS technology is based on CMOS technology, the main problem is how to achieve the best high-performance bipolar technology at the same time with a minimum of additional processes.

On the other hand, in the BiCMOS gate circuit driving the high capacitive load, the collector resistance of the bipolar transistor greatly affects the gate delay. Therefore, collector resistance must be minimized to realize high performance BiCMOS circuit. In order to reduce the collector resistance, a deep N + collector contact technique has been conventionally disclosed as shown in FIG. However, the deep N + collector contact technique must maintain a relatively large collector base spacing to prevent the collector-base breakdown voltage from deteriorating due to lateral diffusion of impurities in forming the deep N + region. This spacing hinders the high integration because it limits the reduction of the design dimension of the bipolar transistor. In order to solve such a problem, a deep N + polysilicon plug contact technique shown in FIG. 2 has been conventionally proposed. This is described in Diegest of Technical Papers, 1988 International Electron Devices Meeting. pp.756-759. December 1988. and IEDM 90. pp. 493-496. Such a deep N + polysilicon plug contact technology has an advantage of suppressing lateral diffusion of N + impurities by sidewall dielectric films and reducing design dimensions of transistors. However, the deep N + polysilicon plug contact technology is a complicated process because the collector trench etching process, the side diffusion preventing sidewall spacer forming process, and the polysilicon trench investment process are added for the collector contact of the bipolar transistor, regardless of the CMOS process. There was this. In addition, there was a fear that voids are generated when the trench is buried with polysilicon. This void generation increases the collector resistance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of reducing collector resistance and providing a high performance bipolar transistor and a method of manufacturing the same in order to solve the problems of the prior art.

Another object of the present invention is to provide a high-performance BiCMOS SRAM semiconductor device and a method for manufacturing the same by adding a minimal process to the SRAM semiconductor device and its manufacturing process based on the CMOS process.

In order to achieve the above object of the present invention, the semiconductor device of the present invention, the semiconductor substrate of the predetermined conductivity type formed on the first conductive semiconductor substrate; A second conductivity type well region formed at a predetermined position on the surface of the semiconductor layer and having an impurity concentration decreasing vertically downward from the surface; A buried region of a second conductivity type which is formed between the well region and the semiconductor substrate and has a higher impurity concentration than an adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad in contact with the exposed area of the buried area and extending to a predetermined portion of the periphery of the opening including the opening, the conductive pad having a uniform thickness; And a metal electrode in contact with the extension of the conductive pad.

The manufacturing method of the present invention is a method of manufacturing a BiCMOS semiconductor device having a CMOS transistor and a bipolar transistor on the same wafer, wherein the first conductive layer and the first conductive layer of the first conductivity type are formed on the surface of the semiconductor substrate of the first conductivity type. Forming a second buried layer of a mold; Growing an epitaxial layer on the surfaces of the first and second buried layers; Forming a first well of a first conductivity type and a second well of a second conductivity type in the epitaxial layer; PMOS transistors or bipolar transistors are formed in the vicinity of the surface of the second well of the second conductivity type on the second buried layer of the second conductivity type, and the first conductivity type first on the first buried layer of the first conductivity type is formed. Forming an NMOS transistor near the surface of one well; Forming an opening for a second buried layer contact in a second well in which said bipolar transistor is to be formed after said transistor is formed; After the opening is formed, a conductive material is deposited on the entire surface, and the deposited conductive material is patterned to simultaneously provide an interconnection and a conductive pad.

1 is a vertical cross-sectional view of a deep impurity contact type NPN bipolar transistor having a conventional impurity doped buried layer.

2 is a vertical cross-sectional view of a conventional polysilicon plug contact NPN bipolar transistor having an impurity doped buried layer.

3 is a vertical cross-sectional view of a conductive pad contact type bipolar transistor having an impurity doped buried layer in accordance with an embodiment of the present invention.

4 to 20 are diagrams illustrating a manufacturing process sequence of the semiconductor device of FIG. 3.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 shows a cross-sectional structure of a bipolar transistor using the conductive pad collector contact technique according to the present invention. 3, 10 is a P-type semiconductor substrate, 12 is an N + buried layer, 16 is an N well, 18 is a P well, 22 is a P base or inner base, 24 is a P + base or an outer base, 26 is an N + emitter, 52 is Emitter polysilicon, 54 is emitter metal silicide, 30 is base electrode, 32 is emitter electrode, 34 is collector electrode, 36 is opening, 44 is N ++ doped polysilicon, 46 is metal silicide, 48 is extension , 50 is the conductive pad. As shown in the third embodiment, in the present invention, a contact is formed by the conductive pad 50 between the N + buried layer 12 and the collector electrode 34 of the bipolar transistor, thereby providing a conventional N + doped polysilicon plug contact technique. Compared to the simple process, the collector contact resistance can be reduced. In addition, the conductive pad contact technique of the present invention does not need to form a side diffusion preventing spacer dielectric film used in the conventional plug contact technique on the inner wall of the opening 36. Because the conventional method forms the plug in advance before the base is formed, a sufficient gap in advance to prevent the impurities from laterally diffusing from the N + doped polysilicon plug by the subsequent heat treatment process and narrowing the gap between the base collectors. Or kept. However, in the present invention, after the base is formed, the conductive pad 50 is formed together with the emitter polysilicon 52 and the emitter metal silicide 54 to not only eliminate the effects of subsequent thermal processes but also simplify the process. have.

In order to look at the contents of the present invention in more detail with reference to the embodiment shown in Figures 4 to 20 will be described in detail.

Referring to FIG. 4, the pad oxide film 1a and the nitride film 1b are sequentially formed on the P-type substrate 100 having a low concentration, and the pad oxide film 1a and the nitride film 1b are laminated for a normal photolithography process. After patterning the structure to open the P buried region, P-type impurities such as boron are injected.

Referring to FIG. 5, when the thermal oxidation process is performed after the P-type impurity is implanted, a thick oxide film 3 is formed only on the substrate surface of the P-embedded region without the nitride film 1b, and the P-type impurities are diffused to form P. Mold impurity layers 102, 102a and 102b are formed. Subsequently, the nitride film is removed and ion implantation of N-type impurities such as anaceous acid is carried out at high concentration using the oxide film 3 as a mask.

Subsequently, when the thermal process is performed at a high temperature for a long time and the oxide film 3 is completely removed, the P-type impurity layers 102, 102a and 102b and the N + -type impurity layers 104, 104a and 104b are shown in FIG. Is formed.

Referring to FIG. 7, 1.51 is formed on a substrate surface on which the impurity layers are formed. An epitaxial layer 5 (hereinafter referred to as an epitaxial layer) of about m is grown. The P-type impurity layers 102, 102a and 102b and the N + -type impurity layers 104, 104a and 104b between the substrate 100 and the epi layer 5 become P-type buried layers and N + -type buried layers, respectively. .

8 shows the formation of the N-type impurity layers 106, 106a and 106b and the P-type impurity layers 108, 108a and 108b using a conventional LOCOS process. The N-type impurity layers 106, 106a and 106b are formed on the N + buried layers 104, 104a and 104b and the P-type impurity layers 108, 108a and 108b are the P-type buried layers 102 and 102a. 102b), wherein the N-type impurity layer is a region in which the PMOS transistor 106a and the bipolar transistor 106b are formed as N wells, and the P-type impurity layer is an NMOS transistor 108a as a P well. And an SRAM memory element 108b is formed.

9 shows a field oxide film 110 for electrical insulation between devices in a portion of the epi layer where N wells 106, 106a and 106b and P wells 108, 108a and 108b are formed and a gate oxide film of a MOS transistor. The formation of 112 is shown.

Referring to FIG. 10, polysilicon (114, 118, 122) is coated on the entire surface, and metal silicide (116, 120, 124) is applied on the entire surface. Next, the polysilicon 114, 118, 122 and the metal silicides 116, 120, and 124 are patterned into a specific shape using a conventional photolithography process. In this case, some polysilicon and metal silicides 114 and 116 (hereinafter referred to as 'polyside') are used together with the gate oxide film 112 as a gate for the MOS structure of the MOS transistor, and the other polysides 122 and 124. Is used as a conductive layer for the electrical connection between the devices, and another part of the polysides 118 and 120 is used as a protective film for protecting the active region of the bipolar transistor.

Referring to FIG. 11, a N-type LDD is formed by ion implanting Phosphorus ions at a dose amount of 3.0E13 # / cm 2 and an ion implantation energy of 40 KeV without using a photographic process on the entire surface of the resultant. In this case, the passivation layers 118 and 120 of the bipolar transistor serve as a mask to prevent the Phosphorus ions from being injected into the active region of the bipolar transistor. After that, all the regions except for the active region of the PMOS transistor are coated with a photoresist film using a conventional photolithography process, and then BF 2 ions are implanted at a dose of 4.4E13 # / cm 2 and an ion implantation energy of 40 KeV, for example, to form a P-type. LDD 126 is formed. At this time, since the dose of the BF 2 ion for forming the P-type LDD 126 is greater than that of the Phosphorus ion for forming the N-type LDD 128, the N-type LDD 128 is formed in the NMOS transistor and the PMOS transistor is formed in the PMOS transistor. P-type LDD 126 is formed.

Referring to FIG. 12, when an oxide film is applied to a thickness of about 3000 kPa and an anisotropic dry etching process is performed, spacers are formed on sidewalls of the polyside layers 114, 116, 118, 120, 122, and 124. This is to form the LDD structure of the MOS transistor. In this case, the polyside passivation layers 118 and 120 of the bipolar transistor prevent the active region of the bipolar transistor from being damaged during the anisotropic dry etching process.

Referring to FIG. 13, the photoresist film is formed using a conventional photolithography process so that the first connection window 132a for the collector power connection of the polyside protective films 118 and 120 and the bipolar transistor of FIG. 12 is sufficiently exposed. When the dry etching process is performed after the formation of (7), the polyside layers 118 and 120 are removed and single crystal silicon of the primary collector power connection window 132a is also etched, which is the core of the present invention. It is one of the processes.

Referring to FIG. 14, immediately after the etching process, boron ions are injected without removing the photoresist film 7, for example, with a dose amount of 2.0E13 # / cm 2 and an ion implantation energy of 50 KeV, thereby forming a P-type internal base. P-type impurity layer 134 is formed. In this case, the P-type impurity layer 134 may be formed in the region of the primary collector power connection window 132a of the bipolar transistor. This is because as the subsequent process proceeds, the P-type impurity layer in the primary collector power connection window 132a is removed and is sufficiently offset by the high concentration of N-type impurity.

Referring to FIG. 15, after removing the photoresist film 7 from the resultant, a photoresist film is formed on the resultant using a conventional photolithography process so that the NMOS transistor region is exposed. Ion implantation with E15 # 15 / cm2 and ion implantation energy of 40 KeV forms the source and drain 136 of the NMOS transistor and the source and drain 138 of the NMOS transistor for an SRAM memory device. After removing the photoresist film, a photoresist film was formed using a conventional photolithography process so that the primary collector power connection window 132a region of the bipolar transistor was exposed, and then a Phosphorus ion was formed, for example, a dose amount of 5.0E15 # / cm2 and an ion. The deep N + type impurity layer 140a is formed by implanting with an implantation energy of 80 KeV. The deep N + type impurity layer 140a is adjacent to the N + buried layer 104b in the vertical direction and affects reducing the collector resistance of the bipolar transistor. The deep N + type impurity layer 140a is also formed in an NMOS transistor for preventing electrostatic discharge (ESD) (not shown). After removing the photoresist film, the photoresist film is formed using a conventional photolithography process so that a part 144 of the PMOS transistor region and the base region of the bipolar transistor are exposed, and then the BF2 ion is formed, for example, with a dose amount of 5.0E15 # / cm2. Ion implantation is performed with ion implantation energy of 30 KeV to form the source and drain regions of the PMOS transistor and the outer base region 144 of the bipolar transistor.

Referring to FIG. 16, an oxide film 146 is coated on the entire surface of the resultant layer for interlayer insulation, and then a ground power connection region 148b for a thin film transistor-loaded SRAM memory device using a conventional photolithography process. ), A photoresist film is formed to expose the word line power supply connection region 148c, the emitter power electrode connection region 148a of the bipolar transistor, and the collector power connection window 132b region of the bipolar transistor. Remove the oxide film. In this way, the connection windows are formed in each connection region, and the single crystal silicon is exposed by removing the oxide film 146 in the region of the primary collector power connection window 132b of the bipolar transistor.

Referring to FIG. 17, the electrical ground power lines 154 and 156 of the TFT-loaded SRAM memory devices, the word lines 158 and 160 of the TFT-loaded SRAM memory devices, and the emitter power electrodes 150 and 152 of the bipolar transistors are formed. As shown, polysilicon (150, 154, 158) is applied to the entire surface of the resultant with a thickness of about 1000 kPa, As ion is injected into the front surface, for example, dose of 7.0E15 # / cm2 and ion implantation energy of 100 KeV, Metal silicides such as tungsten silicides 152, 156, and 160 are applied to the entire surface at a thickness of 1500 Å, and the polysilicon 150, 154, 158 and the metal silicides 152 of the laminated structure are fabricated using a conventional photolithography process. 156 and 160 are shaped into a predetermined shape. Meanwhile, when the etching process is performed, the single crystal silicon in the collector power connection window 132b is simultaneously etched to form the primary collector power connection window 132c as shown in FIG. 17, which is also the core of the present invention. It is one of the processes. As implanted into the polysilicon (150, 154, 156) is diffused into the silicon during the subsequent thermal process to form the emitter 164 of the bipolar transistor.

18 shows a process of forming a TFT bottom gate 162c of a load type SRAM storage element, an interconnection line 162b of a load type SRAM storage element, and a conductive pad 162a for power connection of a collector of a bipolar transistor. After the oxide film 166 for interlayer insulation was applied to a thickness of about 2000 kW, the first collector power connection window 132d of the bipolar transistor and the interconnection line connection area 163 of the SRAM memory device were exposed. After forming the photoresist film and removing the exposed oxide film 166, polysilicon 162a, 162b, and 164c were applied to the front surface of the resultant at a thickness of 1000 하고 and Ph ions were applied to the front surface, for example, the dose amount 7.0E15 # / cm2. And 100KeV of ion implantation energy, and the polysilicon 162a, 162b, 162c of the laminated structure is formed into a predetermined shape by using a conventional photolithography process. Ph implanted into the polysilicon 162a, 162b, and 162c diffuses into silicon as the thermal process proceeds in a subsequent process, thereby increasing the concentration of the deep N + type impurity layer 140b of FIG. 17 to increase the collector resistance of the bipolar transistor. Help reduce Therefore, some polysilicon 162a is used as a conductive pad for a collector power electrode of a bipolar transistor, and another polyside 162b is used as an interconnection line of a resistive SRAM memory device, and another part of poly The side 162c is used as the TFT bottom gate of the load type SRAM memory device.

FIG. 19 illustrates the formation of the TFT source and drain 170a and the channel 170b of the load type SRAM memory device. The intercon of the load type SRAM memory device is coated after the oxide film 168 is applied to a thickness of about 500 GPa. The oxide film 168 in the connection window 163 area for the connection is etched using a conventional photolithography process. At this time, the oxide film 168 becomes a gate oxide film of a load type SRAM memory device. Next, polycrystalline silicon 170a and 170b are coated to a thickness of about 500 GPa, and a photoresist film is formed so as to expose the TFT source and drain 170a regions of the load-type SRAM memory device, and a BF2 ion is used, for example, a dose amount of 1.0E15 # /. After implanting cm2 and ion implantation energy at 30 KeV, the polycrystalline silicon (170a, 170b) is patterned into a specific shape by using a conventional photolithography process, so that the TFT source and drain (170a) and the channel ( 170b).

FIG. 20 illustrates a process of forming the electrodes of the MOS transistor and the bipolar transistor, in which a hot temperature oxide (HTO) is laminated on the resultant, and then a BPSG (Boro-Phosphorus Silicate Glass) is laminated, and the planarization process is performed. Next, the HTO and BPSG films on the regions 172, 174, 176, 178, and 180 where the electrodes are to be formed are removed by using a conventional photolithography process to form a connection window, and to completely fill the window on the front of the BPSG. The conductive materials 182, 184, 186, 188, and 190 are deposited and then patterned to complete each of the electrodes.

The present invention is not limited to the above-described embodiments, but can be easily modified by those skilled in the art within the spirit and scope of the present invention described in the claims below.

As described above, in the present invention, the collector contact of the N + buried layer 104b of the bipolar transistor can be used to reduce the collector resistance by using the contact pad structure without using the deep N + doped layer structure or the polysilicon plug plug structure and simplify the process. It can be effective.

Claims (6)

A bicymos semiconductor device formed on the same wafer, comprising: a semiconductor layer of a predetermined conductivity type formed on a semiconductor substrate of a first conductivity type; A second conductivity type well region formed at a predetermined position on the surface of the semiconductor layer and having an impurity concentration decreasing vertically downward from the surface; A buried region of a second conductivity type which is formed between the well region and the semiconductor substrate and has a higher impurity concentration than an adjacent portion of the well region; An opening formed in the semiconductor layer to expose a predetermined portion of the buried region; A conductive pad in contact with the exposed area of the buried area and extending to a predetermined portion of the periphery of the opening including the opening, the conductive pad having a uniform thickness; And a metal electrode in contact with an extension of the conductive pad. 2. The semiconductor device of claim 1, wherein the buried region is a high concentration collector of a bipolar transistor. 2. The semiconductor device of claim 1, wherein the conductive pad is any one of an impurity doped polysilicon, an impurity doped amorphous silicon, or a stacked structure thereof. 2. The semiconductor device of claim 1, wherein the conductive pad has a stacked structure of impurity doped polysilicon and metal silicide. A method of manufacturing a BiCMOS semiconductor device having a CMOS transistor and a bipolar transistor on the same wafer: a first buried layer of a first conductivity type and a second buried layer of a second conductivity type on a surface of a first conductive semiconductor substrate Forming a; Growing an epitaxial layer on a surface of the semiconductor substrate on which the first and second buried layers are formed; Forming a first well of a first conductivity type and a second well of a second conductivity type in the epitaxial layer; The first conductive material is deposited on the surface of the first well of the first conductivity type and the surface of the second well of the second conductivity type, and the deposited first conductive material is patterned to form the first buried layer of the first conductivity type. NMOS transistors or NMOS transistors for load resistance type SRAM storage elements are formed in the vicinity of the surface of the first well of the first conductivity type of the first conductivity type, and the surface of the second well of the second conductivity type on the second buried layer of the second conductivity type is formed. Forming a protective film in a region where a gate of the PMOS transistor and a base of the NPN bipolar transistor are to be formed; Forming a photoresist film for etch prevention and ion implantation prevention so that the entire region where the bipolar transistor is to be formed is exposed, removing the protective film, and simultaneously forming an opening for a second buried layer contact, and forming a base of the NPN bipolar transistor. Performing ion implantation for formation and removing the photosensitive film; After the opening is formed, the second conductive material is deposited on the front surface and patterned to form a word line of the load resistance SRAM memory device and a ground power supply wiring of the load resistance SRAM memory device, and at the same time, the collector of the NPN bipolar transistor. Etching the silicon of the opening region for the second buried layer contact used as the power connection window of the trench to deepen the opening; After forming the opening, depositing a third conductive material on the front surface and patterning the deposited third conductive material to simultaneously form a bottom gate of the load resistance type SRAM memory device and a conductive pad for the second buried layer contact. Manufacturing method characterized in that it comprises. 6. The method according to claim 5, wherein the first, second and third conductive materials are polysides of impurity doped polysilicon and metal silicide.