KR100546812B1 - Fabricating method of semiconductor device - Google Patents

Abstract

According to the present invention, in forming a halo region of a semiconductor device, the implanted halo ions can be prevented from diffusing into the channel region and the source / drain region of the transistor, and at the same time, the profile of the halo region defined as the implanted halo ions can be finely adjusted. A semiconductor device manufacturing method,

A semiconductor device manufacturing method according to the present invention comprises the steps of forming a gate insulating film and a gate electrode on a semiconductor substrate; and sequentially stacking a first insulating film and a second insulating film on the entire surface of the substrate including the gate electrode; Selectively removing the first insulating film and the second insulating film to form a spacer including first and second spacers on the left and right sidewalls of the gate electrode; and on the gate electrode surface and the semiconductor substrate surface on the left and right sides of the gate electrode. Forming a salicide layer on the substrate; and performing a high concentration of a second conductivity type impurity ion implantation process for source / drain formation on the entire surface of the substrate including the salicide layer; and removing the second spacer. Exposing a semiconductor substrate in a predetermined region to the left and right of the gate electrode; Implanting impurity ions to form a halo region in an exposed region of the semiconductor substrate; and forming a source / drain region by heat treating the semiconductor substrate and activating the halo region. do.

Halo, pocket

Description

Fabrication method of semiconductor device             

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Description of the main parts of the drawing

101 semiconductor substrate 102 device isolation film

103: gate insulating film 104: gate electrode

105a: first spacer 105b: second spacer

106: salicide layer 107: high concentration ion implantation region

108: halo area

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, in forming a halo region of a semiconductor device, the implanted halo ions prevent the diffusion of the implanted halo ions into the channel region and the source / drain region of the transistor and at the same time, The present invention relates to a method of manufacturing a semiconductor device capable of finely controlling a profile of a halo region.

In general, as the integration of semiconductor devices proceeds, the size of the semiconductor device is reduced and the channel length of the semiconductor device is also reduced. However, as the channel length of the semiconductor device is reduced, undesired electrical characteristics of the semiconductor device, for example, a short channel effect appear.

In order to solve the short channel effect, a vertical reduction such as a thickness of the gate insulating layer and a junction depth of a source / drain must be performed along with a horizontal reduction such as a reduction of the gate electrode length. In addition, the horizontal reduction and the vertical reduction reduce the voltage of the applied power supply, increase the doping concentration of the semiconductor substrate, and in particular, control the doping profile of the channel region should be efficiently performed.

However, since the size of semiconductor devices is being reduced but the operating power required by electronic products is not yet low, for example, in the case of an NMOS transistor, electrons injected from a source are accelerated severely in a high potential gradient state of the drain. Hot carriers are susceptible to fragile structures. Accordingly, a lightly doped drain (LDD) structure has been proposed to improve an NMOS transistor vulnerable to the hot carrier.

In the LDD transistor, a low concentration (n−) region is positioned between a channel and a high concentration (n +) source / drain, and the low concentration (n−) region buffers a high drain voltage around the drain junction to cause a sudden potential change. By not doing so, the generation of hot carriers is suppressed. As the manufacturing technology of high-density semiconductor devices has been studied, various techniques for manufacturing MOSFETs of LDD structures have been proposed. Among them, the LDD manufacturing method for forming spacers on the sidewalls of the gate electrode is the most typical method and is used in most mass production techniques.

However, as the semiconductor devices have been highly integrated in recent years, the formation of the LDD alone does not completely control the short channel effect, and thus does not affect the doping concentration of the channel region that determines the threshold voltage of the transistor. A halo structure has been proposed which suppresses the depletion regions of the drain from approaching each other in the horizontal direction.

The halo structure is formed by implanting impurities of opposite polarity around the source / drain, that is, halo ions, by surrounding a diffusion region having an impurity concentration higher than the well concentration around the source / drain of the field effect transistor. Reduce the length of the depletion region of the source / drain.

However, in the case of a semiconductor device such as a MOS transistor manufactured by a conventional halo ion implantation method, doped impurities in the source / drain region, e.g., when a heat treatment process for forming a junction of a source / drain region of a MOS transistor are performed, For example, boron (B) or phosphorus (P) also tends to diffuse into the channel region due to heat treatment. This adversely affects the channel region and degrades the electrical characteristics of the MOS transistor. In other words, since the threshold voltage (V _T ) of the MOS transistor is changed from the original predetermined value, it is difficult to distinguish the turn on and turn-off operation of the MOS transistor, resulting in frequent malfunction of the MOS transistor and leakage. The leakage current increases.

The present invention has been made to solve the above problems, while preventing the implanted halo ions to diffuse into the channel region and the source / drain region of the transistor and at the same time finely profile the halo region defined by the implanted halo ions An object of the present invention is to provide a method for manufacturing a semiconductor device that can be adjusted.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can easily implement a shallow junction (shallow junction).

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate insulating film and a gate electrode on a semiconductor substrate; and sequentially, the first insulating film and the second insulating film on the entire surface of the substrate including the gate electrode Stacking; and selectively removing the first insulating film and the second insulating film to form a spacer including first and second spacers on the left and right sidewalls of the gate electrode; and the gate electrode surface and the gate electrode. Forming a salicide layer on the left and right semiconductor substrate surfaces; and performing a high concentration of a second conductivity type impurity ion implantation process for source / drain formation on the entire surface of the substrate including the salicide layer; and Removing the second spacers to expose the semiconductor substrate in predetermined regions on the left and right sides of the gate electrode; Implanting first conductivity type impurity ions into the entire surface of the substrate to form a halo region in an exposed region of the semiconductor substrate; and heat treating the semiconductor substrate to form a source / drain region and simultaneously activating the halo region. Characterized in that comprises a.

Preferably, the impurity ions of the first conductivity type may be n-type impurity ions, and the impurity ions of the second conductivity type may be p-type impurity ions.

Preferably, the impurity ions of the first conductivity type may be phosphorus (P) ions.

Preferably, the first conductivity type impurity ions forming the halo region may be implanted on the entire surface of the substrate at a concentration of 5E13 to 5E14 ions / cm ² at an energy of 10 to 50 KeV.

Preferably, the forming of the halo region may include implanting the first conductivity type impurity ions at an angle of 5 to 30 ° inclined downward with respect to the vertical axis of the semiconductor substrate.

Preferably, the second conductivity type impurity ions which are the source / drain formation ions may be implanted on the entire surface of the substrate at an energy of 1 to 30 KeV and a concentration of 1E15 to 1E16 ions / cm ₂ .

Preferably, the heat treatment process of the substrate is performed by applying a temperature of 900 ~ 1050 ℃ and a process time of 10 to 20 seconds under an inert gas atmosphere.

According to a feature of the present invention, the source / drain ion implantation can be implemented after the salicide process to realize a shallow junction of the source / drain. You can control it.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

First, as illustrated in FIG. 1A, in order to define an active region for a semiconductor substrate 101 made of a single crystal silicon or the like, an isolation process, for example, a shallow trench isolation (STI) process, is used. An element isolation film 102 is formed in the field region of 101. Here, the first conductive single crystal silicon substrate 101 may be used as the semiconductor substrate 101, and the first conductive type may be n type or p type. For convenience of description, the present invention will be described based on the case where the first conductivity type is n-type.

After the formation of the device isolation layer 102 is completed, the gate insulating layer 103 is grown on the active region of the semiconductor substrate 101 by a thermal oxidation process. Subsequently, for example, BF ₂ ions are implanted near the surface of the semiconductor substrate 101 to adjust the threshold voltage of the channel region to a desired value although not shown in the drawing.

Subsequently, a conductive layer for the gate electrode 104 is laminated on the gate insulating layer 103. The conductive layer may be composed of only a high concentration of a polysilicon layer or together with a silicide layer thereon.

Referring to FIG. 1B, once the conductive layers for the gate electrode 104 are stacked, a gate electrode 104 is formed on the conductive layer in a region where the gate electrode 104 is to be formed using a conventional photolithography process. A pattern of an etching mask photosensitive film (not shown) corresponding to the pattern of is formed. Subsequently, when the conductive layer and the gate insulating layer 103 under the pattern of the photoresist layer are left and the conductive layer and the gate insulating layer 103 in the remaining areas are exposed. Etch until Accordingly, the pattern of the gate electrode 104 and the gate insulating film 103 is formed on a portion of the active region. In such a state, the first insulating layer 105a is stacked on the entire surface of the substrate 101 including the gate electrode 104 by using a Tetra Ethyl Ortho Silicate (TEOS) chemical vapor deposition process. An oxide film may be used as a material of the first insulating film 105a. Subsequently, a second insulating film 105b is stacked on the first insulating film 105a. A nitride film may be used as the material of the second insulating film 105b.

As shown in FIG. 1C, when the first and second insulating layers 105a and 105b are stacked, the dry etching process having anisotropic etching characteristics, for example, the reactive ion etching process may be performed. 2 Etch the insulating film. At this time, the gate electrode and the first insulating film on the source / drain regions on the left and right sides of the gate electrode are also etched. Accordingly, a spacer 105 including a double layer of a first spacer 105a of a first insulating material and a second spacer 105b of a second insulating material is formed on the sidewall of the gate electrode. The spacer serves as an ion implantation mask for defining a source / drain region, and the second spacer 105b of the spacer is removed during future halo ion implantation.

In the state where the spacer 105 is formed, as shown in FIG. 1D, a high melting point metal layer is laminated on the entire surface of the substrate including the gate electrode using a sputtering process or the like, followed by heat treatment of the substrate to remove the spacer, that is, A silicide reaction between silicon and metal is induced on the surface of the gate electrode 104 and the surface of the semiconductor substrate 101 in the source / drain region. A salicide layer (Salicide: Self Aligned Silicide) 106 is formed on the gate electrode surface and the semiconductor substrate surface on the source / drain region through the silicide reaction. The salicide layer 106 may be formed of a material layer such as MoSi ₂ , PdSi ₂ , PtSi ₂ , TaSi _2, and WSi ₂ , depending on the type of the high melting point metal.

In the state where the salicide layer 106 is formed on the gate electrode surface and the semiconductor substrate surface of the source / drain region, as shown in FIG. 1E, a high concentration of impurity ion implantation process is performed to form the source / drain. Specifically, a high concentration ion implantation region 107 is formed by implanting a second conductivity type p-type impurity ion, for example, boron (B) in the form of an ion of B ⁺ or BF ^{+2 over} the substrate 101. Specifically, the ion implantation may be implanted under conditions of energy of 1 to 30 KeV and 1E15 to 1E16 ions / cm ₂ . On the other hand, as the salicide layer 106 is already formed on the surface of the semiconductor substrate 101 in the source / drain region, the depth of the high concentration impurity ion implantation region perpendicular to the semiconductor substrate is higher than that of the normal source / drain region. It becomes shallow. As a result, the design rule of the semiconductor device can be reduced.

In the state where the high concentration impurity ion implantation process is completed, as shown in FIG. 1F, the second spacer 105b is removed to expose the semiconductor substrate 101 in predetermined regions on the left and right sides of the gate electrode. At this time, the first spacer 105a formed under the vertical axis of the second spacer 105b is also removed by etching. In the state where the second spacer 105b is removed, halo ions, i.e., n-type impurities of the first conductivity type, for example, phosphorus (P) ions, are applied to the entire surface of the substrate 101 with energy of 10 to 50 KeV and 5E13 to 5E14. A halo region 108 is formed in the exposed semiconductor substrate region by implantation at a concentration of ions / cm ² . In this case, the implantation of the halo ions is performed at a predetermined inclined angle, for example, a tilt angle of 5 to 30 ° inclined downward with respect to the vertical axis of the surface of the semiconductor substrate 101. In the case of halo ion implantation, since the first spacers 105a are disposed on sidewalls on the left and right sides of the gate electrode, the implanted halo ions can be prevented from being diffused toward the channel region below the center of the gate electrode.

Subsequently, although not shown in the drawings, the substrate is heat-treated to activate ions implanted in the high concentration ion implantation region 107 to form a source / drain and simultaneously activate ions in the halo region 108 according to the present invention. The semiconductor device manufacturing method is completed. The heat treatment process is carried out at a temperature of 900 ~ 1050 ℃ and a process time of 10 to 20 seconds under an inert gas atmosphere such as nitrogen by applying a rapid heat treatment process.

The semiconductor device manufacturing method according to the present invention has the following effects.

By performing source / drain ion implantation after the salicide process, shallow junctions of the source / drain can be implemented to ensure the miniaturization of the semiconductor device.As a result of the halo ion implantation process after removing the dummy spacer, the profile of the halo region The fine control of the can improve the electrical characteristics of the semiconductor device.

Claims (7)

Forming a gate insulating film and a gate electrode on the semiconductor substrate; Sequentially stacking a first insulating film and a second insulating film on the entire surface of the substrate including the gate electrode; Selectively removing the first insulating film and the second insulating film to form a spacer including first and second spacers on left and right sidewalls of the gate electrode; Forming a salicide layer on the gate electrode surface and the semiconductor substrate surfaces on the left and right sides of the gate electrode; Performing a high concentration of a second conductivity type impurity ion implantation process for source / drain formation on the entire surface of the substrate including the salicide layer; Removing the second spacer to expose a semiconductor substrate in predetermined regions on the left and right sides of a gate electrode; Implanting first conductivity type impurity ions into the entire surface of the substrate to form a halo region in an exposed region of the semiconductor substrate; Heat-treating the semiconductor substrate to form a source / drain region and simultaneously activating the halo region. The method of claim 1, wherein the impurity ions of the first conductivity type are n-type impurity ions, and the impurity ions of the second conductivity type are p-type impurity ions. The method of claim 1, wherein the impurity ions of the first conductivity type are phosphorus (P) ions. The method of claim 1, wherein the first conductivity type impurity ions forming the halo region are implanted on the entire surface of the substrate at a concentration of 5E13 to 5E14 ions / cm ² at an energy of 10 to 50 KeV. . The method of claim 1, wherein the forming of the halo region comprises: And injecting the first conductivity type impurity ions at an angle of 5 to 30 degrees inclined downward with respect to the vertical axis of the semiconductor substrate. The semiconductor device fabrication of claim 1, wherein the second conductivity type impurity ions, which are the source / drain forming ions, are implanted on the entire surface of the substrate at an energy of 1 to 30 KeV and a concentration of 1E15 to 1E16 ions / cm ₂ . Way. The method of claim 1, wherein the heat treatment of the substrate is performed by applying a temperature of 900 to 1050 ° C. and a process time of 10 to 20 seconds under an inert gas atmosphere.

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