KR100588787B1 - Fabricating method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device capable of finely controlling the profile of a halo region defined as implanted halo ions while preventing the implanted halo ions from diffusing into the channel region and the source / drain region of the transistor.

In accordance with another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a gate insulating film and a gate electrode on a semiconductor substrate; and implanting impurity ions of a first conductivity type on the entire surface of the substrate to provide a region corresponding to the diffusion preventing ion region. Forming a halo region in the semiconductor substrate; and injecting diffusion preventing ions onto the entire surface of the substrate to form a diffusion preventing ion region; and implanting impurity ions of a second conductivity type on the substrate; And forming a low concentration ion implantation region in the semiconductor substrate to the left and right of the electrode.

Halo, spread

Description

Fabrication method of semiconductor device             

1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Description of the main parts of the drawing

101 semiconductor substrate 102 device isolation film

103: gate insulating film 104: gate electrode

105: halo region 106: ion region for diffusion prevention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to prevent the implanted halo ions from diffusing into a channel region and a source / drain region of a transistor, and at the same time, to finely define a profile of a halo region defined as implanted halo ions. It relates to a semiconductor device manufacturing method that can be adjusted.

In general, as the integration of semiconductor devices proceeds, the size of the semiconductor device is reduced and the channel length of the semiconductor device is also reduced. However, as the channel length of the semiconductor device is reduced, undesired electrical characteristics of the semiconductor device, for example, a short channel effect appear.

In order to solve the short channel effect, a vertical reduction such as a thickness of the gate insulating layer and a junction depth of a source / drain must be performed along with a horizontal reduction such as a reduction of the gate electrode length. In addition, the horizontal reduction and the vertical reduction reduce the voltage of the applied power supply, increase the doping concentration of the semiconductor substrate, and in particular, control the doping profile of the channel region should be efficiently performed.

However, since the size of semiconductor devices is being reduced but the operating power required by electronic products is not yet low, for example, in the case of an NMOS transistor, electrons injected from a source are accelerated severely in a high potential gradient state of the drain. Hot carriers are susceptible to fragile structures. Accordingly, a lightly doped drain (LDD) structure has been proposed to improve an NMOS transistor vulnerable to the hot carrier.

In the LDD transistor, a low concentration (n−) region is positioned between a channel and a high concentration (n +) source / drain, and the low concentration (n−) region buffers a high drain voltage around the drain junction to cause a sudden potential change. By not doing so, the generation of hot carriers is suppressed. As the manufacturing technology of high-density semiconductor devices has been studied, various techniques for manufacturing MOSFETs of LDD structures have been proposed. Among them, the LDD manufacturing method of forming a spacer on the side wall of the gate electrode is the most typical method and has been used in most mass production technology to date.

However, as the semiconductor devices have been highly integrated in recent years, the formation of the LDD alone does not completely control the short channel effect, and thus does not affect the doping concentration of the channel region that determines the threshold voltage of the transistor. A halo structure has been proposed which suppresses the depletion regions of the drain from approaching each other in the horizontal direction.

The halo structure is formed by implanting impurities of opposite polarity around the source / drain, that is, halo ions, by surrounding a diffusion region having an impurity concentration higher than the well concentration around the source / drain of the field effect transistor. Reduce the length of the depletion region of the source / drain.

However, in the case of a semiconductor device such as a MOS transistor manufactured by a conventional halo ion implantation method, doped impurities in the source / drain region, e.g., when a heat treatment process for forming a junction of a source / drain region of a MOS transistor are performed, For example, boron (B) or phosphorus (P) also tends to diffuse into the channel region due to heat treatment. This adversely affects the channel region and degrades the electrical characteristics of the MOS transistor. In other words, since the threshold voltage (V _T ) of the MOS transistor is changed from the original predetermined value, it is difficult to distinguish the turn on and turn-off operation of the MOS transistor, resulting in frequent malfunction of the MOS transistor and leakage. The leakage current increases.

The present invention has been made to solve the above problems, while preventing the implanted halo ions to diffuse into the channel region and the source / drain region of the transistor and at the same time finely profile the halo region defined by the implanted halo ions An object of the present invention is to provide a method for manufacturing a semiconductor device that can be adjusted.

The semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a gate insulating film and a gate electrode on a semiconductor substrate; and implanting the first conductivity type impurity ions on the entire surface of the substrate to prevent the diffusion Forming a halo region in a semiconductor substrate of a region corresponding to the region; and implanting diffusion preventing ions onto the entire surface of the substrate to form a diffusion preventing ion region; and an impurity of a second conductivity type on the substrate And implanting ions to form a low concentration ion implantation region in the semiconductor substrate on the left and right sides of the gate electrode.

Preferably, after forming the low concentration ion implantation region, performing a heat treatment process on the substrate, forming spacers on the left and right sidewalls of the gate electrode, and forming secondary diffusion preventing ions on the entire surface of the substrate. And implanting impurity ions of the second conductivity type on the substrate to form a high concentration ion implantation region in the substrate.

Preferably, the impurity ions of the first conductivity type may be n-type impurity ions, and the impurity ions of the second conductivity type may be p-type impurity ions.

Preferably, the diffusion preventing ions are implanted into the semiconductor substrate and located at interstitial sites between the atomic lattice of the substrate.

Preferably, the diffusion preventing ion is larger than the atomic size of the semiconductor substrate and corresponds to the size of the impurity ion of the second conductivity type.

Preferably, the diffusion preventing ions may be carbon ions.

Preferably, the second conductivity type impurity ions may be boron (B) ions.

Preferably, the diffusion preventing ions are implanted on the entire surface of the substrate at a concentration of 1E13 to 1E15 ions / cm ² at an energy of 30 to 50 KeV.

Preferably, the secondary diffusion preventing ions may be implanted on the entire surface of the substrate at a concentration of 4E14 to 5E15 ions / cm ² at an energy of 5 to 10 KeV.

Preferably, the impurity ions of the second conductivity type may be implanted on the entire surface of the substrate at a concentration of 1E14 to 1E15 ions / cm ² at an energy of 10 to 30 KeV.

Preferably, the impurity ions of the second conductivity type may be implanted on the entire surface of the substrate at a concentration of 1E15 to 5E15 ions / cm ² at an energy of 3 to 10 KeV.

Preferably, the heat treatment process of the substrate is performed by applying a temperature of 900 ~ 1050 ℃ and a process time of 10 to 20 seconds under an inert gas atmosphere.

Preferably, the forming of the halo region may include implanting the first conductivity type impurity ions at an angle of 5 to 30 ° inclined downward with respect to the vertical axis of the semiconductor substrate.

According to a feature of the invention, ions in the LDD structure and source / drain are implanted by implanting diffusion preventing ions into the front surface of the substrate prior to implantation of the LDD structure and source / drain formation and placing them at interstitial sites in the silicon lattice of the substrate. They can be prevented from diffusing into the halo region and other regions, thereby ensuring the electrical properties of the semiconductor device.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 1A to 1H are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

First, as illustrated in FIG. 1A, in order to define an active region for a semiconductor substrate 101 made of a single crystal silicon or the like, an isolation process, for example, a shallow trench isolation (STI) process, is used. An element isolation film 102 is formed in the field region of 101. Here, the first conductive single crystal silicon substrate 101 may be used as the semiconductor substrate 101, and the first conductive type may be n type or p type. For convenience of description, the present invention will be described based on the case where the first conductivity type is n-type.

After the formation of the device isolation layer 102 is completed, the gate insulating layer 103 is grown on the active region of the semiconductor substrate 101 by a thermal oxidation process. Subsequently, for example, BF ₂ ions are implanted near the surface of the semiconductor substrate 101 in order to adjust the threshold voltage of the channel region to a desired value although not shown in the drawing.

Subsequently, a conductive layer for the gate electrode 104 is laminated on the gate insulating layer 103. The conductive layer may be composed of only a high concentration of a polysilicon layer or together with a silicide layer thereon.

Referring to FIG. 1B, once the conductive layers for the gate electrode 104 are stacked, a gate electrode 104 is formed on the conductive layer in a region where the gate electrode 104 is to be formed using a conventional photolithography process. A pattern of an etching mask photosensitive film (not shown) corresponding to the pattern of is formed. Subsequently, when the conductive layer and the gate insulating layer 103 under the pattern of the photoresist layer are left and the conductive layer and the gate insulating layer 103 in the remaining areas are exposed. Etch until Accordingly, the pattern of the gate electrode 104 and the gate insulating film 103 is formed on a portion of the active region.

In this state, a halo ion implantation step is performed as shown in FIG. 1C. Halo ions, that is, n-type impurities of the first conductivity type, for example, phosphorus (P) ions are implanted into the entire surface of the substrate 101 at an energy of 30 to 50 KeV and a concentration of 1E13 to 1E15 ions / cm ² . ). In this case, the implantation of the halo ions is performed at a predetermined inclined angle, for example, a tilt angle of 5 to 30 ° inclined downward with respect to the vertical axis of the surface of the semiconductor substrate 101.

After the halo ion implantation process is completed, a diffusion preventing ion implantation process is performed as shown in FIG. 1D. That is, diffusion preventing ions, for example, carbon (C) ions are applied to the entire surface of the substrate 101 with energy of 10 to 50 KeV and 1E13 to 1E15 ions / cm ^2. The diffusion prevention ion implantation region 106 is formed by implanting at a concentration of. The diffusion preventing ion implantation region 106 corresponds to the active region of the semiconductor substrate, that is, the diffusion prevention ions implanted in the corresponding region corresponding to the LDD region and the source / drain region.

The implanted diffusion preventing ions, for example, carbon (C) ions, are located and fixed at an interstitial site in the silicon lattice on the surface of the semiconductor substrate 101. As the diffusion preventing ions are fixed to the invasive sites in the silicon lattice, diffusion of LDD structure forming ions subsequently implanted, that is, p-type impurity ions of the second conductivity type, for example, boron (B) ions is prevented from being diffused. Can be obtained. The invasive site in the silicon lattice is a space between silicon atoms that is smaller in size than silicon atoms, and when atoms smaller than silicon atoms are injected into the silicon lattice, the invasive sites diffuse along the invasive site. Therefore, diffusion prevention ions having a size similar to that of the boron atoms, for example, carbon ions are previously implanted into the silicon lattice to inject boron ions in a fixed state at the invasive site in the silicon lattice to secure a path through which the boron ions are diffused. In other words, securing of the invasive site is limited, thereby preventing the boron ions in the halo region from diffusing into the channel region or the source / drain region.

As diffusion preventing ions are implanted prior to ion implantation for LDD structure formation, the mobility of the ions for forming the LDD structure may be restricted to realize fine profiles of the LDD structure, the source / drain region, and the halo region.

In the state where the halo ion implantation process and the diffusion preventing ion implantation process are completed, as shown in FIG. 1E, p-type impurity ions of the second conductivity type are ion-implanted at a low concentration (n−) on the entire surface of the substrate 101. The low concentration ion implantation region 107 is formed in the bulk of the semiconductor substrate 101 in the left and right regions of the gate electrode 104. The low concentration ion implantation region 107 is activated by a subsequent heat treatment process of the substrate 101 to be converted into an LDD (Lightly Doped Drain) region. Here, boron (B) ions may be used as the impurity ions of the second conductivity type, and when the boron ions are used, the boron ions may be implanted into the substrate at an energy of 10 to 30 KeV and a concentration of 1E14 to 1E15 ions / cm ² .

Subsequently, a heat treatment process is performed on the substrate. The heat treatment process is intended to form an LDD structure by activating the diffusion preventing ion implantation region and the halo region and activating the low concentration ion implantation region. The process proceeds at a temperature of 1050 ° C. and a process time of 10 to 20 seconds.

In this state, as shown in FIG. 1F, an insulating film for the spacer 110 of FIG. 1G is laminated on the semiconductor substrate. That is, an insulating film, for example, an oxide film 108 is laminated on the surface of the semiconductor substrate including the gate electrode, and then a nitride film 109 is laminated on the oxide film 108. Next, as illustrated in FIG. 1G, the nitride film on the gate electrode is etched using a dry etching process having anisotropic etching characteristics, for example, a reactive ion etching (RIE) process. At this time, the gate electrodes and the oxide layer on the active region are also etched. Thus, spacers 110 are formed on sidewalls of the gate electrodes.

When the spacer is completed on the sidewall of the gate electrode, as shown in FIG. 1H, a diffusion preventing ion implantation process as in FIG. 1D is performed again. The diffusion preventing ion implantation process at this stage is to prevent diffusion of the source / drain formation ions implanted by the subsequent process into the channel region and the like as in FIG. 1D. Specifically, the diffusion preventing ions, for example, carbon (C) ions to the entire surface of the substrate 101 energy of 5-10 KeV and 5E14-5E15 ions / cm ² Inject at the concentration of.

When the secondary diffusion preventing ion implantation process is completed, as shown in FIG. 1H, a source / drain formation ion, that is, a second conductivity type p-type impurity ion implantation process is performed.

At this time, the p-type impurity ions are implanted at a high concentration. Preferably, the p-type impurity ions of the second conductivity type are implanted at a high concentration (n +) on the entire surface of the substrate 101 so that the p-type impurity ions are implanted at a high concentration (n +). A high concentration ion implantation region 111 is formed in the bulk of the semiconductor substrate 101. The high concentration ion implantation region 111 is activated by a subsequent heat treatment process of the substrate 101 and is converted into a source / drain region. Here, boron (B) ions may be used as the impurity ions of the second conductivity type, and when the boron ions are used, the boron ions may be implanted into the substrate at an energy of 3 to 10 KeV and a concentration of 1E15 to 5E15 ions / cm ² .

Through the above manufacturing process, the semiconductor device manufacturing method of the present invention is completed. Subsequently, although not shown in the drawings, a transistor may be completed by applying a subsequent semiconductor device unit process such as silicide formation.

Therefore, it is obvious to those skilled in the art that various modifications can be made without departing from the technical spirit of the present invention.

The semiconductor device manufacturing method according to the present invention has the following effects.

By implanting anti-diffusion ions into the front surface of the substrate prior to implantation of the LDD structure and source / drain formation, the ions in the LDD structure and source / drain are transferred to the halo region and other regions by placing them at interstitial sites in the silicon lattice of the substrate. It is possible to prevent the diffusion, thereby ensuring the electrical properties of the semiconductor device.

Claims (13)

Forming a gate insulating film and a gate electrode on the semiconductor substrate; Implanting impurity ions of a first conductivity type on the entire surface of the substrate to form a halo region in a semiconductor substrate at a portion corresponding to the diffusion preventing ion region; Implanting diffusion preventing ions onto the entire surface of the substrate to form diffusion prevention ion regions; Implanting impurity ions of a second conductivity type on the substrate to form a low concentration ion implantation region in the semiconductor substrates to the left and right of the gate electrode; Performing a heat treatment process on the substrate; Forming spacers on left and right sidewalls of the gate electrode; Implanting ions for preventing secondary diffusion into the entire surface of the substrate; and Implanting impurity ions of a second conductivity type on the substrate to form a high concentration ion implantation region in the substrate; A semiconductor device manufacturing method comprising a. delete The method of claim 1, wherein the impurity ions of the first conductivity type are n-type impurity ions, and the impurity ions of the second conductivity type are p-type impurity ions. The method of claim 1, wherein the diffusion preventing ions are implanted into the semiconductor substrate and located at interstitial sites between the atomic lattice of the substrate. The method of claim 1, wherein the diffusion preventing ions are larger than an atomic size of the semiconductor substrate and correspond to a size of the impurity ions of the second conductivity type. The method of claim 1, wherein the diffusion preventing ions are carbon ions. The method of claim 1, wherein the second conductivity type impurity ions are boron (B) ions. The method of claim 1, wherein the diffusion preventing ions are implanted onto the entire surface of the substrate at a concentration of 1E13 to 1E15 ions / cm ² at an energy of 30 to 50 KeV. The method of claim 1, wherein the secondary diffusion preventing ions are implanted on the entire surface of the substrate at a concentration of 4E14 to 5E15 ions / cm ² at an energy of 5 to 10 KeV. The method of claim 1, wherein the impurity ions of the second conductivity type are implanted on the entire surface of the substrate at a concentration of 1E14 to 1E15 ions / cm ² at an energy of 10 to 30 KeV. The method of claim 1, wherein the impurity ions of the second conductivity type are implanted on the entire surface of the substrate at a concentration of 1E15 to 5E15 ions / cm ² at an energy of 3 to 10 KeV. The method of claim 1, wherein the heat treatment of the substrate is performed by applying a temperature of 900 to 1050 ° C. and a process time of 10 to 20 seconds under an inert gas atmosphere. The method of claim 1, wherein the forming of the halo region comprises: And injecting the first conductivity type impurity ions at an angle of 5 to 30 degrees inclined downward with respect to the vertical axis of the semiconductor substrate.

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