KR100561977B1 - Method For Manufacturing Semiconductor Devices - Google Patents

Abstract

The present invention forms a gate electrode on an active region of a semiconductor substrate, implants carbon (C +) ions into the active region, and implants (P) ions such as BF + ions into the active region, followed by heat treatment. The P-type LDD region is diffused by the process. Thereafter, spacers are formed on both sidewalls of the gate electrode, and a P-type source / drain region is diffused in the active region by a heat treatment process.

Therefore, when the boron (B +) ions in the LDD region are diffused by a heat treatment process, the present invention can suppress diffusion of the boron (B +) ions into an unwanted region such as a channel region. This improves electrical characteristics such as stabilizing threshold voltage and reducing leakage current while forming a shallow junction of a P-type MOS transistor having a short channel.

Transistor, P-type LED Area, Threshold Voltage

Description

Semiconductor device manufacturing method {Method For Manufacturing Semiconductor Devices}             

1 is a cross-sectional structural view showing a semiconductor device according to the prior art.

2A to 2E are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to suppress the diffusion of boron ions in a lightly doped drain (LDD) region into a channel region, thereby preventing the electrical of a PMOS transistor. The present invention relates to a semiconductor device manufacturing method which prevents the deterioration of characteristics.

In general, as the integration of semiconductor devices proceeds, the size of the semiconductor device is reduced, and the channel length of the semiconductor device, for example, the MOS transistor, is also reduced. However, when the channel length of the MOS transistor is reduced, undesirable electrical characteristics of the MOS transistor, for example, a short channel effect (SCE), may occur.

In order to solve the short channel effect, if the horizontal reduction such as the reduction of the gate electrode length of the MOS transistor and the vertical reduction such as the reduction of the gate insulating film thickness and the source / drain junction depth of the MOS transistor are not performed together, Can not be done. In addition, the horizontal reduction and vertical reduction reduce the voltage of the driving power source, increase the doping concentration of the semiconductor substrate, and in particular, the doping profile of the channel region should be efficiently controlled.

However, since the size of the semiconductor device is rapidly being reduced, but the driving voltage required by the electronic products to which the semiconductor device is applied is still high, for example, in the case of a semiconductor device such as a general NMOS transistor, The electrons are severely accelerated to the drain due to the large potential gradient of the drain, and thus have a fragile structure in which hot carriers tend to occur near the drain. In order to improve the structure of a general MOS transistor vulnerable to such a hot carrier, a transistor having a lightly doped drain (LDD) structure has been introduced.

In this LDD NMOS transistor, the low concentration (n-) LDD region located between the channel and the source / drain mitigates the high drain-gate voltage near the drain junction, thereby reducing severe potential fluctuations and further reducing the occurrence of hot carriers. Can be suppressed. Various techniques for manufacturing the transistor of the LDD structure have been proposed. Among these techniques, a method of forming spacers of an insulating film on both sidewalls of the gate electrode is the most typical method of manufacturing the transistor of the LDD structure. It is used as most mass production technology.

In recent years, as the high integration of semiconductor devices proceeds, a shallow junction technology that forms a very shallow junction depth is essentially introduced to effectively suppress the short channel effect (SCE). That is, by the boron (B +) ion or BF ₂ + ion in the ion implantation step of the ion implantation with a low energy ion implantation has been to form the shallows junction. Nevertheless, as ultra-high integration of semiconductor devices proceeds, it becomes increasingly difficult to obtain a desired profile for the junction of the LDD region. Therefore, a halo structure that suppresses the depletion regions of the source / drain in proximity to each other in the horizontal direction without affecting the doping concentration of the channel region that determines the threshold voltage (V _T ) of the MOS transistor. Introduced additional.

The halo structure may be formed by implanting impurities of a type opposite to that of the source / drain, that is, halo ions, in a region near the junction of the source / drain adjacent to the gate electrode of the MOS transistor. This is to reduce the depletion region of the source / drain region by forming a diffusion region having an impurity concentration higher than the well doping concentration near the source / drain junction of the MOS transistor.

In the conventional PMOS transistor having such a halo structure, as shown in FIG. 1, an active region of the semiconductor substrate 10 is defined by the device isolation layer 11 of the semiconductor substrate 10, and the active A gate electrode 20 is formed on the region, a P-type LDD region 30 is formed in the active region with the gate electrode 20 in the center, and the gate electrode adjacent to the junction of the LDD region 30. A hollow region (H) 40 is formed in the semiconductor substrate 10 under the 20, spacers 50 of an insulating film are formed on both sidewalls of the gate electrode 20, and the gate electrode 20 A P + type source / drain region 60 is formed in the semiconductor substrate 10 with the spacer 50 in the center. A gate insulating film 21 exists between the semiconductor substrate 10 and the gate electrode 20.

However, in the conventional PMOS transistor, since the ion implantation process of the BF ₂ + ions is performed to form the LDD region 30, damage caused by ion implantation occurs in the LDD region 30. That is, defects such as interstitial sites occur in the silicon lattice of the LDD region 30. In this state, when the LDD region 30 is formed using a heat treatment process, boron (B +) ions cause a diffusion enhanced diffusion into an unwanted region, for example, a channel region. This is because the BF ₂ + ion has a lot of F + ions to promote the diffusion of the boron ions. As a result, the electrical characteristics of the transistor are degraded by changing the threshold voltage V _T of the transistor differently from the initially determined value. That is, since the division of turn-on and turn-off operations of the transistor becomes unclear, malfunction or malfunction of the transistor occurs, and an increase in leakage current occurs.

Therefore, an object of the present invention is to suppress the diffusion of boron ions into the channel region when diffusing the LDD region of the P-type MOS transistor.

Another object of the present invention is to improve electrical characteristics by stabilizing threshold voltages.

It is another object of the present invention to improve electrical characteristics by suppressing an increase in leakage current.

The semiconductor device manufacturing method according to the present invention for achieving the above object is

Forming a gate electrode on an active region of the semiconductor substrate; Implanting ions of the formed LED region containing boron into the active region at low concentration; And forming the shaped LED region by diffusing the LED region forming ions by a heat treatment process, wherein the boron ions are prevented from diffusing into the channel region during the heat treatment process. In order to proceed to the heat treatment step before the process characterized in that it comprises the step of implanting a predetermined ion in the active region.

Preferably, the ion implantation of the predetermined ions may be performed before the ion implantation of the LED region forming ions or after the ion implantation of the LED region forming ions.

Preferably, carbon ions can be ion implanted as the predetermined ions. In addition, it is preferable to ion implant the carbon ions at an ion implantation energy of 3 to 20 KeV and an ion implantation concentration of 1.0E14 ions / cm ² to 1.0E15 ions / cm ² .

Preferably, BF + ions can be ion implanted as the LED region forming ions. In addition, the BF + ions are preferably ion implanted at an ion implantation energy of 2 to 10 KeV and an ion implantation concentration of 5.0E14 ions / cm ² to 5.0E15 ions / cm ² .

Preferably, the BF + ions may be diffused by a rapid heat treatment process. In addition, the BF + ions are preferably diffused for 10 to 20 seconds in a temperature of 900 ~ 1050 ℃ and nitrogen (N ₂ ) gas.

Therefore, in the present invention, since carbon ions are implanted into the active region for the shaped LED region, BF + ions are implanted, thereby preventing boron ions from diffusing unwanted channel regions during the heat treatment process. You can prevent it. As a result, the electrical characteristics can be improved by stabilizing the threshold voltage of the type morph transistor and reducing the leakage current.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are given to parts of the same construction and the same operation as the conventional parts.

2A to 2E are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, first, an isolation process, for example, a shallow trench isolation (STI) process or the like, is used to electrically isolate an active region of a semiconductor substrate 10, for example, a single crystal silicon substrate. An element isolation film 11 of an insulating film such as an oxide film is formed in the field region of the substrate 10. Here, a single conductive silicon substrate may be used as the single crystal silicon substrate of the semiconductor substrate 10, and the first conductive type may be n type or p type. For convenience of description, the present invention will be described based on the case where the first conductivity type is n type.

Although not shown in the drawings, after the formation of the device isolation layer 11, ion implantation for adjusting the threshold voltage V _T , ion implantation for preventing punch through, and channel stopper are formed. For ion implantation, ion implantation for well formation may be further proceeded, and description thereof will be omitted for simplicity of explanation.

After the formation of the device isolation layer 11 is completed, the gate insulating film 21 of the gate electrode 20, for example, the gate oxide film, by a thermal oxidation process on the active region of the semiconductor substrate 10. Growing to a thickness of 100 ~ 150Å. Subsequently, a conductive layer for the gate electrode 20, for example, a high concentration polycrystalline silicon layer, may be formed on the gate insulating layer 21 by a chemical vapor deposition process, for example, a low pressure chemical vapor deposition process. To be deposited.

Here, the conductive layer for the gate electrode 20 may be formed of a plurality of layers of the silicide layer on the polycrystalline silicon layer by the subsequent process and the polycrystalline silicon layer instead of a single layer of a high concentration polycrystalline silicon layer. Do.

After the polycrystalline silicon layer for the gate electrode 20 is stacked, an etching mask corresponding to the pattern of the gate electrode 20 is formed on the gate electrode forming region of the polycrystalline silicon layer by using a conventional photolithography process. ), For example, to form a pattern of the photosensitive film. Thereafter, the polycrystalline silicon layer and the gate insulating layer 21 under the pattern of the photoresist layer are left and the polycrystalline silicon layer and the gate insulating layer in the remaining regions are completely etched. Accordingly, patterns of the gate electrode 20 and the gate insulating film 21 are formed on the gate electrode forming region and the surfaces of the remaining active regions are exposed. Thereafter, the pattern of the photosensitive film is removed.

Referring to FIG. 2B, after the pattern of the gate electrode 20 is formed, ions for suppressing diffusion of boron (B +) ions in the LED region 70 of FIG. 2D into an unwanted region, for example, Carbon (C +) ions are implanted into the exposed active region. Preferably, the ion implantation energy of the carbon ions is 3-20 KeV, and the ion implantation concentration is 1.0E14 ions / cm ² to 1.0E15 ions / cm ² .

Here, the carbon ions are pre-modified the single crystalline silicon layer of the exposed active region into a preamorphized silicon layer to inject BF + ions in the subsequent ion implantation process of FIG. 2C to form an LDD region. When the channeling (channeling) phenomenon can be suppressed.

In addition, the carbon ions are located at interstitial sites in the silicon lattice of the active region when the boron (B +) ions are diffused in the subsequent heat treatment process of FIG. It makes it difficult to secure a diffusion path like a brother site. As a result, it is possible to suppress the diffusion of boron ions into an unwanted region such as a channel region under the gate electrode 20 along a diffusion path such as the invasive site.

Referring to FIG. 2C, after the carbon ions are ion implanted, P-type LED region forming ions containing boron in the exposed active region using the pattern of the gate electrode 20 as an ion implantation mask, For example, BF + ions are implanted at low concentrations. Preferably, the ion implantation energy of the BF + ion is 2 ~ 10 KeV, the ion implantation concentration is 5.0E14 ions / cm ² ~ 5.0E15 ions / cm ² .

Here, the BF + ions can suppress the diffusion promotion of the boron (B +) ions when the boron (B +) ions are diffused in a subsequent heat treatment process of FIG. 2D for forming an LDD region. This is the BF + ions because the boron (B +) of the fluoride that promotes diffusion of the ion (F +) ion prior BF ₂ + to contain less than the ion.

On the other hand, the present invention has been described on the basis of proceeding the ion implantation of carbon (C +) ions first followed by the ion implantation of BF + ions, the ion implantation of carbon (C +) ions after the implantation of BF + ions You may proceed.

Referring to FIG. 2D, after the ion implantation of the BF + ions is completed, the P-type LDD region may be diffused by diffusing boron (B +) ions using a heat treatment process, for example, a rapid thermal process (RTP) process. 70). Preferably, the rapid heat treatment process is performed for 10 to 20 seconds at a temperature of 900 ~ 1050 ℃ and an atmosphere of an inert gas, for example nitrogen (N ₂ ) gas.

At this time, in the ion implantation process of FIG. 2B, carbon ions previously implanted are positioned at the invasive sites in the silicon lattice of the LDD region 70 to secure the diffusion path of the boron (B +) ions such as the invasive sites. Becomes difficult. Further, the diffusion of the boron ion (B +) can be suppressed in the BF + ions are boron (B +) to promote the diffusion of fluorine ion (F +) ions, so the containing less than a conventional BF ₂ + ions that.

Therefore, the present invention can suppress the diffusion of boron (B +) ions in the LDD region into the channel region under the gate electrode 20, so that the threshold of the MOS transistor having a short channel while forming a shallow junction of the LDD region Electrical characteristics such as stabilizing voltage and reducing leakage current can be improved.

Referring to FIG. 2E, after the LDD region 70 is formed, an insulating film for the spacer 50, for example, a nitride film, is deposited on all regions including the gate electrode 20 by a chemical vapor deposition process or the like. . Thereafter, the nitride layer is etched by a dry etching process having anisotropic etching characteristics to expose the surface of the active region of the semiconductor substrate 10 for the P + type source / drain region 80. Accordingly, spacers 50 are formed on both sidewalls of the gate electrode 20.

Subsequently, P-type impurities, such as boron (B +) ions, for the source / drain region 80 are applied to the exposed active region using the gate electrode 20 and the spacer 50 as an ion implantation mask. Ion implantation at high concentration.

A junction of the source / drain regions 80 is then formed using a heat treatment process. Therefore, the semiconductor device manufacturing method of this invention is completed by advancing such a series of manufacturing processes.

Subsequently, although not shown in the figure, the structure of the transistor may be completed by performing a subsequent process such as a silicide process, a contact process, a metal wiring process, etc. to form a silicide layer on the source / drain region and the gate electrode. Detailed description thereof will be omitted for convenience of description because it is less relevant to the gist of the present invention.

As described in detail above, in the method of fabricating a semiconductor device according to the present invention, a gate electrode is formed on an active region of a semiconductor substrate, and carbon (C +) ions are implanted into the active region, and BF + ions are formed in the active region. The same P-type ion is implanted and the P-type LDD region is diffused by the heat treatment process. Thereafter, spacers are formed on both sidewalls of the gate electrode, and the source / drain regions are diffused in the active region with the gate electrode and the spacer in the center.

Therefore, when the boron (B +) ions in the LDD region are diffused by the heat treatment process, the present invention can suppress diffusion of the boron (B +) ions into the channel region. This improves electrical characteristics such as stabilizing threshold voltage and reducing leakage current while forming a shallow junction of a P-type MOS transistor having a short channel.

Meanwhile, the present invention is not limited to the contents described in the drawings and the detailed description, and various modifications may be made without departing from the spirit of the present invention, which is obvious to those skilled in the art. to be.

Claims (10)

Forming a gate electrode on an active region of the semiconductor substrate; Implanting BF + ions, which are formed Eldi region-forming ions containing boron in the active region, at an ion implantation energy of ² to 10 KeV and an ion implantation concentration of 5.0E14ions / cm ² to 5.0E15ions / cm ² ; And In the semiconductor device manufacturing method comprising the step of diffusing the BF + ions by a heat treatment process to form a target LED region, Implanting predetermined ions into the active region prior to the heat treatment process to suppress diffusion of boron ions of the LED region forming ions into the channel region during the heat treatment process; And Forming spacers on both sidewalls of the gate electrode after the LED region is formed A semiconductor device manufacturing method comprising a. The method of claim 1, wherein the ion implantation of the predetermined ions is performed before the ion implantation of the LED region forming ion. The method of claim 1, wherein the implanting of the predetermined ions is performed after the implantation of the LED forming ion. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein carbon ions are implanted as the predetermined ions. The method of claim 4, wherein the carbon ions are ion implanted at an ion implantation energy of 3 to 20 KeV and an ion implantation concentration of 1.0E14 ions / cm ² to 1.0E15 ions / cm ² . delete delete The method of claim 1, wherein the BF + ions are diffused by a rapid heat treatment process. The method of claim 8, wherein the BF + ions are diffused at a temperature of 900 ° C. to 1050 ° C. 10. The method of claim 9, wherein the BF + ions are diffused in a temperature of 900 to 1050 ° C. and nitrogen gas for 10 to 20 seconds.

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