CN105070663B - A kind of silicon carbide MOSFET raceway groove self-registered technology implementation method - Google Patents
A kind of silicon carbide MOSFET raceway groove self-registered technology implementation method Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 150000002500 ions Chemical class 0.000 claims abstract description 23
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 22
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 22
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 22
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 22
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 238000000407 epitaxy Methods 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims abstract description 4
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 claims 3
- 239000013078 crystal Substances 0.000 claims 1
- -1 Nitrogen ion Chemical class 0.000 abstract 1
- 229910052757 nitrogen Inorganic materials 0.000 abstract 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 208000021760 high fever Diseases 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a kind of silicon carbide MOSFET raceway groove self-registered technology implementation methods, including：Cleaning sic epitaxial wafer；First layer dielectric layer is deposited in the silicon carbide epitaxy on piece；Second layer dielectric layer is deposited on the first layer dielectric layer；Photoresist is coated on the second layer dielectric layer, and photoetching development goes out preliminary p-type base area window；Photoresist mask etching SiO2Medium；With remaining photoresist and SiO2Mask etching polysilicon is combined, remaining photoresist is removed after the completion of etching；Using polysilicon as ion implanting barrier layer, Al ion implantation forms p-type base area；It is deposited on the polysilicon and etches SiO2, form side wall mask；Using polysilicon and side wall as ion implanting barrier layer, N~+ implantation forms N+Source region；Remove SiO2And polysilicon, and form P+Ion implanting barrier layer；Al ion implantation forms P+Contact zone.The present invention is by deposit polycrystalline silicon and forms side wall and is used as P+Contact area barrier layer avoids the region from injecting Nitrogen ion, does not need stripping technology.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of silicon carbide MOSFET raceway groove self-registered technology are real
Existing method.
Background technology
Carbofrax material has excellent physically and electrically characteristic, with its big energy gap, high critical breakdown electric field, high fever
The particular advantages such as conductance and high saturation drift velocity become and make high pressure, the reason of high power, high temperature resistant, high frequency, Flouride-resistani acid phesphatase device
Think semi-conducting material, has broad application prospects at military and civil aspect.The power electronics device prepared with carbofrax material
Part has become one of hot spot device and research frontier of current semiconductor applications.
Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, metal oxygen
Compound semiconductor field effect transistor) there are the advantages such as conducting resistance is low, switching speed is fast, temperature reliability is high, it is expected to become
Next-generation high-voltage circuit breaker device.In silicon carbide MOSFET, device of the same area, cellular quantity is more, effective area
Bigger, then the current density of device will be bigger, therefore reduces single cell density in silicon carbide MSOFET devices, increases cellular
Quantity is current one of the main method for improving device current density.
The effective ways for reducing single cell density in silicon carbide MOSFET device are to reduce channel length.In order to reduce light
Environment and artificial influence during quarter, a length of 0.5 μm of raceway groove below are all made of raceway groove self-registered technology.Existing raceway groove
Self-registered technology is being N+Before source region ion implanting, using stripping technology in P+Contact area forms metal mask, as P+Region
Ion implanting barrier layer, to stop N+Injection, this method introduces stripping technology, incompatible with silicon technology；High temperature ion simultaneously
Metal barrier is used in injection process, can generate pollution to device surface and ion implantation apparatus, is existing as shown in Figure 1 to Figure 3
There is technology silicon carbide MOSFET device raceway groove self-registered technology flow chart.
Invention content
The present invention provides a kind of silicon carbide MOSFET raceway groove self-registered technology implementation method, can avoid using stripping technology
And metal is as ion implanting barrier layer, while can reduce by a photoetching compared with traditional handicraft, improve P+Contact zone side
The accuracy on boundary.
In order to achieve the above object, the present invention uses following technical proposals：
A kind of silicon carbide MOSFET raceway groove self-registered technology implementation method, including：
Cleaning sic epitaxial wafer；
First layer dielectric layer is deposited in the silicon carbide epitaxy on piece；
Second layer dielectric layer is deposited on the first layer dielectric layer；
Photoresist is coated on the second layer dielectric layer, and photoetching development goes out preliminary p-type base area window；
Photoresist mask etching SiO2Medium；
With remaining photoresist and SiO2Mask etching polysilicon is combined, remaining photoresist is removed after the completion of etching；
Using polysilicon as ion implanting barrier layer, Al ion implantation forms p-type base area；
It is deposited on the polysilicon and etches SiO2, form side wall mask；
Using polysilicon and side wall as ion implanting barrier layer, N~+ implantation forms N+Source region；
Remove SiO2And polysilicon, and form P+Ion implanting barrier layer；
Al ion implantation forms P+Contact zone.
Optionally, in the cleaning sic epitaxial wafer the step of, using standard RCA technique cleaning sic extensions
N is used in combination in piece2Drying.
Optionally, the first layer dielectric layer is polysilicon or non-crystalline silicon.
Optionally, the second layer dielectric layer is SiO2Or SiN.
Optionally, etches polycrystalline silicon is hard mask etching, to improve polysilicon sidewall steepness, while with remaining photoresist
Etching improves etching selection ratio.
Optionally, when p-type base area is injected, P+Overlying regions deposit polycrystalline silicon barrier layer.
Optionally, it deposits and etches SiO2, the SiO of channel width is formed in polysilicon both sides2Side wall.
Optionally, P is being formed+When the ion implanting barrier layer of region, considers lateral wall width, make N+Source region and P+Contact area
It is connected.
Optionally, each ion implanting is multiple combination injection, forms uniform Impurity Distribution.
Optionally, the p-type base area, P+Contact zone and N+Source region is carbofrax material.
Silicon carbide MOSFET raceway groove self-registered technology implementation method provided in an embodiment of the present invention, simultaneously by deposit polycrystalline silicon
Side wall is formed as P+Contact area barrier layer avoids region N+Injection, does not need stripping technology, simultaneous with existing silicon technology
Hold, while avoiding pollution of the metal barrier to epitaxial wafer surface and ion implantation apparatus；P+Region forms ion implanting blocking
When layer window, considers polysilicon side wall width, make P+Contact area and N+Source region connects, and realizes raceway groove self-registered technology.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 to Fig. 3 is silicon carbide MOSFET device raceway groove self-registered technology flow chart in the prior art；
Fig. 4 is silicon carbide MOSFET raceway groove self-registered technology implementation method flow chart provided in an embodiment of the present invention；
Fig. 5 to Figure 17 is to be carried out in silicon carbide MOSFET raceway groove self-registered technology implementation method provided in an embodiment of the present invention
The structural schematic diagram obtained after each processing step.
Specific implementation mode
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts all other
Embodiment shall fall within the protection scope of the present invention.
As shown in figure 4, the embodiment of the present invention provides a kind of silicon carbide MOSFET raceway groove self-registered technology implementation method, including
Following steps：
Step S101, cleaning sic epitaxial wafer obtains structure as shown in Figure 5；
Step S102,2 μm of Poly Si are deposited and are etched in the silicon carbide epitaxy on piece and form ion implanting barrier layer,
Obtain structure as shown in FIG. 6；
Step S103, Al ion implantation forms the regions P base, obtains structure as shown in Figure 7；
Step S104, deposition 800nm SiO2, obtain structure as shown in Figure 8；
Step S105, etching 800nm SiO2, form side wall and carry out N~+ implantation formation N+Source region is obtained such as Fig. 9 institutes
The structure shown；
Step S106, removal Poly Si and SiO2, deposition 2.5 μm of SiO2And even photoresist, it obtains as shown in Figure 10
Structure；
Step S107, photoetching development goes out preliminary P+Window is injected, photoresist mask etching SiO is carried out at the same time2, obtain such as figure
Structure shown in 11；
Step S108, it removes photoresist and Al ion implantation forms P+Contact, obtains structure as shown in figure 12；
Step S109, SiO is removed2After mask, ion implanting activation annealing and grid oxygen oxidation are carried out, is obtained as shown in figure 13
Structure；
Step S110, polysilicon deposition and graphical, obtains structure as shown in figure 14；
Step S111, inter-level dielectric deposition and etching trepanning, obtain structure as shown in figure 15；
Step S112, alloy self-registered technology forms source and drain ohmic alloy, obtains structure as shown in figure 16；
Step S113, positive back metal thickeies, and obtains structure as shown in figure 17.
So far, a complete silicon carbide MOSFET manufacture is completed.
Optionally, in the cleaning sic epitaxial wafer the step of, using standard RCA technique cleaning sic extensions
N is used in combination in piece2Drying.
Optionally, the first layer dielectric layer is polysilicon or non-crystalline silicon.
Optionally, the second layer dielectric layer is SiO2Or SiN.
Optionally, etches polycrystalline silicon is hard mask etching, to improve polysilicon sidewall steepness, while with remaining photoresist
Etching improves etching selection ratio.
Optionally, when p-type base area is injected, P+Overlying regions deposit polycrystalline silicon barrier layer.
Optionally, it deposits and etches SiO2, the SiO of channel width is formed in polysilicon both sides2Side wall.
Optionally, P is being formed+When the ion implanting barrier layer of region, considers lateral wall width, make N+Source region and P+Contact area
It is connected.
Optionally, each ion implanting is multiple combination injection, forms uniform Impurity Distribution.
Optionally, the p-type base area, P+Contact zone and N+Source region is carbofrax material.
Silicon carbide MOSFET raceway groove self-registered technology implementation method provided in an embodiment of the present invention, simultaneously by deposit polycrystalline silicon
Side wall is formed as P+Contact area barrier layer avoids region N+Injection, does not need stripping technology, simultaneous with existing silicon technology
Hold, while avoiding pollution of the metal barrier to epitaxial wafer surface and ion implantation apparatus；P+Region forms ion implanting blocking
When layer window, considers polysilicon side wall width, make P+Contact area and N+Source region connects, and realizes raceway groove self-registered technology.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, all answer by the change or replacement that can be readily occurred in
It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. a kind of silicon carbide MOSFET raceway groove self-registered technology implementation method, which is characterized in that including：
Cleaning sic epitaxial wafer；
First layer dielectric layer is deposited in the silicon carbide epitaxy on piece；
Second layer dielectric layer is deposited on the first layer dielectric layer；
Photoresist is coated on the second layer dielectric layer, and photoetching development goes out two preliminary p-type base area windows；
Photoresist mask etching SiO2Medium；
With remaining photoresist and SiO2Mask etching polysilicon is combined, remaining photoresist is removed after the completion of etching；
Using polysilicon as ion implanting barrier layer, Al ion implantation forms two p-type base areas；
It is deposited on the polysilicon and etches SiO2, form side wall mask and reserve the contact zones P+；
Using polysilicon and side wall as ion implanting barrier layer, N~+ implantation forms two N+Source region；
Remove SiO2And polysilicon, and P is formed according to the contact zones P+ that the side wall mask is reserved between two N+ source regions+
Ion implanting barrier layer；
Al ion implantation forms P+Contact zone.
2. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that described
In the step of cleaning sic epitaxial wafer, using standard RCA technique cleaning sic epitaxial wafers, N is used in combination2Drying.
3. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that described
One layer of dielectric layer is polysilicon or non-crystalline silicon.
4. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that described
Two layer medium layer is SiO2Or SiN.
5. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that etching is more
Crystal silicon is hard mask etching, to improve polysilicon sidewall steepness, while being etched with remaining photoresist, improves etching selection ratio.
6. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that p-type base
When area is injected, P+Overlying regions deposit polycrystalline silicon barrier layer.
7. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that deposition is simultaneously
Etch SiO2, the SiO of channel width is formed in polysilicon both sides2Side wall.
8. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that formed
P+When the ion implanting barrier layer of region, considers lateral wall width, make N+Source region and P+Contact area is connected.
9. silicon carbide MOSFET raceway groove self-registered technology implementation method according to claim 1, which is characterized in that each ion
Injection is multiple combination injection, forms uniform Impurity Distribution.
10. silicon carbide MOSFET raceway groove self-registered technology implementation method according to any one of claim 1 to 9, special
Sign is, the p-type base area, P+Contact zone and N+Source region is carbofrax material.
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| CN105810722B (en) * | 2016-03-16 | 2019-04-30 | 中国科学院半导体研究所 | A kind of silicon carbide MOSFET device and preparation method thereof |
| CN109545855B (en) * | 2018-11-19 | 2021-09-17 | 中国科学院微电子研究所 | Preparation method of active region of silicon carbide double-groove MOSFET device |
| CN111653484B (en) * | 2020-06-03 | 2023-12-15 | 深圳基本半导体有限公司 | Method for optimizing self-alignment process of silicon carbide MOSFET |
| CN112563140B (en) * | 2020-11-29 | 2022-08-16 | 中国电子科技集团公司第五十五研究所 | Self-aligned doping process for JFET (junction field effect transistor) area of silicon carbide MOSFET (metal-oxide-semiconductor field effect transistor) device |
| CN114361015A (en) * | 2022-03-17 | 2022-04-15 | 成都功成半导体有限公司 | Method for preparing silicon carbide power device based on shallow source region injection |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4466176A (en) * | 1982-08-09 | 1984-08-21 | General Electric Company | Process for manufacturing insulated-gate semiconductor devices with integral shorts |
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
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| CN102668049B (en) * | 2010-12-22 | 2015-11-25 | 住友电气工业株式会社 | Manufacture the method for sic semiconductor device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4466176A (en) * | 1982-08-09 | 1984-08-21 | General Electric Company | Process for manufacturing insulated-gate semiconductor devices with integral shorts |
| US4898835A (en) * | 1988-10-12 | 1990-02-06 | Sgs-Thomson Microelectronics, Inc. | Single mask totally self-aligned power MOSFET cell fabrication process |
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