CN101556967B - Power semiconductor and manufacturing method thereof - Google Patents
Power semiconductor and manufacturing method thereof Download PDFInfo
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- CN101556967B CN101556967B CN200810035949XA CN200810035949A CN101556967B CN 101556967 B CN101556967 B CN 101556967B CN 200810035949X A CN200810035949X A CN 200810035949XA CN 200810035949 A CN200810035949 A CN 200810035949A CN 101556967 B CN101556967 B CN 101556967B
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Abstract
The invention discloses a power semiconductor and a manufacturing method thereof. The power semiconductor comprises an N-shaped substrate, an N-shaped extension region disposed above the N-shaped substrate, a second metal layer disposed below the N-shaped substrate, a P well region disposed above the N-shaped extension region, a source region disposed on the P well region, a plurality of grids passing through the P well region and the source region and contacting with the N-shaped extension region, a first insulating layer, a first metal layer and a second insulating layer which are all arranged on the source region, and a plurality of contact holes passing through the first insulating layer which contacts with the P well region and the source region through the contact holes. The power semiconductor and the manufacturing method thereof enable the realization of high density to become possible, thereby lowering the on resistance which is an important parameter of a power device and reducing the photoetching registration tolerance formed by the distance between a groove grid and the source region.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of power semiconductor and manufacture method thereof.
Background technology
Recent two decades comes, and the fast development of power device and encapsulation technology thereof makes electric and electronic technical field that huge variation take place, and numerous Power Electronic Circuit can be realized by power (POWER) MOSFET.MOSFET promptly is metal-oxide semiconductor (MOS)-field-effect transistor, keeps apart in order to the gate oxide that is approached by one deck between the grid of control device electric current and the semiconductor, modulates size of current in the semiconductor channel by the control gate pole tension.Under static conditions, grid itself can not absorb any electric current.When grid voltage changes, then grid capacitance is discharged and recharged, thereby greatly simplified the design of the drive circuit of power device.Power MOSFET also has advantages such as input impedance height, power gain height, Heat stability is good, stable manufacturing process, thereby has obtained increasingly extensive application.
There is different requirements different application scenarios to power MOSFET, but the cell density that how to improve power MOSFET is the common objective that the designer pursues forever, and becomes the emphasis of industry research.The power device of traditional mos transistor structure is owing to be surface device, developed into the limit, can not further effectively increase cell density, and the transistor arrangement of trench-gate (trench-gate) is as device in the body, not limited, thus the main striving direction that reduces conducting resistance (Rdson) become.
The cell configuration of the power MOSFET of vertical trench generally has strip, closed quadrangle, hexagon or the like.Briefly, the power MOSFET of groove structure is exactly in the tagma of N type epitaxial loayer, etching a plurality of grooves; The silicon dioxide insulating layer that in groove, at first forms by thermal oxidation, the deposit polysilicon constitutes device grids then; In epitaxial loayer, between each groove, inject p type impurity and form the P well area; Then in the P well area, selectively inject N type impurity and form the source region; Deposit one deck oxide and one deck BPSG (Boro-Phospho-Silicate Glass, boron-phosphorosilicate glass) etch the trench openings of N type source region-P trap contact afterwards respectively in whole region surface again; Deposited metal etches metal level according to required graphics shape then; The growing surface passivation layer etches passivation layer window and is used for source, grid contact, for encapsulation is used thereupon; Behind the pad pasting protection front description, carry out back process in silicon chip back again: grind attenuate, deposited metal has formed the drain region contact of power MOSFET.
The conducting resistance of groove MOSFET is device summation of all resistance between source electrode and the drain electrode when conducting state.Conducting resistance is that a very important device parameters is because it has determined the maximum current capability of device.Its composition of conducting resistance has comprised metallic resistance, source region resistance, channel resistance, drift zone resistance, resistance substrate and contact resistance etc., in order to reduce conducting resistance, all resistance components all will reduce as much as possible, and the factor of most critical is the drift zone resistance that will reduce in channel resistance and the epitaxial loayer.Common method is to dwindle the MOSFET cell size promptly to increase element number on the unit are.In the design of the groove MOSFET that dwindles cell size, most important factor is a distance between trench-gate and the source contact hole.Foozle owing to producing in the registration error that exists reticle in technology and the course of processing need leave certain distance and prevent electrical property short circuit between grid and the source electrode.How guaranteeing dwindling cell size as much as possible under the prerequisite that is not short-circuited between the contact of trench-gate and source region, thereby improving the element number of unit are, is a problem that needs solution.
Figure 1A to Fig. 1 C is a step schematic diagram of making each technology of power MOSFET in the prior art.What Figure 1A showed is the pattern of photoresist after the photoetching, Figure 1B shows be the source region inject and High temperature diffusion after cross section, what Fig. 1 C showed is after silicon chip surface deposit one deck oxide and BPSG, again the cross-sectional view of the contact hole after other usefulness source region-P well region contact hole reticle etching.Shown in Figure 1A to Fig. 1 C, in original process, the step that the formation source region contacts with the source region is:
Form an epitaxial loayer 12 earlier on N type substrate 11, a plurality of channel shaped of etching become trench-gate 14 on this epitaxial loayer 12, in epitaxial loayer and between each groove, inject p type impurity and form P well area 15; After trench-gate 14 and 15 formation of P well area, use source region reticle 13, the source region 16 with N type impurity is injected; After whole region surface difference deposit one deck oxide and one deck BPSG (Boro-Phospho-Silicate Glass, boron-phosphorosilicate glass) 18, etch the trench openings 17 of N type source region 16-P well area 15 contacts again.
But diagram forms the method that the source region contacts with the source region above, after cell size narrows down to a certain degree, following problem can occur:
1, the width of the blue photoresist among Figure 1A can be more and more thinner, and the size relative error that causes in the explained hereafter can be increasing; And when the line thickness of photoresist carefully arrived certain degree, the phenomenon of photoresist avalanche can appear on the technology, cause the decline of product yield (yield).
2, in the above-mentioned step, two reticle have been used.One is the source region reticle, and another piece is source region-P well region contact hole reticle.Because the error of lithography registration makes that the distance imbalance tolerance between the contact of trench-gate and source region need be stayed greatlyyer, has restricted and has dwindled cell size further.
Summary of the invention
The technical problem to be solved in the present invention is in order to overcome defective of the prior art, a kind of power semiconductor and manufacture method thereof are provided, this power semiconductor and manufacture method thereof make highdensity realization become possibility, thereby can reduce the parameter of this important power device of conducting resistance, reduce the lithography registration tolerance that the distance between the contact of trench-gate and source region forms, avoided the thin phenomenon that occurs the photoresist avalanche to certain degree of width of photoresist simultaneously.
The present invention solves above-mentioned technical problem by following technical proposals: a kind of power semiconductor comprises a N type substrate; One is formed on the N type epi region of this N type substrate top, and one is formed on second metal level of this N type substrate below; One is formed at the P well area of this N type epi region top; One is formed at the source region on this P well area; A plurality ofly pass the grid that this P well area, this source region and this N type epi region contact; Be positioned at first insulating barrier of 1 on the source region, a first metal layer and one second insulating barrier successively; A plurality of contact holes that pass this first insulating barrier, this first metal layer contacts with this P well area, source region by those contact holes.
Another technical scheme of the present invention provides a kind of manufacture method of power semiconductor, and it may further comprise the steps: step 1: a N type substrate is provided, forms a N type epi region above this N type substrate; Step 2: on this N type epi region, form a plurality of grids; Step 3: above this N type epi region, form a P well area; Step 4: above this P well area, form a source region; Step 5: growth one first insulating barrier above this source region, and form a plurality of contact holes that pass this first insulating barrier; Step 6: deposit one the first metal layer above this first insulation; Step 7: deposit one second insulating barrier above this first metal layer; Step 8: deposit one second metal level below this N type substrate.
Wherein, the resistivity of described N type substrate is 0.001-0.005ohm.cm, and concentration is 1E19-5E19/cm
3
Wherein, the thickness of described N type epi region is 4-8 μ m, and resistivity is 1-5ohm.cm, and concentration is 1E14-1E16/cm
3
Wherein, the degree of depth of described P well area is less than the degree of depth of this grid.
Wherein, described first insulating barrier comprises oxide and boron-phosphorosilicate glass.
Wherein, described power semiconductor is a power metal oxide semiconductor field-effect transistor.
Wherein, the step 1 of described formation N type epi region is finished by the chemical vapor process growth.
Wherein, the step 2 of a plurality of grids of described formation specifically comprises following process: use the trench lithography version earlier, at a plurality of groove structures of trench region etching, then trench wall being carried out sacrificial oxidation handles, to remove by the groove silicon layer of plasma damage, again trench wall is done the gate insulation oxidation, then the deposit polysilicon comes filling groove inside and upper surface thereof, etch away unnecessary polysilicon, form grid at last.
Wherein, the step 3 of described formation P well area is by using P trap reticle to inject 1E13-1E14/cm at P type injection zone ion
2The boron of dosage is heat-treated and is advanced P trap impurity to enter that N type epi region finishes.
Wherein, the step 4 in described formation source region specifically comprises following process: handle the oxide layer of back formation 500A at P well area surface heat oxygen after, ion injects N type impurity then, and injection condition is about 5E14-1E16/cm for phosphorus dosage
2, energy is about 120KeV, heat-treats to advance phosphorus impurities to form the source region again.
Wherein, the step 5 of described growth first insulating barrier and a plurality of contact holes of formation specifically comprises following process: growth first insulating barrier above the source region, this first insulating barrier comprises oxide and boron-phosphorosilicate glass, use the contact hole reticle to carry out contact etching then, the contact hole that etches passes first insulating barrier and the source region is deep into the P well area always, carry out contact hole 28 then and inject, injection condition is that ion injects 8E14/cm
2, 40KeV boron.
Wherein, the step 8 of described deposit second metal level specifically comprises following process: N type substrate below by mechanical reduction behind 200 μ m, deposit second metal level again under 230 ℃ of temperature.
Positive progressive effect of the present invention is:
1. pass through to reduce the reticle number of manufacturing process, thereby reduced the complexity of manufacturing process, reduced production cost.
2. the present invention is applicable to various cell configurations, and that gives an example says, can be strip, quadrangle, hexagon, or the like.
3. the present invention can bring up to cell density per square inch more than 400,000,000.
Description of drawings
Figure 1A to Fig. 1 C is a step schematic diagram of making each technology of power MOSFET in the prior art.
Fig. 2 A to Fig. 2 H makes the step of each technology of power MOSFET for the present invention.
Embodiment
According to Fig. 2 A to Fig. 2 H, provide one embodiment of the invention, and described in detail below,, rather than be used for limiting scope of the present invention so that those skilled in the art is easier to understand architectural feature of the present invention and function characteristics.
Shown in Fig. 2 A to Fig. 2 H, the present invention makes power MOSFET and comprises following processing step:
Step 1: shown in Fig. 2 A, at first, be 0.001-0.005ohm.cm in resistivity, concentration reaches 1E19-5E19/cm
3 N type substrate 21 on, be 4-8 μ m by the chemical vapor process thickness that grows out, resistivity is the N type epi region 22 of 1-5ohm.cm, the concentration of this N type epi region 22 is approximately 1E14-1E16/cm
3
Step 2: shown in Fig. 2 B, use the trench lithography version, at a plurality of groove structures of trench region etching, the degree of depth is approximately 1-3 μ m, then trench wall is carried out sacrificial oxidation and handles, to remove by the groove silicon layer of plasma damage, again trench wall is done the gate insulation oxidation, then the deposit polysilicon comes filling groove inside and upper surface thereof, etches away unnecessary polysilicon, has formed the grid 24 of groove MOSFET.
Step 3: shown in Fig. 2 C, use P trap (P-WELL) reticle, inject 1E13-1E14/cm at P type injection zone ion
2The boron of dosage is heat-treated propelling P trap impurity again and is entered N type epi region 22 formation P well areas 25, and the degree of depth of P well area 25 is approximately 1-2 μ m, less than the degree of depth of grid 24.
Step 4: shown in Fig. 2 D, after P well area 25 surface heat oxygen are handled the oxide layer of back formation 500A, the silicon chip surface ion is injected N type impurity, injection condition is: phosphorus dosage is about 5E14-1E16/cm
2, energy is about 120KeV, heat-treats to advance phosphorus impurities to form source region 26 again.
Step 5: shown in Fig. 2 E, growth one first insulating barrier 27 above source region 26, this first insulating barrier 27 comprises oxide and boron-phosphorosilicate glass (BPSG), use the contact hole reticle to carry out contact etching then, the contact hole 28 that etches passes first insulating barrier 27 and source region 26, is deep into P well area 25 always.Carry out contact hole 28 then and inject, injection condition is: ion injects 8E14/cm
2, 40KeV boron, purpose is that the metal level 29 that P well area 25 can and be formed afterwards forms good Ohmic contact.
Step 6: shown in Fig. 2 F, at first insulating barrier, 27 deposits, one the first metal layer 29, the first metal layer 29 contacts with P well area 25, source region 26 by contact hole 28, forms the source electrode contact.
Step 7: shown in Fig. 2 G, deposit one second insulating barrier 30 above the first metal layer 29 uses the pad reticle that insulating barrier is carried out etching, leaves the pad window, is used for the encapsulation contact.
Step 8: shown in Fig. 2 H, behind 200 μ m, deposit one second metal level 31 again under 230 ℃ of temperature forms the drain electrode contact of groove MOSFET by mechanical reduction in N type substrate 21 belows.
From the above, power MOSFET of the present invention comprises a N type substrate 21, lay respectively at the N type epi region 22 and second metal level 31 of these N type substrate 21 upper and lowers, be formed at the P well area 25 of N type epi region 22 tops, be positioned at the source region 26 on this P well area 25, a plurality of trench-gates 24 pass P well area 25, source region 26 contacts with N type epi region 22, be positioned at first insulating barrier 27 on the source region 26 successively, the first metal layer 29 and second insulating barrier 30, wherein a plurality of contact holes 28 pass first insulating barrier 27, and the first metal layer 29 is by contact hole 28 and P well area 25, source region 26 contacts.And, in order to reduce the lithography registration tolerance of the distance formation between the contact of trench-gate and source region as far as possible, avoid the thin phenomenon that occurs the photoresist avalanche to certain degree of width of photoresist simultaneously, main feature about the manufacture method of highdensity trench-gate power MOSFET among the present invention is: omitted the reticle that the source region photoetching is used, after the technology making step forms the P well area, directly the whole silicon wafer surface ion is injected N type impurity, thereby formed a continuous thin layer source region at the surface portion of whole P well area; Again at surface deposition after first insulating barrier, directly carry out contact etching with the contact hole reticle, formed and passed the contact hole that insulating material and thin layer source region are deep into the P well area always, follow the deposit the first metal layer, the first metal layer has formed with source region, the vertical of P well area by this contact hole and has contacted.
In sum, positive progressive effect of the present invention is:
1. pass through to reduce the reticle number of manufacturing process, thereby reduced the complexity of manufacturing process, reduced production cost.
2. the present invention is applicable to various cell configurations, and that gives an example says, can be strip, quadrangle, hexagon, or the like.
3. the present invention can bring up to cell density per square inch more than 400,000,000.
Though more than described the specific embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, under the prerequisite that does not deviate from principle of the present invention and essence, can make numerous variations or modification to these execution modes.Therefore, protection scope of the present invention is limited by appended claims.
Claims (13)
1. power semiconductor is characterized in that it comprises:
One N type substrate;
One is formed on the N type epi region of this N type substrate top, and one is formed on second metal level of this N type substrate below;
One is formed at the P well area of this N type epi region top;
One is formed at the source region on this P well area;
A plurality ofly pass the grid that this P well area, this source region and this N type epi region contact;
Be positioned at first insulating barrier of 1 on the source region, a first metal layer and one second insulating barrier successively;
A plurality of contact holes that pass this first insulating barrier, this first metal layer contacts with this P well area, source region by those contact holes.
2. power semiconductor as claimed in claim 1 is characterized in that, the resistivity of described N type substrate is 0.001-0.005ohm.cm, and doping content is 1E19-5E19/cm
3
3. power semiconductor as claimed in claim 1 is characterized in that, the thickness of described N type epi region is 4-8 μ m, and resistivity is 1-5ohm.cm, and doping content is 1E14-1E16/cm
3
4. power semiconductor as claimed in claim 1 is characterized in that the degree of depth of described P well area is less than the degree of depth of this grid.
5. power semiconductor as claimed in claim 1 is characterized in that, described first insulating barrier comprises oxide and boron-phosphorosilicate glass.
6. power semiconductor as claimed in claim 1 is characterized in that, described power semiconductor is a power metal oxide semiconductor field-effect transistor.
7. the manufacture method of a power semiconductor is characterized in that, it may further comprise the steps:
Step 1: a N type substrate is provided, above this N type substrate, forms a N type epi region;
Step 2: on this N type epi region, form a plurality of grids;
Step 3: above this N type epi region, form a P well area;
Step 4: above this P well area, form a source region;
Step 5: growth one first insulating barrier above this source region, and form a plurality of contact holes that pass this first insulating barrier;
Step 6: deposit one the first metal layer above this first insulation;
Step 7: deposit one second insulating barrier above this first metal layer;
Step 8: deposit one second metal level below this N type substrate.
8. the manufacture method of power semiconductor as claimed in claim 7 is characterized in that, the described step 1 that forms N type epi region is finished by the chemical vapor process growth.
9. the manufacture method of power semiconductor as claimed in claim 7, it is characterized in that, the described step 2 that forms a plurality of grids specifically comprises following process: use the trench lithography version earlier, at a plurality of groove structures of trench region etching, then trench wall is carried out sacrificial oxidation and handle, to remove by the groove silicon layer of plasma damage, again trench wall is done the gate insulation oxidation, then the deposit polysilicon comes filling groove inside and upper surface thereof, etches away unnecessary polysilicon, forms grid at last.
10. the manufacture method of power semiconductor as claimed in claim 7 is characterized in that, the described step 3 that forms the P well area is by using P trap reticle to inject 1E13-1E14/cm at P type injection zone ion
2The boron of dosage is heat-treated and is advanced P trap impurity to enter that N type epi region finishes.
11. the manufacture method of power semiconductor as claimed in claim 7 is characterized in that, the described step 4 that forms the source region specifically comprises following process: handle the back at P well area surface heat oxygen and form
Oxide layer after, ion injects N type impurity then, injection condition is 5E14-1E16/cm for phosphorus dosage
2, energy is 120KeV, heat-treats to advance phosphorus impurities to form the source region again.
12. the manufacture method of power semiconductor as claimed in claim 7, it is characterized in that, first insulating barrier of growing specifically comprises following process with the described step 5 that forms a plurality of contact holes: growth first insulating barrier above the source region, this first insulating barrier comprises oxide and boron-phosphorosilicate glass, use the contact hole reticle to carry out contact etching then, the contact hole that etches passes first insulating barrier and the source region is deep into the P well area always, carry out contact hole then and inject, injection condition is that ion injects 8E14/cm
2, 40KeV boron.
13. the manufacture method of power semiconductor as claimed in claim 7, it is characterized in that, the described step 8 of deposit second metal level specifically comprises following process: N type substrate below by mechanical reduction behind 200 μ m, deposit second metal level again under 230 ℃ of temperature.
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| CN103854979B (en) * | 2012-11-28 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | A kind of super junction extension CMP method |
| CN104157578B (en) * | 2014-08-26 | 2018-04-27 | 上海华虹宏力半导体制造有限公司 | The forming method of semiconductor devices |
| CN106298946A (en) * | 2016-10-09 | 2017-01-04 | 无锡新洁能股份有限公司 | A kind of manufacture method reducing low pressure Trench DMOS conducting resistance |
| CN114334621B (en) * | 2022-01-04 | 2023-08-11 | 广东芯粤能半导体有限公司 | Semiconductor structure, semiconductor device and preparation method thereof |
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| CN101026190A (en) * | 2007-03-30 | 2007-08-29 | 东南大学 | Trench high-pressure N-type metal oxide semiconductor tube and its preparing process |
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| CN101026190A (en) * | 2007-03-30 | 2007-08-29 | 东南大学 | Trench high-pressure N-type metal oxide semiconductor tube and its preparing process |
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