CN108258040A - Igbt with wide band gap semiconducter substrate material and preparation method thereof - Google Patents
Igbt with wide band gap semiconducter substrate material and preparation method thereof Download PDFInfo
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- 239000010703 silicon Substances 0.000 claims abstract description 43
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- 238000000034 method Methods 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The present invention proposes a kind of igbt (IGBT) with wide band gap semiconducter substrate material and preparation method thereof.The IGBT device is mainly characterized by wide bandgap semiconductor materials being combined with silicon semiconductor material, using wide bandgap semiconductor materials as the anode of IGBT device and substrate.The higher N+ molded breadth bandgap semiconductor material buffer layers of doping concentration are first formed on wide bandgap semiconductor materials P+ type substrate, and then the relatively low N-type wide bandgap semiconductor materials epitaxial layer of doping concentration is formed on N+ molded breadth band gap buffer layers, it is combined based on the N-type wide band gap semiconducter epitaxial layer using crystal bonding technology with N-type silicon semiconductor layer again, forms the active area of IGBT device on silicon bonding layer by silicon maturation process.The present invention can significantly improve the breakdown voltage of IGBT, improve device performance.
Description
Technical field
The present invention relates to power semiconductor field more particularly to a kind of igbt (IGBT) and its systems
Make method.
Background technology
Power semiconductor refer to be mainly used for power equipment transformation of electrical energy and control circuit in terms of high-power electricity
Sub- device.Important Components of the igbt (IGBT) as power semiconductor field, because it is with on-state
Resistance is low, saturation pressure reduces, current handling capability is strong, loss is low, input impedance is high, driving power is small, switching speed is very fast etc.
Good characteristic has been widely used in power integrated circuit and power integrated system.In recent years, to the characteristic of IGBT device
Optimization mainly studies ripe superjunction technique and realizes the IGBT device with superjunction.
Invention content
The present invention proposes a kind of new igbt power device, it is intended to further improve the breakdown potential of IGBT
Pressure improves device performance.
Technical scheme is as follows：
The igbt with broad-band gap substrate material, including：
The P+ type substrate of wide bandgap semiconductor materials；
In the N+ type buffer layers for the wide bandgap semiconductor materials that the P+ type substrate top surface is epitaxially-formed, it is denoted as N+
Molded breadth band gap buffer layer；
In the N-type extension of wide bandgap semiconductor materials that the N+ molded breadths band gap buffer layer upper surface is epitaxially-formed
Layer, is denoted as N-type broad-band gap epitaxial layer；
The N-type bonded layer of crystal bonding technology combination silicon materials is utilized in the N-type broad-band gap epitaxial layer upper surface, is denoted as
N-type silicon bonding layer；
The p-type base area at two that left and right two end regions on the N-type silicon bonding layer top are formed respectively；Everywhere p-type base
Raceway groove and N+ types source region and the contact of P+ channeled substrates are formed in area, wherein N+ types source region is abutted with raceway groove, and P+ channeled substrates connect
It touches and is located at raceway groove distal end relative to N+ types source region；
Gate oxide, between p-type base area at two and the upper surface of part N+ types source region and respective channels, middle part is covered
The upper surface of lid N-type silicon bonding layer；
Grid, inside gate oxide；
Source electrode covers the upper surface that corresponding P+ channeled substrates contact the region that connects with N+ type source regions, and source electrode connects altogether at two；
Drain electrode, positioned at the lower surface of the P+ type substrate；
The thickness and doping concentration of the N-type broad-band gap epitaxial layer determines by the resistance to pressure request of device, N-type broad-band gap extension
The doping concentration of layer is less than the doping concentration of N+ molded breadth band gap buffer layers and P+ type substrate.
On the basis of above scheme, the present invention has also further made following optimization：
Above-mentioned wide bandgap semiconductor materials use silicon carbide, gallium nitride or diamond.
Difference of the doping concentration of above-mentioned N-type broad-band gap epitaxial layer compared with P+ type substrate is true according to the breakdown voltage of design
It is fixed, 4-6 order of magnitude of P+ type substrate doping is generally should be smaller than, 2-4 number smaller than N+ molded breadth band gap buffer layer doping concentrations
Magnitude.
The general value of doping concentration of above-mentioned N-type broad-band gap epitaxial layer is (1014-1016)cm-3。
The thickness and doping concentration of above-mentioned N-type broad-band gap epitaxial layer determines according to the breakdown voltage of design, such as：P+ type serves as a contrast
The doping concentration at bottom is 1 × 1020cm-3, the doping concentration of N+ molded breadth band gap buffer layers is 1 × 1018cm-3；Resistance to pressure request is
360V, then the thickness of N-type broad-band gap epitaxial layer is 5 microns, and the doping concentration of N-type broad-band gap epitaxial layer and N-type silicon bonding layer is 1
×1015cm-3；Resistance to pressure request is 510V, then the thickness of N-type broad-band gap epitaxial layer is 14 microns, N-type broad-band gap epitaxial layer and N-type
The doping concentration of silicon bonding layer is 2 × 1015cm-3；Resistance to pressure request is 720V, then the thickness of N-type broad-band gap epitaxial layer is micro- for 14
The doping concentration of rice, N-type broad-band gap epitaxial layer and N-type silicon bonding layer is 1 × 1015cm-3。
Aforementioned p-type base area and its N+ types source region and the contact of P+ channeled substrates and raceway groove, are led on N-type silicon bonding layer top
Cross what ion implanting and double diffusion technique were formed.
Above-mentioned grid is polysilicon gate, and source electrode is metallizing source, is drained as metalized drain.
A kind of method for making the above-mentioned igbt with broad-band gap substrate material, includes the following steps：
(1) prepare P+ type wide bandgap semiconductor materials as P+ type substrate；
(2) N+ molded breadth band gap buffers are epitaxially-formed in the upper surface of the P+ type substrate of the wide bandgap semiconductor materials
Layer；
(3) it is epitaxially-formed N-type broad-band gap epitaxial layer in the upper surface of the N+ molded breadths band gap buffer layer；
(4) in the N-type broad-band gap epitaxial layer upper surface, pass through room temperature crystal bonding techniques combination N-type silicon bonding layer, key
High annealing after the completion of conjunction；
(5) aoxidize to form silica membrane in the N-type silicon bonding layer upper surface, under mask protection, using it is each to
Anisotropic etching methods etch silica membrane, form active area；
(6) gate oxide, and depositing polysilicon are further formed in N-type silicon bonding layer upper surface, then etches polycrystalline silicon
And gate oxide, removal form polysilicon gate positioned at the part of left and right two end regions；
(7) p-type is formed by boron ion injection and double diffusion technique in left and right two end regions on N-type silicon bonding layer top
Base area, and carry out pushing away trap process, junction depth depends finally on the temperature and time for pushing away trap；
(8) the N+ source regions of heavy doping and the contact of P+ channeled substrates are further formed by way of ion implanting, using double
Diffusion technique forms corresponding raceway groove, and annealing time is short as possible after the completion of injection；
(9) in device surface silicon oxide deposition film, and contact hole is etched in the position corresponding to source electrode；
(10) metal is deposited in contact hole and etches to remove remaining silicon oxide film of periphery, forms source electrode, and will
Source electrode connects altogether at two；
(11) metalized drain is formed in P+ type substrate lower surface.
Technical solution of the present invention has the beneficial effect that：
The IGBT device substrate of the present invention is first formed in broad-band gap P+ type substrate material upper surface and is mixed using wide bandgap material
The higher N+ molded breadth band gap buffer layers of miscellaneous concentration, and then the relatively low N of doping concentration is formed in N+ molded breadth band gap buffer layers upper surface
Molded breadth band gap epitaxial layer, then combined based on the N-type broad-band gap epitaxial layer using crystal bonding technology with N-type silicon bonding layer,
By using silicon maturation process device active region is formed in silicon bonding layer.Utilize the longitudinal electric field (device generated in wide bandgap material
During part OFF state pressure resistance) to the modulating action of the longitudinal electric field in silicon bonding layer, make the longitudinal electric field integral raising of device, breakdown potential
Pressure increase, in the case where thickness identical drift doping concentration in device drift region is identical and relatively low, compared with traditional silicon substrate IGBT
Breakdown voltage can improve more than 71%, while the high heat conductance characteristic of wide bandgap material is conducive to the heat dissipation of device, device performance
It is effectively improved.
Description of the drawings
Fig. 1-Figure 11 is the element manufacturing flow diagram of one embodiment of the invention；
Figure 12 is the structure diagram of one embodiment of the invention IGBT device.
Wherein, 101- source electrodes；102- gate oxides；103- grids；104- source electrodes；105-P+ channeled substrates contact (P+ type
Body area)；106-N+ type source regions；107-P types base area；The P+ type substrate of 801- wide bandgap semiconductor materials；802-N+ molded breadth band gap
Buffer layer；803-N molded breadth band gap epitaxial layers；804-N type silicon bonding layers；108- drains.
Specific embodiment
The present invention is introduced by taking N-channel IGBT as an example below in conjunction with the accompanying drawings.
As shown in Figure 1-Figure 11, which can specifically be prepared by following steps：
(1) prepare P+ type wide bandgap semiconductor materials as P+ type substrate 801, as shown in Figure 1；
(2) N+ molded breadth band gap is epitaxially-formed in the upper surface of the P+ type substrate 801 of the wide bandgap semiconductor materials
Buffer layer 802, as shown in Figure 2；
(3) N-type broad-band gap epitaxial layer 803 is epitaxially-formed in the upper surface of the N+ molded breadths band gap buffer layer 802, such as
Shown in Fig. 3.Wide bandgap semiconductor materials are using silicon carbide, gallium nitride or diamond, the doping of N-type broad-band gap epitaxial layer 802
A concentration of (1014-1016)cm-3, the doping concentration of N-type broad-band gap epitaxial layer 803 is smaller 4-6 than the doping concentration of P+ type substrate 801
A order of magnitude, the 2-4 order of magnitude smaller than the doping concentration of N+ molded breadth band gap buffers layer 802；
(4) in 803 upper surface of N-type broad-band gap epitaxial layer, pass through room temperature crystal bonding techniques combination N-type silicon epitaxy layer
804, high annealing after the completion of bonding, as shown in Figure 4.
(5) it aoxidizes to form silica membrane in 804 upper surface of N-type silicon bonding layer, under mask protection, using each
Anisotropy lithographic method etches silica membrane, forms active area (not marked in figure), as shown in Figure 5.
(6) gate oxide 102, and depositing polysilicon are further formed in 804 upper surface of N-type silicon bonding layer, then etched
Polysilicon and gate oxide, removal form polysilicon gate 103, as shown in Figure 6 positioned at the part of left and right two end regions.
(7) P is formed by boron ion injection and double diffusion technique in left and right two end regions on 804 top of N-type silicon bonding layer
Type base area 107, and carry out pushing away trap process, junction depth depends finally on the temperature and time for pushing away trap, as shown in Figure 7.
(8) the N+ source regions 106 of heavy doping and P+ channeled substrates contact 105 are further formed by way of ion implanting,
Corresponding raceway groove (not marked in figure) is formed using double diffusion technique, annealing time is short as possible after the completion of injection, such as Fig. 8 institutes
Show.
(9) in device surface silicon oxide deposition film, and contact hole is etched in the position corresponding to source electrode, as shown in Figure 9.
(10) metal is deposited in contact hole and etches to remove remaining silicon oxide film of periphery, formed source electrode 101,
104, and source electrode at two is connect (do not marked in figure) altogether, as shown in Figure 10.
(11) metalized drain 108 is formed in 801 lower surface of P+ type substrate, as shown in figure 11.
As shown in figure 12, the structure composition of the device is mainly：
The P+ type substrate 801 of wide bandgap semiconductor materials；
In the wide bandgap semiconductor materials that 801 upper surface of P+ type substrate of wide bandgap semiconductor materials is epitaxially-formed
N+ type buffer layers are denoted as N+ molded breadth band gap buffers layer 802；
Outside the N-type of wide bandgap semiconductor materials being epitaxially-formed in 802 upper surface of N+ molded breadths band gap buffer layer
Prolong layer, be denoted as N-type broad-band gap epitaxial layer 803；
The N-type bonded layer of crystal bonding technology combination silicon materials is utilized in 803 upper surface of N-type broad-band gap epitaxial layer,
It is denoted as N-type silicon bonding layer 804；
The p-type base area 107 at two that left and right two end regions on the N-type silicon bonding layer top are formed respectively；Everywhere P
Raceway groove and N+ types source region 106 and P+ channeled substrates contact 105 are formed in type base area 107, wherein N+ types source region 106 and raceway groove is adjacent
It connects, P+ channeled substrates contact 105 is located at raceway groove distal end relative to N+ types source region 106；
Gate oxide 102, between p-type base area 107 at two and the upper table of part N+ types source region 106 and respective channels
Face, middle part cover the upper surface of the N-type silicon bonding layer；
Grid 103, inside gate oxide；
Source electrode 101,104 covers corresponding P+ channeled substrates contact 105 and connects with N+ types source region 106 upper surface in region；
Source electrode 101,104 connects altogether at two；
Drain electrode 108, positioned at 801 lower surface of P+ type substrate.
Compared with traditional silicon substrate IGBT device, IGBT device of the invention is by wide bandgap semiconductor materials and silicon semiconductor material
Material is combined, part drift region, buffer layer and substrate using wide bandgap semiconductor materials as IGBT device.
Show performance improvement of the device compared with traditional silicon substrate IGBT through ISE TCAD emulation, two kinds of device drift regions
Thickness is identical, and in the case that drift doping concentration is identical and relatively low, the breakdown voltage of the device improves more than 71%.
IGBT in the present invention can certainly be P-type channel, and structure is equal with above-mentioned N-channel IGBT, it should also regard
To belong to the application scope of the claims, details are not described herein.
Extension is silicon semiconductor material in wide bandgap semiconductor materials material above in the present invention, should be broadly understood,
I.e. the other elements such as germanium semi-conducting material is equal with the IGBT that wide band gap semiconducter forms IGBT with the present invention illustrates, it should also regard
To belong to the application scope of the claims, details are not described herein.
Claims (9)
1. the igbt with wide band gap semiconducter substrate material, which is characterized in that including：
The P+ type substrate (801) of wide bandgap semiconductor materials；
In the N+ type buffer layers of wide bandgap semiconductor materials that P+ type substrate (801) upper surface is epitaxially-formed, it is denoted as N
+ molded breadth band gap buffer layer (802)；
In the N-type extension of wide bandgap semiconductor materials that N+ molded breadths band gap buffer layer (802) upper surface is epitaxially-formed
Layer, is denoted as N-type broad-band gap epitaxial layer (803)；
The N-type bonded layer of crystal bonding technology combination silicon materials, note are utilized in N-type broad-band gap epitaxial layer (803) upper surface
For N-type silicon bonding layer (804)；
The p-type base area (107) at two that left and right two end regions on N-type silicon bonding layer (804) top are formed respectively；It is each
Locate to form raceway groove and N+ types source region (106) and P+ channeled substrates contact (105), wherein N+ types source region in p-type base area (107)
(106) it is abutted with raceway groove, P+ channeled substrates contact (105) relative to N+ types source region (106) positioned at raceway groove distal end；
Gate oxide (102), between p-type base area (107) at two and part N+ types source region (106) and respective channels it is upper
Surface, the upper surface of middle part covering N-type silicon bonding layer (804)；
Grid (103), inside gate oxide；
Source electrode (101,104) at two cover corresponding P+ channeled substrates contact (105) and connect with N+ types source region (106) region
Upper surface, and source electrode (101,104) connects altogether at two；
It drains (108), positioned at the lower surface of the P+ type substrate (801)；
The thickness and doping concentration of the N-type broad-band gap epitaxial layer (803) are determined by the resistance to pressure request of device, outside N-type broad-band gap
Prolong doping concentration of the doping concentration less than N+ molded breadth band gap buffer layers (802) and P+ type substrate (801) of layer (803).
2. the igbt according to claim 1 with wide band gap semiconducter substrate material, feature exist
In：The wide bandgap semiconductor materials use silicon carbide, gallium nitride or diamond.
3. the igbt according to claim 1 with wide band gap semiconducter substrate material, feature exist
In：The doping concentration of N-type broad-band gap epitaxial layer (803) the 4-6 order of magnitude smaller than the doping concentration of P+ type substrate (801), compares N+
The small 2-4 order of magnitude of doping concentration of molded breadth band gap buffer layer (802).
4. the igbt according to claim 3 with wide band gap semiconducter substrate material, feature exist
In：The doping concentration of the N-type broad-band gap epitaxial layer (803) is (1014-1016)cm-3。
5. the igbt according to claim 4 with wide band gap semiconducter substrate material, feature exist
In：The doping concentration of P+ type substrate (801) is 1 × 1020cm-3, the doping concentrations of N+ molded breadth band gap buffer layers (802) for 1 ×
1018cm-3；
Resistance to pressure request be 360V, then the thickness of N-type broad-band gap epitaxial layer (803) be 5 microns, N-type broad-band gap epitaxial layer (803) and
The doping concentration of N-type silicon bonding layer (804) is 1 × 1015cm-3；
Resistance to pressure request is 510V, then the thickness of N-type broad-band gap epitaxial layer (803) is 14 microns, N-type broad-band gap epitaxial layer (803)
And the doping concentration of N-type silicon bonding layer (804) is 2 × 1015cm-3；
Resistance to pressure request is 720V, then the thickness of N-type broad-band gap epitaxial layer (803) is 14 microns, N-type broad-band gap epitaxial layer (803)
And the doping concentration of N-type silicon bonding layer (804) is 1 × 1015cm-3。
6. the igbt according to claim 1 with wide band gap semiconducter substrate material, feature exist
In：The p-type base area (107) and its N+ types source region (106) and P+ channeled substrates contact (105) and raceway groove, are in N-type silicon key
Close what layer (804) top was formed by ion implanting and double diffusion technique.
7. the igbt according to claim 1 with wide band gap semiconducter substrate material, feature exist
In：The grid (103) is polysilicon gate, and the source electrode (101,104) is metallizing source, and the drain electrode (108) is gold
Categoryization drains.
8. a kind of method for making the igbt with wide band gap semiconducter substrate material described in claim 1,
Include the following steps：
(1) prepare P+ type wide bandgap semiconductor materials as P+ type substrate (801)；
(2) N+ molded breadth band gap is epitaxially-formed in the upper surface of the P+ type substrate (801) of the wide bandgap semiconductor materials to delay
Rush layer (802)；
(3) it is epitaxially-formed N-type broad-band gap epitaxial layer (803) in the upper surface of the N+ molded breadths band gap buffer layer (802)；
(4) in N-type broad-band gap epitaxial layer (803) upper surface, pass through room temperature crystal bonding techniques combination N-type silicon bonding layer
(804), high annealing after the completion of bonding；
(5) aoxidize to form silica membrane in N-type silicon bonding layer (804) upper surface, under mask protection, using it is each to
Anisotropic etching methods etch silica membrane, form active area；
(6) gate oxide (102), and depositing polysilicon are further formed in N-type silicon bonding layer (804) upper surface, then etched
Polysilicon and gate oxide, removal form polysilicon gate (103) positioned at the part of left and right two end regions；
(7) it injects to form p-type base area (107) by boron ion in left and right two end regions on N-type silicon bonding layer (804) top, and
It carries out pushing away trap process, junction depth depends finally on the temperature and time for pushing away trap；
(8) the N+ source regions (106) of heavy doping and P+ channeled substrates contact (105) are further formed by way of ion implanting,
Corresponding raceway groove is formed using double diffusion technique, annealing time is short as possible after the completion of injection；
(9) in device surface silicon oxide deposition film, and contact hole is etched in the position corresponding to source electrode；
(10) metal is deposited in contact hole and etches to remove remaining silicon oxide film of periphery, forms source electrode (101,104),
And source electrode at two is connect altogether；
(11) metalized drain is formed in P+ type substrate (801) lower surface.
9. according to the method described in claim 8, it is characterized in that：The wide bandgap semiconductor materials are using silicon carbide, nitridation
Gallium or diamond.
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