CN107123684B - Vertical double-diffusion metal oxide semiconductor field effect transistor with wide band gap material and silicon material composite - Google Patents
Vertical double-diffusion metal oxide semiconductor field effect transistor with wide band gap material and silicon material composite Download PDFInfo
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- 239000002210 silicon-based material Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 230000005669 field effect Effects 0.000 title claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 15
- 150000004706 metal oxides Chemical class 0.000 title claims description 15
- 239000002131 composite material Substances 0.000 title claims description 11
- 238000009792 diffusion process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
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- 239000010703 silicon Substances 0.000 claims abstract description 37
- 238000005516 engineering process Methods 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 5
- 229910002601 GaN Inorganic materials 0.000 claims description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000009286 beneficial effect Effects 0.000 abstract description 3
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The VDMOS device is mainly characterized in that the wide band gap material is combined with the silicon material, an N-type wide band gap epitaxial layer with smaller doping concentration is formed on the upper surface of a wide band gap N + type substrate material, the N-type wide band gap epitaxial layer is taken as a base to carry out heteroepitaxial growth (or is formed by utilizing a bonding technology) on the N-type wide band gap epitaxial layer, and a device active region is formed by adopting a silicon mature process. The high-critical breakdown electric field characteristic of the wide-band-gap material is utilized, the high electric field peak of the device is introduced into the wide-band-gap material, the longitudinal electric field peak of the device is raised, the device can bear higher breakdown voltage, the limitation that the breakdown voltage of the device is limited by the critical breakdown electric field of a single silicon material is broken through, meanwhile, the high-thermal-conductivity characteristic of the wide-band-gap material is beneficial to heat dissipation of the device, and the performance of the device is effectively improved.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a vertical double-diffusion metal oxide field effect transistor.
Background
The power semiconductor device is a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. With the rapid development of power electronic technology, power semiconductor devices have been widely used in modern industrial control and defense equipment. Vertical Double-diffused Metal-Oxide-Semiconductor field effect transistors (VDMOS) are commonly used in power integrated circuits and power integrated systems due to their characteristics of fast switching speed, low loss, high input impedance, low driving power, good frequency characteristics, high transconductance, high linearity, and the like.
In recent years, the characteristic optimization of the VDMOS device is mainly to research a mature super junction process to realize the VDMOS device with the super junction.
Disclosure of Invention
The invention provides a novel vertical double-diffusion metal oxide semiconductor power device, aiming at further improving the breakdown voltage of a VDMOS and improving the performance of the device.
The technical scheme of the invention is as follows:
the vertical double-diffusion metal oxide semiconductor field effect transistor with the wide band gap material and the silicon material composite comprises:
an N + type substrate of wide bandgap semiconductor material;
an N-type epitaxial layer made of a wide band gap semiconductor material is formed on the upper surface of the N + type substrate and is marked as an N-type wide band gap epitaxial layer;
heteroepitaxially growing or forming an N-type silicon epitaxial layer (generally called a bonding layer formed by using a bonding technology, and collectively referred to as an N-type silicon epitaxial layer) on the upper surface of the N-type wide band gap epitaxial layer by using a bonding technology;
two P-type base regions are respectively formed in the left end region and the right end region of the upper part of the N-type silicon epitaxial layer; a channel and an N + type source region are formed in each P type base region and are contacted with a P + channel substrate, wherein the N + type source region is adjacent to the channel, and the P + channel substrate contact is positioned at the far end of the channel relative to the N + type source region; the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and a channel is still positioned in the silicon epitaxial layer;
the gate oxide layer covers the part of the N-type silicon epitaxial layer between the two P-type base regions and the corresponding two channels;
the grid is positioned on the upper surface of the grid oxide layer;
the source electrode covers the upper surface of a region where the P + channel substrate contact and the N + type source region are connected; two source electrodes are connected in common;
the drain electrode is positioned on the lower surface of the N + type substrate;
the thickness and the doping concentration of the N-type wide band gap epitaxial layer are determined by the withstand voltage requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer is lower than that of the N + type substrate.
On the basis of the scheme, the invention further optimizes the following steps:
the wide band gap semiconductor material adopts silicon carbide or gallium nitride.
The doping concentration of the N-type wide band gap epitaxial layer is determined according to the designed breakdown voltage, and the difference compared with an N + type substrate is about 4-6 orders of magnitude.
The N-type silicon epitaxial layer is a thin layer (about 1-6 microns), and the part of the P-type base region extending into the wide-bandgap N-type epitaxial layer is not more than two thirds.
The thickness of the wide bandgap epitaxial layer is determined according to the designed breakdown voltage. For example, when the withstand voltage is 900V, the thickness of the wide bandgap epitaxial layer is about 17 μm.
The doping concentration of the N-type wide band gap epitaxial layer is determined according to the designed breakdown voltage, and is generally (10)14‐1016)cm‐3
The P-type base region, the N + type source region of the P-type base region, the P + channel substrate contact and the channel are formed on the upper portion of the N-type silicon epitaxial layer by adopting ion implantation and double diffusion technologies.
The grid electrode is a polysilicon grid electrode, the source electrode is a metalized source electrode, and the drain electrode is a metalized drain electrode.
A method for manufacturing the vertical double-diffused metal oxide semiconductor field effect transistor compounded by the material with the wide band gap and the silicon material comprises the following steps:
(1) forming the N-type wide band gap epitaxial layer on the upper surface of an N + type substrate made of a wide band gap semiconductor material;
(2) growing an N-type silicon epitaxial layer by a heteroepitaxial growth technology;
(2) forming a metalized drain on the lower surface of the N + type substrate;
(3) forming a P-type base region and an N + type source region thereof in contact with a P + channel substrate in the left and right end regions of the upper part of the N-type silicon epitaxial layer by adopting ion implantation, and forming a corresponding channel by adopting a double diffusion technology to ensure that the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and the channel is still positioned in the silicon epitaxial layer;
(4) forming a gate oxide layer on the upper surface of the whole N-type silicon epitaxial layer, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer (removing the parts of the left and right end regions) to form a polycrystalline silicon gate;
(5) depositing a passivation layer on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(6) and depositing metal in the contact hole and etching (removing the rest passivation layer on the periphery) to form a source electrode, and connecting the two source electrodes together.
The technical scheme of the invention has the following beneficial effects:
the substrate of the VDMOS device is made of a wide-band-gap material, an N-type wide-band-gap epitaxial layer with low doping concentration is formed on the upper surface of a wide-band-gap N + type substrate material, an N-type silicon epitaxial layer is formed through a hetero-epitaxial technology (or a bonding technology), and the active region of the device is manufactured through a silicon mature process. The high electric field peak generated by the P-type base region/N-type wide band gap epitaxial layer junction is positioned in the wide band gap material, the characteristic of the high critical breakdown electric field of the wide band gap material is utilized, the longitudinal electric field peak of the device is raised, the device can bear higher breakdown voltage, the limitation that the traditional silicon-based VDMOS breakdown voltage is limited by the critical breakdown electric field of a single silicon material is broken through, and the breakdown voltage is improved by 2-3 times compared with the traditional VDMOS breakdown voltage under the condition that the length of a drift region of the device and the concentration of the drift region are the same. Meanwhile, the high heat conductivity of the wide band gap material is beneficial to heat dissipation of the device, and the performance of the device is effectively improved.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Wherein, 1-source electrode; 2-a gate oxide layer; 3-a grid; a 4-source electrode; a 5-P + channel substrate contact (P + type body region); a 6-N + type source region; 7-P type base region; 801-N + type substrate of wide band gap material; an 802-N type wide band gap epitaxial layer; 9-drain electrode.
Detailed Description
The invention will be described below by taking an N-channel VDMOS as an example in conjunction with the accompanying drawings.
As shown in fig. 1, this example includes:
an N + type substrate 801 of wide bandgap semiconductor material;
an N-type epitaxial layer made of a wide band gap semiconductor material is formed on the upper surface of an N + type substrate 801 and is marked as an N-type wide band gap epitaxial layer 802;
an N-type silicon epitaxial layer formed by heteroepitaxial growth or bonding technology on the upper surface of the N-type wide band gap epitaxial layer 802;
two P-type base regions 7 are respectively formed in the left and right end regions of the upper part of the N-type silicon epitaxial layer; a channel, an N + type source region 6 and a P + channel substrate contact 5 are formed in each P type base region 7, wherein the N + type source region 6 is adjacent to the channel, and the P + channel substrate contact 5 is positioned at the far end of the channel relative to the N + type source region 6; the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and a channel is still positioned in the silicon epitaxial layer;
the gate oxide layer covers the part of the N-type silicon epitaxial layer between the two P-type base regions 7 and the corresponding two channels;
the grid 3 is positioned on the upper surface of the grid oxide layer;
and the drain electrode 9 is positioned on the lower surface of the N + type substrate 801.
Taking an N-channel VDMOS as an example, the preparation method can specifically comprise the following steps:
1) forming the N-type wide band gap epitaxial layer 802 on the upper surface of an N + type substrate 801 made of a wide band gap semiconductor material; the wide band gap semiconductor material adopts silicon carbide or gallium nitride, and the doping concentration of the N-type wide band gap epitaxial layer 802 is (10)14‐1016)cm‐3The doping concentration of the N-type wide band gap epitaxial layer 802 is 4-6 orders of magnitude smaller than that of the N + type substrate 801;
2) growing an N-type silicon epitaxial layer by a heteroepitaxial growth technology; the N-type silicon epitaxial layer is a thin layer of 1-6 microns, and the part of the P-type base region extending into the wide band gap N-type epitaxial layer is not more than two thirds;
3) forming a metalized drain on the lower surface of the N + type substrate 801;
4) forming a P-type base region 7, an N + type source region 6 and a P + channel substrate contact 5 in the left and right end regions of the upper part of the N-type silicon epitaxial layer by adopting ion implantation, and forming a corresponding channel by adopting a double diffusion technology to ensure that the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and the channel is still positioned in the silicon epitaxial layer;
5) forming a gate oxide layer on the upper surface of the whole N-type silicon epitaxial layer, depositing polycrystalline silicon, etching the polycrystalline silicon and removing the parts of the gate oxide layer, which are positioned in the left end region and the right end region, so as to form a polycrystalline silicon gate;
6) depositing a passivation layer on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
7) and depositing metal in the contact hole, etching to remove the rest passivation layer on the periphery to form a source electrode, and connecting the two source electrodes together.
ISE TCAD simulation shows that the device has improved performance compared with the traditional silicon-based VDMOS, and the breakdown voltage of the device is improved by 2-3 times compared with the traditional silicon-based VDMOS under the conditions that the lengths of the drift regions of the two devices are the same and the doping concentration of the drift regions is the same.
The VDMOS in the present invention may also be a P-channel VDMOS, and the structure of the VDMOS is equivalent to that of an N-channel VDMOS, and the VDMOS is also considered to belong to the protection scope of the claims of the present application, and the details are not described herein again.
Claims (10)
1. A vertical double-diffused metal oxide semiconductor field effect transistor with a wide band gap material and silicon material composite comprises:
an N + type substrate (801) of wide bandgap semiconductor material;
an N-type epitaxial layer of a wide band gap semiconductor material formed on the upper surface of an N + type substrate (801) and marked as an N-type wide band gap epitaxial layer (802);
an N-type silicon epitaxial layer which is heteroepitaxially grown or formed by utilizing a bonding technology is formed on the upper surface of the N-type wide band gap epitaxial layer (802);
two P-type base regions (7) respectively formed in the left and right end regions of the upper part of the N-type silicon epitaxial layer; a channel, an N + type source region (6) and a P + channel substrate contact (5) are formed in each P type base region (7), wherein the N + type source region (6) is adjacent to the channel, and the P + channel substrate contact (5) is positioned at the far end of the channel relative to the N + type source region (6); the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and a channel is still positioned in the silicon epitaxial layer;
the gate oxide layer (2) is formed in the middle area of the upper surface of the N-type silicon epitaxial layer and covers the part, located between the two P-type base regions (7), of the N-type silicon epitaxial layer and the corresponding two channels;
the grid (3) is positioned on the upper surface of the gate oxide layer;
source electrodes (1, 4) covering the upper surface of a region where the P + channel substrate contact (5) and the N + type source region (6) are connected; two source electrodes (1, 4) are connected together;
the drain electrode (9) is positioned on the lower surface of the N + type substrate (801);
the thickness and the doping concentration of the N-type wide band gap epitaxial layer are determined by the voltage-resistant requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer is lower than that of the N + type substrate (801).
2. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the wide band gap semiconductor material adopts silicon carbide or gallium nitride.
3. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the doping concentration of the N-type wide band gap epitaxial layer (802) is 4-6 orders of magnitude less than that of the N + type substrate (801).
4. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the N-type silicon epitaxial layer is a thin layer of 1-6 microns, and the part of the P-type base region extending into the wide-band-gap N-type epitaxial layer is not more than two thirds.
5. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: when the withstand voltage requirement is 900V, the thickness of the N-type wide band gap epitaxial layer (802) is 17 microns.
6. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the doping concentration of the N-type wide band gap epitaxial layer (802) is (10)14-1016)cm-3。
7. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the P-type base region (7), the N + type source region (6) thereof, the P + channel substrate contact (5) and the channel are formed on the upper part of the N-type silicon epitaxial layer by adopting ion implantation and double diffusion technology.
8. The composite vertical double-diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, wherein: the grid (3) is a polysilicon grid, the source electrodes (1 and 4) are metalized source electrodes, and the drain electrode (9) is a metalized drain electrode.
9. A method for fabricating the vertical double diffused metal oxide semiconductor field effect transistor with wide band gap material and silicon material of claim 1, comprising the steps of:
(1) forming the N-type wide band gap epitaxial layer (802) on the upper surface of an N + type substrate (801) of wide band gap semiconductor material;
(2) growing an N-type silicon epitaxial layer by a heteroepitaxial growth technology;
(2) forming a metalized drain on the lower surface of an N + type substrate (801);
(3) forming a P-type base region (7) and an N + type source region (6) thereof and a P + channel substrate contact (5) in the left and right end regions of the upper part of the N-type silicon epitaxial layer by adopting ion implantation, and forming a corresponding channel by adopting a double diffusion technology to ensure that the longitudinal boundary of the P-type base region extends into the wide band gap N-type epitaxial layer, namely a PN junction formed by the P-type base region and the N-type wide band gap epitaxial layer is positioned in the N-type wide band gap epitaxial layer, and the channel is still positioned in the silicon epitaxial layer;
(4) forming a gate oxide layer on the upper surface of the whole N-type silicon epitaxial layer, depositing polycrystalline silicon, and etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate;
(5) depositing a passivation layer on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(6) and depositing metal in the contact hole and etching to form a source electrode, and connecting the two source electrodes together.
10. The method of claim 9, wherein: the wide band gap semiconductor material adopts silicon carbide or gallium nitride.
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| CN201710157056.1A CN107123684B (en) | 2017-03-16 | 2017-03-16 | Vertical double-diffusion metal oxide semiconductor field effect transistor with wide band gap material and silicon material composite |
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| CN108511528B (en) * | 2018-04-11 | 2020-11-06 | 西安电子科技大学 | Transverse double-diffusion metal oxide composite semiconductor field effect transistor with deep drain region and manufacturing method thereof |
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