CN108258040B - Insulated gate bipolar transistor with wide band gap semiconductor substrate material and manufacturing method thereof - Google Patents
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- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
The invention provides an Insulated Gate Bipolar Transistor (IGBT) with wide-band-gap semiconductor substrate material and a manufacturing method thereof. The IGBT device is mainly characterized in that a wide band gap semiconductor material is combined with a silicon semiconductor material, and the wide band gap semiconductor material is used as an anode and a substrate of the IGBT device. The method comprises the steps of firstly forming an N + type wide bandgap semiconductor material buffer layer with higher doping concentration on a wide bandgap semiconductor material P + type substrate, further forming an N type wide bandgap semiconductor material epitaxial layer with lower doping concentration on the N + type wide bandgap buffer layer, then combining the N type wide bandgap semiconductor epitaxial layer with an N type silicon semiconductor layer by using a crystal bonding technology on the basis of the N type wide bandgap semiconductor epitaxial layer, and forming an active region of an IGBT device on the silicon bonding layer through a silicon mature process. The invention can obviously improve the breakdown voltage of the IGBT and improve the performance of the device.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to an Insulated Gate Bipolar Transistor (IGBT) and a manufacturing method thereof.
Background
The power semiconductor device is a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. Insulated Gate Bipolar Transistors (IGBTs) are important components in the field of power semiconductor devices, and have been widely used in power integrated circuits and power integrated systems due to their excellent characteristics of low on-resistance, reduced saturation voltage, high current handling capability, low loss, high input impedance, low driving power, and fast switching speed. In recent years, the characteristic optimization of the IGBT device is mainly to research the mature super junction process to realize the IGBT device with the super junction.
Disclosure of Invention
The invention provides a novel insulated gate bipolar transistor power device, and aims to further improve the breakdown voltage of an IGBT and improve the performance of the device.
The technical scheme of the invention is as follows:
the insulated gate bipolar transistor with the wide band gap substrate material comprises:
a P + type substrate of wide bandgap semiconductor material;
an N + type buffer layer made of wide band gap semiconductor materials is epitaxially grown on the upper surface of the P + type substrate and is marked as an N + type wide band gap buffer layer;
an N-type epitaxial layer of a wide band gap semiconductor material is epitaxially grown on the upper surface of the N + type wide band gap buffer layer and is marked as an N-type wide band gap epitaxial layer;
combining an N-type bonding layer of a silicon material on the upper surface of the N-type wide band gap epitaxial layer by utilizing a crystal bonding technology, and marking as the N-type silicon bonding layer;
two P-type base regions are respectively formed in the left end region and the right end region of the upper part of the N-type silicon bonding layer; a channel and an N + type source region are formed in each P type base region and are contacted with a P + channel substrate, wherein the N + type source region is adjacent to the channel, and the P + channel substrate contact is positioned at the far end of the channel relative to the N + type source region;
the gate oxide layer is positioned between the two P-type base regions and on the upper surfaces of part of the N + type source region and the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer;
the grid is positioned inside the grid oxide layer;
the source electrode covers the upper surface of a region where the corresponding P + channel substrate contact is connected with the N + type source region, and the two source electrodes are connected together;
the drain electrode is positioned on the lower surface of the P + type substrate;
the thickness and the doping concentration of the N-type wide band gap epitaxial layer are determined by the voltage-resistant requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer is lower than the doping concentrations of the N + type wide band gap buffer layer and the P + type substrate.
On the basis of the scheme, the invention further optimizes the following steps:
the wide band gap semiconductor material is silicon carbide, gallium nitride or diamond.
The difference value of the doping concentration of the N-type wide band gap epitaxial layer compared with the P + type substrate is determined according to the designed breakdown voltage, and is generally smaller than the doping concentration of the P + type substrate by 4-6 orders of magnitude and smaller than the doping concentration of the N + type wide band gap buffer layer by 2-4 orders of magnitude.
The doping concentration of the N-type wide band gap epitaxial layer is generally (10)14-1016)cm-3。
The thickness and doping concentration of the N-type wide band gap epitaxial layer are determined according to the designed breakdown voltage, for example: the doping concentration of the P + type substrate is 1 x 1020cm-3The doping concentration of the N + type wide band gap buffer layer is 1 multiplied by 1018cm-3(ii) a The voltage resistance requirement is 360V, the thickness of the N type wide band gap epitaxial layer is 5 microns, and the doping concentration of the N type wide band gap epitaxial layer and the N type silicon bonding layer is 1 multiplied by 1015cm-3(ii) a The voltage resistance requirement is 510V, the thickness of the N type wide band gap epitaxial layer is 14 microns, and the doping concentration of the N type wide band gap epitaxial layer and the N type silicon bonding layer is 2 multiplied by 1015cm-3(ii) a The withstand voltage requirement is 720V, the thickness of the N type wide band gap epitaxial layer is 14 microns, and the doping concentration of the N type wide band gap epitaxial layer and the N type silicon bonding layer is 1 multiplied by 1015cm-3。
The P-type base region, the N + type source region of the P-type base region, the P + channel substrate contact and the channel are formed on the upper portion of the N-type silicon bonding layer through ion implantation and double diffusion technologies.
The grid is a polysilicon grid, the source electrode is a metalized source electrode, and the drain electrode is a metalized drain electrode.
A method of fabricating an insulated gate bipolar transistor having a wide bandgap substrate material as described above, comprising the steps of:
(1) preparing a P + type wide band gap semiconductor material as a P + type substrate;
(2) epitaxially growing an N + type wide band gap buffer layer on the upper surface of the P + type substrate of the wide band gap semiconductor material;
(3) epitaxially growing an N-type wide band gap epitaxial layer on the upper surface of the N + type wide band gap buffer layer;
(4) combining an N-type silicon bonding layer on the upper surface of the N-type wide band gap epitaxial layer by using a room-temperature crystal bonding technology, and performing high-temperature annealing after bonding;
(5) oxidizing the upper surface of the N-type silicon bonding layer to form a silicon dioxide film, and etching the silicon dioxide film by adopting an anisotropic etching method under the protection of a mask to form an active region;
(6) further forming a gate oxide layer on the upper surface of the N-type silicon bonding layer, depositing polycrystalline silicon, etching the polycrystalline silicon and the gate oxide layer, and removing parts positioned in the left end region and the right end region to form a polycrystalline silicon grid;
(7) forming a P-type base region in the left end region and the right end region of the upper part of the N-type silicon bonding layer through boron ion implantation and double diffusion technology, performing a well pushing process, and finally depending on the temperature and time of a well pushing process;
(8) forming a heavily doped N + source region to be contacted with the P + channel substrate in an ion implantation mode, forming a corresponding channel by adopting a double diffusion technology, and shortening annealing time as much as possible after implantation;
(9) depositing a silicon oxide film on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(10) depositing metal in the contact hole and etching to remove the rest silicon oxide film on the periphery to form a source electrode, and connecting the two source electrodes together;
(11) and forming a metalized drain on the lower surface of the P + type substrate.
The technical scheme of the invention has the following beneficial effects:
the IGBT device substrate adopts a wide band gap material, an N + type wide band gap buffer layer with higher doping concentration is formed on the upper surface of a wide band gap P + type substrate material, an N type wide band gap epitaxial layer with lower doping concentration is formed on the upper surface of the N + type wide band gap buffer layer, the N type wide band gap epitaxial layer is combined with an N type silicon bonding layer by using a crystal bonding technology on the basis of the N type wide band gap epitaxial layer, and a device active region is formed on the silicon bonding layer by adopting a silicon mature process. The longitudinal electric field generated in the wide band gap material (when the device is in an off state and resists voltage) is used for modulating the longitudinal electric field in the silicon bonding layer, so that the longitudinal electric field of the device is integrally raised, the breakdown voltage is increased, the breakdown voltage can be increased by over 71 percent compared with the traditional silicon-based IGBT under the conditions that the drift region of the device is the same in thickness and the doping concentration of the drift region is the same and lower, meanwhile, the high thermal conductivity of the wide band gap material is beneficial to heat dissipation of the device, and the performance of the device is effectively improved.
Drawings
FIGS. 1-11 are schematic device fabrication flow diagrams of one embodiment of the present invention;
fig. 12 is a schematic structural diagram of an IGBT device according to an embodiment of the present invention.
Wherein, 101-source electrode; 102-a gate oxide layer; 103-a gate; 104-source; 105-P + channel substrate contacts (P + type body regions); a 106-N + type source region; 107-P type base region; 801-P + type substrate of wide band gap semiconductor material; an 802-N + type wide band gap buffer layer; 803-N type wide band gap epitaxial layer; 804-an N-type silicon bonding layer; 108-drain.
Detailed Description
The present invention will be described below by taking an N-channel IGBT as an example with reference to the accompanying drawings.
As shown in fig. 1 to 11, the device can be specifically prepared by the following steps:
(1) preparing a P + -type wide band gap semiconductor material as a P + -type substrate 801 as shown in fig. 1;
(2) epitaxially growing an N + type wide band gap buffer layer 802 on the upper surface of the P + type substrate 801 of the wide band gap semiconductor material, as shown in fig. 2;
(3) an N-type wide band gap epitaxial layer 803 is epitaxially grown on the upper surface of the N + type wide band gap buffer layer 802, as shown in fig. 3. The wide band gap semiconductor material adopts silicon carbide, gallium nitride or diamond, and the doping concentration of the N-type wide band gap epitaxial layer 802 is (10)14-1016)cm-3The doping concentration of the N-type wide band gap epitaxial layer 803 is 4-6 orders of magnitude smaller than that of the P + type substrate 801 and 2-4 orders of magnitude smaller than that of the N + type wide band gap buffer layer 802;
(4) on the upper surface of the N-type wide band gap epitaxial layer 803, an N-type silicon epitaxial layer 804 is combined by a room temperature crystal bonding technique, and high temperature annealing is performed after bonding is completed, as shown in fig. 4.
(5) And oxidizing the upper surface of the N-type silicon bonding layer 804 to form a silicon dioxide film, and etching the silicon dioxide film by using an anisotropic etching method under the protection of a mask to form an active region (not shown in the figure), as shown in fig. 5.
(6) A gate oxide layer 102 is further formed on the upper surface of the N-type silicon bonding layer 804, polysilicon is deposited, then the polysilicon and the gate oxide layer are etched, and portions located at the left and right end regions are removed to form a polysilicon gate 103, as shown in fig. 6.
(7) Forming a P-type base region 107 in the left and right end regions of the upper part of the N-type silicon bonding layer 804 by using boron ion implantation and double diffusion technology, and performing a well pushing process, wherein the junction depth finally depends on the temperature and time of the well pushing process, as shown in fig. 7.
(8) Heavily doped N + source regions 106 and P + channel substrate contacts 105 are further formed by ion implantation, and the corresponding channels (not shown) are formed by a double diffusion technique, and the annealing time after the implantation is completed is as short as possible, as shown in fig. 8.
(9) A silicon oxide film is deposited on the surface of the device and contact holes are etched at locations corresponding to the source electrodes, as shown in fig. 9.
(10) Metal is deposited in the contact holes and etched to remove the remaining silicon oxide film on the periphery, thereby forming source electrodes 101 and 104, and connecting the two source electrodes together (not shown), as shown in fig. 10.
(11) A metalized drain 108 is formed on the bottom surface of the P + type substrate 801 as shown in fig. 11.
As shown in fig. 12, the structure of the device mainly comprises:
a P + type substrate 801 of wide bandgap semiconductor material;
an N + type buffer layer of wide band gap semiconductor material formed by epitaxial growth on the upper surface of a P + type substrate 801 of wide band gap semiconductor material is marked as an N + type wide band gap buffer layer 802;
an N-type epitaxial layer of a wide band gap semiconductor material epitaxially grown on the upper surface of the N + type wide band gap buffer layer 802 is denoted as an N-type wide band gap epitaxial layer 803;
an N-type bonding layer of silicon material is bonded on the upper surface of the N-type wide band gap epitaxial layer 803 by using a crystal bonding technology, and is marked as an N-type silicon bonding layer 804;
two P-type base regions 107 formed in the left and right end regions of the upper portion of the N-type silicon bonding layer, respectively; a channel, an N + type source region 106 and a P + channel substrate contact 105 are formed in each P type base region 107, wherein the N + type source region 106 is adjacent to the channel, and the P + channel substrate contact 105 is positioned at the far end of the channel relative to the N + type source region 106;
the gate oxide layer 102 is positioned between the two P-type base regions 107 and on the upper surfaces of part of the N + type source region 106 and the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer;
a gate 103 located inside the gate oxide layer;
and the drain electrode 108 is positioned on the lower surface of the P + type substrate 801.
Compared with the traditional silicon-based IGBT device, the IGBT device combines the wide band gap semiconductor material with the silicon semiconductor material, and uses the wide band gap semiconductor material as part of the drift region, the buffer layer and the substrate of the IGBT device.
ISE TCAD simulation shows that the performance of the device is improved compared with that of the traditional silicon-based IGBT, and the breakdown voltage of the device is improved by over 71 percent under the conditions that the thicknesses of drift regions of two devices are the same and the doping concentration of the drift regions is the same and lower.
The IGBT of the present invention may also be a P-type channel, and its structure is equivalent to the above-mentioned N-channel IGBT, and should also be considered as belonging to the protection scope of the claims of the present application, and is not described herein again.
The material extending over the wide band gap semiconductor material in the present invention is a silicon semiconductor material, and should be understood in a broad sense, that is, other element semiconductor materials such as germanium and the like and the wide band gap semiconductor form an IGBT which is equivalent to the IGBT described in the present invention, and should also be considered as belonging to the protection scope of the claims of the present application, and the details thereof are not described herein again.
Claims (7)
1. An insulated gate bipolar transistor having a wide bandgap semiconductor substrate material, comprising:
a P + type substrate (801) of wide bandgap semiconductor material;
an N + type buffer layer made of wide band gap semiconductor materials is epitaxially grown on the upper surface of the P + type substrate (801), and is marked as an N + type wide band gap buffer layer (802);
an N-type epitaxial layer made of a wide band gap semiconductor material is epitaxially grown on the upper surface of the N + type wide band gap buffer layer (802), and is marked as an N-type wide band gap epitaxial layer (803);
an N-type bonding layer of silicon materials is bonded on the upper surface of the N-type wide band gap epitaxial layer (803) by utilizing a crystal bonding technology and is marked as an N-type silicon bonding layer (804);
two P-type base regions (107) are respectively formed in the left end region and the right end region of the upper part of the N-type silicon bonding layer (804); forming a channel in each P-type base region (107), and an N + type source region (106) and a P + channel substrate contact (105), wherein the N + type source region (106) is adjacent to the channel, and the P + channel substrate contact (105) is located at a far end of the channel relative to the N + type source region (106);
the gate oxide layer (102) is positioned between the two P-type base regions (107), part of the N + type source region (106) and the upper surface of the corresponding channel, and the middle part of the gate oxide layer covers the upper surface of the N-type silicon bonding layer (804);
a gate (103) located inside the gate oxide layer;
two source electrodes (101, 104) covering the upper surface of the region where the corresponding P + channel substrate contact (105) and the N + type source region (106) are connected, wherein the two source electrodes (101, 104) are connected together;
a drain (108) located on a lower surface of the P + type substrate (801);
the thickness and the doping concentration of the N-type wide band gap epitaxial layer (803) are determined by the voltage withstanding requirement of the device, and the doping concentration of the N-type wide band gap epitaxial layer (803) is lower than the doping concentrations of the N + type wide band gap buffer layer (802) and the P + type substrate (801); the method specifically comprises the following steps: the doping concentration of the N-type wide band gap epitaxial layer (803) is (10)14-1016)cm-3The doping concentration of the P + type substrate (801) is 1X 1020cm-3The doping concentration of the N + type wide band gap buffer layer (802) is 1 multiplied by 1018cm-3。
2. The insulated gate bipolar transistor having a wide bandgap semiconductor substrate material of claim 1, wherein: the wide band gap semiconductor material is silicon carbide, gallium nitride or diamond.
3. The insulated gate bipolar transistor having a wide bandgap semiconductor substrate material of claim 1, wherein: when the withstand voltage is required to be 360V, the thickness of the N-type wide band gap epitaxial layer (803) is 5 μm, and the doping concentration of the N-type wide band gap epitaxial layer (803) and the N-type silicon bonding layer (804) is 1X 1015cm-3；
When the withstand voltage requirement is 510V, the thickness of the N-type wide band gap epitaxial layer (803) is 14 μm, and the doping concentration of the N-type wide band gap epitaxial layer (803) and the N-type silicon bonding layer (804) is 2X 1015cm-3；
When the withstand voltage requirement is 720V, the thickness of the N-type wide band gap epitaxial layer (803) is 14 μm, and the doping concentration of the N-type wide band gap epitaxial layer (803) and the N-type silicon bonding layer (804) is 1X 1015cm-3。
4. The insulated gate bipolar transistor having a wide bandgap semiconductor substrate material of claim 1, wherein: the P-type base region (107) and the N + type source region (106) thereof, the P + channel substrate contact (105) and the channel are formed on the upper part of the N-type silicon bonding layer (804) by ion implantation and double diffusion technology.
5. The insulated gate bipolar transistor having a wide bandgap semiconductor substrate material of claim 1, wherein: the gate (103) is a polysilicon gate, the sources (101, 104) are metalized sources, and the drain (108) is a metalized drain.
6. A method of fabricating the insulated gate bipolar transistor having a wide bandgap semiconductor substrate material of claim 1, comprising the steps of:
(1) preparing a P + type wide band gap semiconductor material as a P + type substrate (801);
(2) epitaxially growing an N + type wide band gap buffer layer (802) on the upper surface of the P + type substrate (801) made of the wide band gap semiconductor material;
(3) epitaxially growing an N-type wide band gap epitaxial layer (803) on the upper surface of the N + type wide band gap buffer layer (802);
(4) combining an N-type silicon bonding layer (804) on the upper surface of the N-type wide band gap epitaxial layer (803) by a room temperature crystal bonding technology, and performing high-temperature annealing after bonding;
(5) oxidizing the upper surface of the N-type silicon bonding layer (804) to form a silicon dioxide film, and etching the silicon dioxide film by adopting an anisotropic etching method under the protection of a mask to form an active region;
(6) further forming a gate oxide layer (102) on the upper surface of the N-type silicon bonding layer (804), depositing polycrystalline silicon, etching the polycrystalline silicon and the gate oxide layer, removing parts located at the left end region and the right end region, and forming a polycrystalline silicon gate (103);
(7) forming a P-type base region (107) in the left end region and the right end region of the upper part of the N-type silicon bonding layer (804) through boron ion implantation, performing a well pushing process, and finally enabling junction depth to depend on the temperature and time of a well pushing process;
(8) forming a heavily doped N + source region (106) and a P + channel substrate contact (105) in an ion implantation mode, forming a corresponding channel by adopting a double diffusion technology, and annealing after the implantation is finished;
(9) depositing a silicon oxide film on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
(10) depositing metal in the contact hole and etching to remove the rest silicon oxide film on the periphery to form source electrodes (101, 104), and connecting the two source electrodes together;
(11) a metalized drain is formed on the lower surface of a P + type substrate (801).
7. The method of claim 6, wherein: the wide band gap semiconductor material is silicon carbide, gallium nitride or diamond.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201711436190.1A CN108258040B (en) | 2017-12-26 | 2017-12-26 | Insulated gate bipolar transistor with wide band gap semiconductor substrate material and manufacturing method thereof |
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| CN102017159A (en) * | 2008-09-12 | 2011-04-13 | 住友电气工业株式会社 | Silicon carbide semiconductor device and process for producing the silicon carbide semiconductor device |
| CN104064587A (en) * | 2013-03-22 | 2014-09-24 | 株式会社东芝 | Semiconductor Device And Method Of Manufacturing Same |
| CN107086243A (en) * | 2017-03-16 | 2017-08-22 | 西安电子科技大学 | The U MOSFET being combined with wide bandgap material and silicon materials |
| CN107093623A (en) * | 2017-03-16 | 2017-08-25 | 西安电子科技大学 | A kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor with broad-band gap backing material |
| CN107123684A (en) * | 2017-03-16 | 2017-09-01 | 西安电子科技大学 | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor |
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| CN102017159A (en) * | 2008-09-12 | 2011-04-13 | 住友电气工业株式会社 | Silicon carbide semiconductor device and process for producing the silicon carbide semiconductor device |
| CN104064587A (en) * | 2013-03-22 | 2014-09-24 | 株式会社东芝 | Semiconductor Device And Method Of Manufacturing Same |
| CN107086243A (en) * | 2017-03-16 | 2017-08-22 | 西安电子科技大学 | The U MOSFET being combined with wide bandgap material and silicon materials |
| CN107093623A (en) * | 2017-03-16 | 2017-08-25 | 西安电子科技大学 | A kind of vertical double-diffusion metal-oxide-semiconductor field effect transistor with broad-band gap backing material |
| CN107123684A (en) * | 2017-03-16 | 2017-09-01 | 西安电子科技大学 | One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor |
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