CN107123684A - One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor - Google Patents

One kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor Download PDF

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CN107123684A
CN107123684A CN201710157056.1A CN201710157056A CN107123684A CN 107123684 A CN107123684 A CN 107123684A CN 201710157056 A CN201710157056 A CN 201710157056A CN 107123684 A CN107123684 A CN 107123684A
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wide bandgap
band gap
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epitaxial layer
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CN107123684B (en
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段宝兴
吕建梅
袁嵩
曹震
杨银堂
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Xidian University
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors

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Abstract

The present invention, which proposes one kind, has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor (VDMOS), the VDMOS device is mainly characterized by wide bandgap material being combined with silicon materials, the less N-type broad-band gap epitaxial layer of doping concentration is formed in wide bandgap N+type backing material upper surface, heteroepitaxial growth (or being formed using bonding techniques) N-type silicon epitaxy layer based on the N-type broad-band gap epitaxial layer, device active region is formed using silicon maturation process again.Utilize the high critical breakdown electric field characteristic of wide bandgap material, the high electric field peak of device is introduced into wide bandgap material, the longitudinal electric field peak of device is raised, device can undertake higher breakdown voltage, device electric breakdown strength is breached to be limited by single silicon materials critical breakdown electric field, the high heat conductance characteristic of wide bandgap material is conducive to device to radiate simultaneously, effectively improves device performance.

Description

One kind has wide bandgap material and silicon materials complex vertical bilateral diffusion metal oxide half Conductor FET
Technical field
The present invention relates to power semiconductor field, more particularly to a kind of vertical bilateral diffusion metallic oxide field-effect Pipe.
Background technology
Power semiconductor refers to be mainly used in the high-power electricity in terms of the transformation of electrical energy and control circuit of power equipment Sub- device.With developing rapidly for Power Electronic Technique, power semiconductor have been widely used for modern industry control and In defence equipment.Vertical double-diffused MOS field-effect transistor (VDMOS, Vertical Double- Diffusion Metal Oxide Semiconductor) so that its switching speed is fast, the small, input impedance of loss is high, driving power The characteristics such as small, frequency characteristic is good, mutual conductance high linearity height are usually used in power integrated circuit and power integrated system.
In recent years, it is mainly the ripe superjunction technique of research to the characteristic optimizing of VDMOS device to realize with superjunction VDMOS device.
The content of the invention
The present invention proposes a kind of new vertical double diffusion metal oxide semiconductor power device, it is intended to further improve VDMOS breakdown voltage, improves device performance.
Technical scheme is as follows：
Should have wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor, including：
The N+ type substrates of wide bandgap semiconductor materials；
In the N-type epitaxy layer of the wide bandgap semiconductor materials of N+ types substrate top surface formation, N-type broad-band gap extension is designated as Layer；
In the N-type broad-band gap epitaxial layer upper surface heteroepitaxial growth or the N-type silicon epitaxy using bonding techniques formation Layer (using the normally referred to as bonded layer of bonding techniques formation, is uniformly designated as N-type silicon epitaxy layer) herein；
Respectively the N-type silicon epitaxy layer top left and right two end regions formation two at p-type base；Everywhere p-type base Raceway groove and N+ types source region and the contact of P+ channeled substrates are formed in area, wherein N+ types source region is abutted with raceway groove, and P+ channeled substrates connect Touch and be located at raceway groove distal end relative to N+ types source region；The longitudinal boundary of the p-type base is extended into wide bandgap N type epitaxial layer, i.e. P Type base and the PN junction of N-type broad-band gap epitaxial layer formation are located in N-type broad-band gap epitaxial layer, and raceway groove is still located in silicon epitaxy layer；
Gate oxide, covers the N-type silicon epitaxy layer and is located at ditch at the part and corresponding two at two between p-type base Road；
Grid, positioned at gate oxide upper surface；
Source electrode, covering P+ channeled substrates contact the upper surface in the region that connects with N+ type source regions；Source electrode connects altogether at two；
Drain electrode, positioned at the N+ types substrate lower surface；
The thickness and doping concentration of the N-type broad-band gap epitaxial layer determines by the resistance to pressure request of device, N-type broad-band gap extension The doping concentration of layer is less than the doping concentration of N+ type substrates.
On the basis of above scheme, the present invention has also further made following optimization：
Above-mentioned wide bandgap semiconductor materials use carborundum or gallium nitride.
The doping concentration of above-mentioned N-type broad-band gap epitaxial layer is determined according to the breakdown voltage of design, compared with N+ type substrates Difference is the about 4-6 order of magnitude.
Above-mentioned N-type silicon epitaxy layer is thin layer (about in 1-6 microns), and p-type base stretches into wide bandgap N type epitaxial layer Part is no more than 2/3rds.
Above-mentioned broad-band gap epitaxy layer thickness is determined according to the breakdown voltage of design.For example, when it is pressure-resistant be 900V when, broad-band gap Epitaxy layer thickness is 17 microns.
The doping concentration of above-mentioned N-type broad-band gap epitaxial layer is determined according to the breakdown voltage of design, is generally (1014‐1016) cm‐3
Aforementioned p-type base and its N+ types source region and the contact of P+ channeled substrates and raceway groove, are adopted on N-type silicon epitaxy layer top Formed with ion implanting and double diffusion technique.
Above-mentioned grid is polysilicon gate, and the source electrode is metallizing source, is drained as metalized drain.
One kind making is above-mentioned, and there is wide bandgap material to be imitated with silicon materials complex vertical double-diffused metal oxide semiconductor Should pipe method, comprise the following steps：
(1) the N-type broad-band gap epitaxial layer is formed in the upper surface of the N+ type substrates of wide bandgap semiconductor materials；
(2) heteroepitaxial growth technology growth N-type silicon epitaxy layer is passed through；
(2) in N+ type substrates lower surface formation metalized drain；
(3) left and right two end regions on N-type silicon epitaxy layer top use ion implanting formation p-type base and its N+ types source Area and the contact of P+ channeled substrates, and corresponding raceway groove is formed using double diffusion technique, it is ensured that the longitudinal boundary of p-type base is extended into In wide bandgap N type epitaxial layer, i.e. p-type base and the PN junction of N-type broad-band gap epitaxial layer formation is located in N-type broad-band gap epitaxial layer, Raceway groove is still located in silicon epitaxy layer；
(4) form gate oxide in whole N-type silicon epitaxy layer upper surface, and depositing polysilicon, then etches polycrystalline silicon with And gate oxide (removing positioned at the part of left and right two end regions), form polysilicon gate；
(5) passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
(6) metal is deposited in contact hole and (remove remaining passivation layer of periphery) is etched and forms source electrode, and by source at two Extremely connect altogether.
Technical solution of the present invention has the beneficial effect that：
The substrate of VDMOS device uses wide bandgap material, and doping concentration is formed in wide bandgap N+type backing material upper surface Less N-type broad-band gap epitaxial layer, then by heterogeneous epitaxial technology (or bonding techniques) formation N-type silicon epitaxy layer, using silicon into Ripe technique making devices active area.The high electric field peak that wherein p-type base/N-type broad-band gap epitaxial layer knot is produced is located at broad-band gap material In material, the characteristics of critical breakdown electric field high using wide bandgap material, the longitudinal electric field peak of device is raised, device can undertake higher Breakdown voltage, breach traditional silicon substrate VDMOS breakdown voltages and limited by single silicon materials critical breakdown electric field, device drift Move in the case of section length, drift region concentration identical, 2-3 times is improved than traditional VDMOS breakdown voltages.While broad-band gap material The high heat conductance characteristic of material is conducive to device to radiate, and effectively improves device performance.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention.
Wherein, 1- source electrodes；2- gate oxides；3- grids；4- source electrodes；5-P+ channeled substrates contact (P+ type body area)；6‐N+ Type source region；7-P types base；The N+ type substrates of 801- wide bandgap materials；802-N molded breadth band gap epitaxial layers；9- drains.
Embodiment
The present invention is introduced by taking N-channel VDMOS as an example below in conjunction with the accompanying drawings.
As shown in figure 1, this example includes：
The N+ types substrate 801 of wide bandgap semiconductor materials；
The N-type epitaxy layer of the wide bandgap semiconductor materials formed in the upper surface of N+ types substrate 801, is designated as outside N-type broad-band gap Prolong layer 802；
Outside the upper surface heteroepitaxial growth of N-type broad-band gap epitaxial layer 802 or the N-type silicon of utilization bonding techniques formation Prolong layer；
Respectively the N-type silicon epitaxy layer top left and right two end regions formation two at p-type base 7；Everywhere p-type Raceway groove and N+ types source region 6 and P+ channeled substrates contact 5 are formed in base 7, wherein N+ types source region 6 is abutted with raceway groove, P+ raceway grooves Substrate contact 5 is located at raceway groove distal end relative to N+ types source region 6；The longitudinal boundary of the p-type base extends into wide bandgap N type extension In layer, i.e. p-type base and the PN junction of N-type broad-band gap epitaxial layer formation is located in N-type broad-band gap epitaxial layer, and raceway groove is still located at outside silicon Prolong in layer；
Gate oxide, covers the N-type silicon epitaxy layer and is located at the part and corresponding two at two between p-type base 7 Raceway groove；
Grid 3, positioned at gate oxide upper surface；
Source electrode 1,4, covering P+ channeled substrates contact 5 connects the upper surface in region with N+ types source region 6；Source electrode 1,4 is total at two Connect；
Drain electrode 9, positioned at the lower surface of N+ types substrate 801.
By taking N-channel VDMOS as an example, it can specifically be prepared by following steps：
1) the N-type broad-band gap epitaxial layer 802 is formed in the upper surface of the N+ types substrate 801 of wide bandgap semiconductor materials； Wide bandgap semiconductor materials use carborundum or gallium nitride, and the doping concentration of N-type broad-band gap epitaxial layer 802 is (1014‐1016) cm‐3, the doping concentration small 4-6 order of magnitude of the doping concentration than N+ types substrate 801 of N-type broad-band gap epitaxial layer 802；
2) heteroepitaxial growth technology growth N-type silicon epitaxy layer is passed through；N-type silicon epitaxy layer is 1-6 microns of thin layer, p-type The part that base stretches into wide bandgap N type epitaxial layer is no more than 2/3rds；
3) in the lower surface of N+ types substrate 801 formation metalized drain；
4) left and right two end regions on N-type silicon epitaxy layer top use ion implanting formation p-type base 7 and its N+ types source Area 6 and P+ channeled substrates contact 5, and corresponding raceway groove is formed using double diffusion technique, it is ensured that the longitudinal boundary extension of p-type base Enter in wide bandgap N type epitaxial layer, i.e. p-type base and the PN junction of N-type broad-band gap epitaxial layer formation is located at N-type broad-band gap epitaxial layer Interior, raceway groove is still located in silicon epitaxy layer；
5) form gate oxide in whole N-type silicon epitaxy layer upper surface, and depositing polysilicon, then etches polycrystalline silicon and Gate oxide is removed positioned at the part of left and right two end regions, forms polysilicon gate；
6) passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
7) metal is deposited in contact hole and removal remaining passivation layer of periphery formation source electrode is etched, and source electrode at two is total to Connect.
Show through ISE TCAD emulation, performance improvement of the device than traditional silicon substrate VDMOS, two kinds of device drift regions Length is identical, in the case of drift doping concentration identical, and the breakdown voltage of the device is improved compared to traditional silicon substrate VDMOS 2-3 times.
VDMOS in the present invention can also be P-type channel, and its structure is equal with N-channel VDMOS, is also regarded as belonging to The application scope of the claims, will not be repeated here.

Claims (10)

1. one kind has wide bandgap material and silicon materials complex vertical double-diffusion metal-oxide-semiconductor field effect transistor, including：
The N+ types substrate (801) of wide bandgap semiconductor materials；
The N-type epitaxy layer of the wide bandgap semiconductor materials formed in N+ types substrate (801) upper surface, is designated as N-type broad-band gap extension Layer (802)；
In N-type broad-band gap epitaxial layer (802) the upper surface heteroepitaxial growth or the N-type silicon epitaxy using bonding techniques formation Layer；
Respectively the N-type silicon epitaxy layer top left and right two end regions formation two at p-type base (7)；Everywhere p-type base Raceway groove and N+ types source region (6) and P+ channeled substrates contact (5) are formed in area (7), wherein N+ types source region (6) is abutted with raceway groove, P + channeled substrate contacts (5) and is located at raceway groove distal end relative to N+ types source region (6)；The longitudinal boundary of the p-type base extends into broadband In gap N-type epitaxy layer, i.e. p-type base and the PN junction of N-type broad-band gap epitaxial layer formation is located in N-type broad-band gap epitaxial layer, raceway groove It is still located in silicon epitaxy layer；
Gate oxide (2), covers the N-type silicon epitaxy layer and is located at the part and corresponding two at two between p-type base (7) Raceway groove；
Grid (3), positioned at gate oxide upper surface；
Source electrode (1,4), covering P+ channeled substrates contact (5) connects the upper surface in region with N+ types source region (6)；Source electrode at two (1, 4) connect altogether；
Drain (9), positioned at N+ types substrate (801) lower surface；
The thickness and doping concentration of the N-type broad-band gap epitaxial layer determines by the resistance to pressure request of device, N-type broad-band gap epitaxial layer Doping concentration is less than the doping concentration of N+ types substrate (801).
2. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：The wide bandgap semiconductor materials use carborundum or gallium nitride.
3. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：Doping concentration of the doping concentration of N-type broad-band gap epitaxial layer (802) than N+ types substrate (801) The small 4-6 order of magnitude.
4. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：N-type silicon epitaxy layer is 1-6 microns of thin layer, and p-type base stretches into wide bandgap N type epitaxial layer Part is no more than 2/3rds.
5. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：If resistance to pressure request is 900V, then N-type broad-band gap epitaxial layer (802) thickness is 17 microns.
6. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：The doping concentration of the N-type broad-band gap epitaxial layer (802) is (1014‐1016)cm‐3。
7. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：The p-type base (7) and its N+ types source region (6) and P+ channeled substrates contact (5) and ditch Road, is using ion implanting and double diffusion technique formation on N-type silicon epitaxy layer top.
8. according to claims 1 there is wide bandgap material partly to be led with silicon materials complex vertical bilateral diffusion metal oxide Body FET, it is characterised in that：The grid (3) is polysilicon gate, and the source electrode (1,4) is metallizing source, drain electrode (9) it is metalized drain.
9. it is a kind of make described in claim 1 there is wide bandgap material and silicon materials complex vertical bilateral diffusion metal oxide half The method of conductor FET, comprises the following steps：
(1) the N-type broad-band gap epitaxial layer (802) is formed in the upper surface of the N+ types substrate (801) of wide bandgap semiconductor materials；
(2) heteroepitaxial growth technology growth N-type silicon epitaxy layer is passed through；
(2) in N+ types substrate (801) lower surface formation metalized drain；
(3) left and right two end regions on N-type silicon epitaxy layer top use ion implanting formation p-type base (7) and its N+ type source regions (6) and P+ channeled substrates contact (5), and corresponding raceway groove is formed using double diffusion technique, it is ensured that the longitudinal boundary of p-type base prolongs Stretch into wide bandgap N type epitaxial layer, i.e. p-type base and the PN junction of N-type broad-band gap epitaxial layer formation is located at N-type broad-band gap epitaxial layer Interior, raceway groove is still located in silicon epitaxy layer；
(4) gate oxide, and depositing polysilicon are formed in whole N-type silicon epitaxy layer upper surface, then etches polycrystalline silicon and grid Oxide layer, forms polysilicon gate；
(5) passivation layer is deposited in device surface, and contact hole is etched in the position corresponding to source electrode；
(6) metal is deposited in contact hole and is etched and forms source electrode, and source electrode at two is connect altogether.
10. method according to claim 9, it is characterised in that：The wide bandgap semiconductor materials use carborundum or nitrogen Change gallium.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108258040A (en) * 2017-12-26 2018-07-06 西安电子科技大学 Igbt with wide band gap semiconducter substrate material and preparation method thereof
CN108511528A (en) * 2018-04-11 2018-09-07 西安电子科技大学 Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof
CN108538909A (en) * 2018-04-08 2018-09-14 西安电子科技大学 Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block
CN108598159A (en) * 2017-12-26 2018-09-28 西安电子科技大学 Igbt and preparation method thereof with wide bandgap semiconductor materials/silicon semiconductor material hetero-junctions
CN110349853A (en) * 2018-04-04 2019-10-18 英飞凌科技股份有限公司 Wide bandgap semiconductor device and the method for being used to form wide bandgap semiconductor device
CN110429137A (en) * 2019-08-15 2019-11-08 西安电子科技大学 With partial nitridation gallium/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof
CN110518069A (en) * 2019-08-15 2019-11-29 西安电子科技大学 With partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101879A (en) * 2006-07-06 2008-01-09 日产自动车株式会社 Method of manufacturing semiconductor device
US20130277688A1 (en) * 2009-07-21 2013-10-24 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101101879A (en) * 2006-07-06 2008-01-09 日产自动车株式会社 Method of manufacturing semiconductor device
US20130277688A1 (en) * 2009-07-21 2013-10-24 Rohm Co., Ltd. Semiconductor device and manufacturing method thereof

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CN108258040A (en) * 2017-12-26 2018-07-06 西安电子科技大学 Igbt with wide band gap semiconducter substrate material and preparation method thereof
CN108598159A (en) * 2017-12-26 2018-09-28 西安电子科技大学 Igbt and preparation method thereof with wide bandgap semiconductor materials/silicon semiconductor material hetero-junctions
CN108258040B (en) * 2017-12-26 2021-01-01 西安电子科技大学 Insulated gate bipolar transistor with wide band gap semiconductor substrate material and manufacturing method thereof
CN108598159B (en) * 2017-12-26 2021-01-01 西安电子科技大学 Insulated gate bipolar transistor with wide band gap semiconductor material/silicon semiconductor material heterojunction and manufacturing method thereof
CN110349853A (en) * 2018-04-04 2019-10-18 英飞凌科技股份有限公司 Wide bandgap semiconductor device and the method for being used to form wide bandgap semiconductor device
CN110349853B (en) * 2018-04-04 2023-08-18 英飞凌科技股份有限公司 Wide bandgap semiconductor device and method for forming a wide bandgap semiconductor device
CN108538909A (en) * 2018-04-08 2018-09-14 西安电子科技大学 Hetero-junctions vertical double-diffusion metal-oxide-semiconductor field effect transistor and preparation method thereof with charge compensation block
CN108511528A (en) * 2018-04-11 2018-09-07 西安电子科技大学 Lateral double diffusion metal oxide composite semiconductor field-effect tube with deep drain region and preparation method thereof
CN108511528B (en) * 2018-04-11 2020-11-06 西安电子科技大学 Transverse double-diffusion metal oxide composite semiconductor field effect transistor with deep drain region and manufacturing method thereof
CN110429137A (en) * 2019-08-15 2019-11-08 西安电子科技大学 With partial nitridation gallium/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof
CN110518069A (en) * 2019-08-15 2019-11-29 西安电子科技大学 With partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof
CN110518069B (en) * 2019-08-15 2020-10-13 西安电子科技大学 VDMOS (vertical double-diffused metal oxide semiconductor) with partial silicon carbide/silicon semiconductor material heterojunction and manufacturing method thereof

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