CN110544723B - U-MOSFET with partial silicon carbide material/silicon material heterojunction and manufacturing method thereof - Google Patents
U-MOSFET with partial silicon carbide material/silicon material heterojunction and manufacturing method thereof Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 75
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 75
- 239000000463 material Substances 0.000 title claims abstract description 23
- 239000002210 silicon-based material Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims description 47
- 238000005530 etching Methods 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000001534 heteroepitaxy Methods 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 8
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 5
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Abstract
The invention provides a U-MOSFET with a partial silicon carbide material/silicon material heterojunction and a manufacturing method thereof. The high critical breakdown electric field characteristic of the silicon carbide material is utilized, the strong electric field of the gate oxide at the corner of the device groove gate is introduced into the silicon carbide material through the breakdown point transfer technology, the longitudinal electric field peak of the device is raised, the device can bear higher breakdown voltage, the limitation that the traditional silicon-based U-MOSFET device is limited by the critical breakdown electric field of the single silicon material is broken through, meanwhile, the high thermal conductivity characteristic of the silicon carbide material is beneficial to heat dissipation of the device, the reliability of the device is improved, and the performance of the device is effectively improved.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a U-MOSFET structure and a manufacturing method thereof.
Background
The semiconductor power device is a high-power electronic device mainly used for the aspects of electric energy conversion and control circuits of electric power equipment. With the rapid development of semiconductor power technology, power semiconductor devices have been widely used in modern industrial control and defense equipment. In the late 80 s of the 20 th century, the power semiconductor industry began to develop U-MOSFET structures using this process technology due to the development of notching technology. Compared with the VD-MOSFET structure, the U-MOSFET structure also has the characteristics of high switching speed, small loss, high input impedance, small driving power, good frequency characteristic, high transconductance, high linearity and the like, and because the U-MOSFET structure does not have a JFET area, the internal resistance of the U-MOSFET structure is obviously reduced.
Disclosure of Invention
The invention provides a U-MOSFET with a partial silicon carbide material/silicon material heterojunction and a manufacturing method thereof, aiming at further improving the breakdown voltage of the U-MOSFET and improving the performance of a device.
The technical scheme of the invention is as follows:
a U-MOSFET having a partial silicon carbide material/silicon material heterojunction, comprising:
an N + type substrate;
the N-type epitaxial layer is positioned on the upper surface of the N + type substrate;
p-type base regions are respectively formed in the left end region and the right end region of the upper part of the N-type epitaxial layer; a channel is formed in the P-type base region, and the N + type source region is contacted with the P + channel substrate;
the source electrode covers the upper surface of a region where the P + channel substrate contact and the N + type source region are connected; two source electrodes are connected in common;
the drain electrode is positioned on the lower surface of the N + type substrate;
it is characterized in that:
the N + type substrate is made of a silicon carbide material;
the N-type epitaxial layer is composed of two parts: the N-type silicon carbide epitaxial layer with a part of concave structure is positioned in the middle area of the upper surface of the N + type substrate; the other part is two N-type silicon epitaxial layers which are respectively positioned in the left end region and the right end region of the upper surface of the N + type substrate and correspondingly adjacent to the side surface of the N-type silicon carbide epitaxial layer; the two P-type base regions are correspondingly formed on the upper parts of the two N-type silicon epitaxial layers;
the thickness of the N-type silicon epitaxial layer is larger than that of the N-type silicon carbide epitaxial layer, a groove structure is integrally formed, the groove takes the concave part of the concave-shaped structure as the bottom, the depth of the groove is larger than that of a PN junction between the P-type base region and the N-type silicon epitaxial layer, a grid electrode is formed by filling the groove, and a grid oxide layer is arranged between the grid electrode and the inner wall of the groove; the upper surface of the grid is covered with a passivation layer;
the thickness and the doping concentration of the N-type silicon carbide epitaxial layer and the N-type silicon epitaxial layer are determined by the withstand voltage requirement of the device, wherein the doping concentration of the N-type silicon carbide epitaxial layer and the N-type silicon epitaxial layer is lower than that of the N + type substrate.
Based on the above scheme, the invention further optimizes as follows:
the two source electrodes are connected into a whole through metal (namely metal which is the same as the source electrode material) which covers the upper surface of the passivation layer.
The concave structure is formed by partial etching, the left side and the right side of the N-type epitaxial layer are etched and extended to the upper surface of the N + type substrate, the middle part is etched and extended into the N-type silicon carbide epitaxial layer, and the etching depth L of the top of the N-type silicon carbide epitaxial layer n 0.5 to 2 μm.
The N-type silicon epitaxial layer is formed on the upper surfaces of the N + type substrate and the N-type silicon carbide epitaxial layer by a heteroepitaxy technology or a bonding technology; the P-type base region and the N + type source region thereof are in contact with the P + channel substrate and are formed on the upper part of the N-type silicon epitaxial layer by adopting an ion implantation technology.
The doping concentration of the N-type silicon epitaxial layer and the N-type silicon carbide epitaxial layer is 4-6 orders of magnitude smaller than that of the N + type substrate.
The doping concentration of the N-type silicon epitaxial layer is 1 multiplied by 10 15 ～3×10 15 cm -3 The doping concentration of the N-type silicon carbide epitaxial layer is 3 multiplied by 10 15 ～6×10 15 cm -3 。
The height difference L between the bottom of the groove and the PN junction m 2-4 μm.
The distance W from the side surface of the groove to the side surface of the N-type silicon carbide epitaxial layer n 0.5 to 2 μm.
The grid electrode is a polysilicon grid electrode, the source electrode is a metalized source electrode, and the drain electrode is a metalized drain electrode.
The technical scheme of the invention has the following beneficial effects:
the invention combines a silicon carbide material with a silicon material, adopts the silicon carbide material as a substrate of a U-MOSFET, epitaxially grows and forms an N-type silicon carbide material epitaxial layer with lower doping concentration on an N + type substrate of the silicon carbide material, partially etches the N-type silicon carbide material epitaxial layer to form a convex structure, heteroepitaxially grows (or forms by utilizing a bonding technology) the N-type silicon material epitaxial layer by taking the N-type silicon carbide epitaxial layer as a base, and forms an active region of the U-MOSFET device by adopting a silicon maturation process. The high-critical breakdown electric field characteristic of the silicon carbide material is utilized, the strong electric field of the gate oxide at the corner of the device groove gate is introduced into the silicon carbide material through breakdown point transfer, the longitudinal electric field peak of the device is raised, the U-MOSFET device can bear higher breakdown voltage, the limitation that the traditional silicon-based U-MOSFET device is limited by the critical breakdown electric field of the single silicon material is broken through, meanwhile, the high-thermal conductivity characteristic of the silicon carbide material is beneficial to heat dissipation of the device, the reliability of the device is improved, and the performance of the device is effectively improved.
Drawings
FIG. 1 is a schematic diagram of the present invention.
Wherein, the 1-N + type source region; 2-P + channel substrate contact (P + body region); 3-a grid; 4-a passivation layer; 5-a source electrode; 6-gate oxide layer; 7-P type base region; an 8-N type silicon carbide epitaxial layer; 9-N type silicon epitaxial layer; a 10-N + type substrate; 11-drain electrode.
Detailed Description
The invention will be described below by taking an N-channel U-MOSFET as an example in conjunction with the accompanying drawings.
As shown in fig. 1, the present embodiment includes:
an N + type substrate 10 of silicon carbide material;
the thickness and the concentration of the N-type silicon carbide epitaxial layer 8 positioned in the middle area of the upper surface of the N + type substrate 10 are set according to different withstand voltage grades;
the N-type silicon epitaxial layer 9 is formed on the upper surfaces of the N + type substrate 10 and the N-type silicon carbide epitaxial layer 8 through heteroepitaxial growth or by utilizing a bonding technology, and the thickness and the concentration of the N-type silicon epitaxial layer are set according to different withstand voltage grades;
two P-type base regions 7 respectively formed in the left and right end regions of the upper part of the N-type silicon epitaxial layer 9; a channel, an N + type source region 2 and a P + channel substrate contact 1 are formed in each P type base region 7; etching a groove into the N-type silicon epitaxial layer 9 in a region, located between the two N + type source regions 2, of the N-type silicon epitaxial layer, and meanwhile, the depth of the groove is larger than that of a PN junction between the P-type base region 7 and the N-type silicon epitaxial layer 9, the groove extends into the N-type silicon carbide epitaxial layer 8, the depth of the groove is set according to different withstand voltage grades, and a gate oxide layer 6 is deposited on the inner wall of the groove;
the grid 3 is arranged on the inner wall of the grid oxide layer 6; the upper surface of the grid 3 is covered with a passivation layer 4;
the source electrode 5 covers the upper surface of a region where the P + channel substrate contact 1 is connected with the N + type source region 2; two source electrodes 5 are connected in common;
and the drain electrode 11 is positioned on the lower surface of the N + type substrate 10.
The doping concentration of the N-type silicon epitaxial layer and the N-type silicon carbide epitaxial layer is 4-6 orders of magnitude smaller than that of the N + type substrate. The doping concentration of the N-type silicon epitaxial layer is 1 multiplied by 10 15 ～3×10 15 cm -3 The doping concentration of the N-type silicon carbide epitaxial layer is 3 multiplied by 10 15 ～6×10 15 cm -3 。
Etching depth L of top of N-type silicon carbide epitaxial layer n Is 0.5 to 2 μm. The height difference L between the bottom of the groove and the PN junction m 2-4 μm. Distance W from the side of the groove to the side of the N-type silicon carbide epitaxial layer n 0.5 to 2 μm.
Taking an N-channel U-MOSFET as an example, the method can be specifically prepared by the following steps:
1) Forming the N-type silicon carbide epitaxial layer 8 by extending the upper surface of an N + type substrate 10 of a silicon carbide material;
2) Forming a metalized drain on the lower surface of the N + type substrate 10;
3) Partially etching the N-type silicon carbide epitaxial layer 8 by adopting a partial etching technology, and etching and extending to the upper surface of the N + type substrate 10 to form a convex structure;
4) Forming an N-type silicon epitaxial layer 9 on the upper surfaces of the N + type substrate 10 and the N-type silicon carbide epitaxial layer 8 by using a heteroepitaxial growth technology (or by using a bonding technology);
5) Forming a P-type base region 7, an N + type source region 2 and a P + channel substrate contact 1 in the left and right end regions of the upper part of an N-type silicon epitaxial layer 9 by adopting an ion implantation technology, and etching a region between the two N + type source regions 2 to form a groove, wherein the groove depth is larger than the depth of a PN junction between the P-type base region 7 and the N-type silicon epitaxial layer 9, and the groove extends into an N-type silicon carbide epitaxial layer 8; a gate oxide layer 6 is deposited on the inner wall of the groove;
6) Depositing a gate oxide layer 6 on the inner wall of the groove by adopting a local oxidation technology, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate 3;
7) Depositing a passivation layer 4 on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
8) And depositing metal in the contact hole and etching to form a source electrode, and forming a source-level integrated structure covering the whole P-type base region 7 and the upper surface of the passivation layer 4.
ISE TCAD simulation shows that the device has improved performance compared with the traditional silicon-based U-MOSFET, and the breakdown voltage of the device is improved by 2-3 times compared with the traditional silicon-based U-MOSFET under the conditions that the lengths of drift regions of two devices are the same and the doping concentration of the drift regions is the same. For example, when the drift region length of the U-MOSFET is 11 μm, the breakdown voltage breaks through 300V.
The U-MOSFET of the present invention may also be a P-channel MOSFET, and its structure is equivalent to that of an N-channel U-MOSFET, and it is considered to be within the scope of the claims of the present application, and will not be described herein again.
In the U-MOSFET of the present invention, 8 and 9 may be of the same type or different types, that is: 8 is an N-type silicon carbide epitaxial layer, and 9 can also be a P-type silicon epitaxial layer; or 8 can be a P-type silicon carbide epitaxial layer, and 9 can be an N-type silicon epitaxial layer; alternatively, 8 may be a P-type silicon carbide epitaxial layer and 9 may be a P-type silicon epitaxial layer. The structure of the U-MOSFET device is still equivalent to that of the present invention, and should be considered as falling within the protection scope of the claims of the present application, and the description thereof is omitted.
Claims (10)
1. A U-MOSFET having a partial silicon carbide material/silicon material heterojunction, comprising:
an N + -type substrate (10);
an N-type epitaxial layer positioned on the upper surface of the N + type substrate (10);
p-type base regions (7) respectively formed in the left end region and the right end region of the upper part of the N-type epitaxial layer; a channel, an N + type source region (2) and a P + channel substrate contact (1) are formed in the P type base region (7);
the source electrode (5) covers the upper surface of a region where the P + channel substrate contact (1) is connected with the N + type source region (2); two source electrodes (5) are connected together;
the drain electrode (11) is positioned on the lower surface of the N + type substrate (10);
the method is characterized in that:
the N + type substrate (10) adopts a silicon carbide material;
the N-type epitaxial layer is composed of two parts: an N-type silicon carbide epitaxial layer (8) with a part of concave structure is positioned in the middle area of the upper surface of the N + type substrate (10); the other part is two N-type silicon epitaxial layers (9) which are respectively positioned in the left end region and the right end region of the upper surface of the N + type substrate (10) and correspondingly adjacent to the side surfaces of the N-type silicon carbide epitaxial layers (8); the two P-type base regions (7) are correspondingly formed on the upper parts of the two N-type silicon epitaxial layers (9);
the thickness of the N-type silicon epitaxial layer (9) is larger than that of the N-type silicon carbide epitaxial layer (8), a groove structure is integrally formed, the groove takes a concave part of the concave-shaped structure as the bottom, the depth of the groove is larger than that of a PN junction between the P-type base region (7) and the N-type silicon epitaxial layer (9), a grid electrode (3) is formed by filling the groove, and a grid oxide layer (6) is arranged between the grid electrode (3) and the inner wall of the groove; the upper surface of the grid (3) is covered with a passivation layer (4);
the thickness and the doping concentration of the N-type silicon carbide epitaxial layer (8) and the N-type silicon epitaxial layer (9) are determined by the voltage-resistant requirement of the device, wherein the doping concentration of the N-type silicon carbide epitaxial layer (8) and the N-type silicon epitaxial layer (9) is lower than that of the N < + > type substrate (10).
2. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the two source electrodes (5) are connected into a whole through metal which is covered on the upper surface of the passivation layer (4) and is made of the same material.
3. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the concave structure is formed by partial etchingThe left side and the right side of the N-type epitaxial layer are etched and extended to the upper surface of the N + type substrate (10), the middle part is etched and extended into the N-type silicon carbide epitaxial layer (8), and the etching depth L of the top of the N-type silicon carbide epitaxial layer (8) n 0.5 to 2 μm.
4. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the N-type silicon epitaxial layer (9) is formed on the upper surfaces of the N + type substrate (10) and the N-type silicon carbide epitaxial layer (8) through a heteroepitaxy technology or a bonding technology; the P-type base region (7), the N + type source region (2) thereof and the P + channel substrate contact (1) are formed on the upper part of the N-type silicon epitaxial layer (9) by adopting an ion implantation technology.
5. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the doping concentration of the N-type silicon epitaxial layer (9) and the N-type silicon carbide epitaxial layer (8) is 4-6 orders of magnitude smaller than that of the N + type substrate (10).
6. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the doping concentration of the N-type silicon epitaxial layer (9) is 1 multiplied by 10 15 ～3×10 15 cm -3 The doping concentration of the N-type silicon carbide epitaxial layer (8) is 3 multiplied by 10 15 ～6×10 15 cm -3 。
7. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the height difference L between the bottom of the groove and the PN junction m 2-4 μm.
8. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the distance W from the side surface of the groove to the side surface of the N-type silicon carbide epitaxial layer (8) n Is 0.5 to 2 μm.
9. A U-MOSFET according to claim 1 having a partial silicon carbide/silicon material heterojunction, wherein: the grid electrode (3) is a polysilicon grid electrode, the source electrode (5) is a metalized source electrode, and the drain electrode (11) is a metalized drain electrode.
10. A method of making a U-MOSFET of claim 1 having a partial silicon carbide material/silicon material heterojunction, comprising the steps of:
1) Extending and forming an N-type silicon carbide epitaxial layer (8) on the upper surface of an N + type substrate (10) of silicon carbide;
2) Forming a metalized drain electrode (11) on the lower surface of the N + type substrate (10);
3) Partial etching technology is adopted to partially etch the N-type silicon carbide epitaxial layer (8), and the left side and the right side are etched and extended to the upper surface of the N + type substrate (10);
4) Heteroepitaxially growing or forming an N-type silicon epitaxial layer (9) on the upper surfaces of the N + type substrate (10) and the N-type silicon carbide epitaxial layer (8) by utilizing a bonding technology;
5) Forming a P-type base region (7), an N + type source region (2) and a P + channel substrate contact (1) in the left end region and the right end region of the upper portion of an N-type silicon epitaxial layer (9) by adopting an ion implantation technology, etching the region between the two N + type source regions (2) to form a groove, extending the groove into the N-type silicon carbide epitaxial layer (8), wherein the depth of the groove is larger than the depth of a PN junction between the P-type base region (7) and the N-type silicon epitaxial layer (9), the bottom of the groove extends into the N-type silicon carbide epitaxial layer (8), the width of the groove is smaller than the width of the N-type silicon carbide epitaxial layer (8), and a gate oxide layer (6) is deposited on the inner wall of the groove;
6) Depositing a gate oxide layer (6) on the inner wall of the groove by adopting a local oxidation technology, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate (3);
7) Depositing a passivation layer (4) on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
8) And depositing metal in the contact hole and etching to form a source electrode, and forming a source electrode integrated structure covering the whole P-type base region (7) and the upper surface of the passivation layer (4).
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