CN110429138B - U-MOSFET with partial gallium nitride/silicon semiconductor material heterojunction and manufacturing method thereof - Google Patents
U-MOSFET with partial gallium nitride/silicon semiconductor material heterojunction and manufacturing method thereof Download PDFInfo
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 85
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 66
- 239000010703 silicon Substances 0.000 title claims abstract description 66
- 239000000463 material Substances 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000001534 heteroepitaxy Methods 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 7
- 239000002210 silicon-based material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 3
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007123 defense Effects 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
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Abstract
The invention provides a U-MOSFET with a partial gallium nitride/silicon semiconductor material heterojunction and a manufacturing method thereof. The U-MOSFET device is mainly characterized in that a gallium nitride material and a silicon material are combined to form a heterojunction, an N-type silicon epitaxial layer is formed on the basis of the convex structural surface of the gallium nitride substrate and the whole N-type gallium nitride epitaxial layer, a groove is formed in the middle area of the N-type silicon epitaxial layer in an etching mode, the width of the groove is smaller than that of the N-type gallium nitride epitaxial layer, the bottom of the groove extends into the middle area of the upper portion of the N-type gallium nitride epitaxial layer, and the depth of the groove is larger than that of a PN junction between a P-type base region and the N-type silicon epitaxial layer; by utilizing the high critical breakdown electric field characteristic of the gallium nitride semiconductor material, a strong electric field of gate oxide at the corner of a device groove gate is introduced into the gallium nitride material through breakdown point transfer, the longitudinal electric field peak of the device is raised, and the device performance is effectively improved.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a U-MOSFET structure and a manufacturing method thereof.
Background
The semiconductor power device refers to a high-power electronic device mainly used for an electric energy conversion and control circuit of power equipment. With the rapid development of semiconductor power technology, power semiconductor devices have been widely used in modern industrial control and defense equipment. In the late 80 s of the 20 th century, the power semiconductor industry began to develop U-MOSFET structures using this process technology due to the development of notching technology. Compared with the VD-MOSFET structure, the U-MOSFET structure also has the characteristics of high switching speed, small loss, high input impedance, small driving power, good frequency characteristic, high transconductance, high linearity and the like, and because the U-MOSFET structure does not have a JFET area, the internal resistance of the U-MOSFET structure is obviously reduced.
Disclosure of Invention
The invention provides a U-MOSFET with a partial gallium nitride/silicon semiconductor material heterojunction, and aims to further improve the breakdown voltage of the U-MOSFET and improve the performance of a device.
The technical scheme of the invention is as follows:
the U-MOSFET with partial gallium nitride/silicon semiconductor material heterojunction comprises:
an N + type substrate of gallium nitride material;
the N-type gallium nitride epitaxial layer is positioned in the middle area of the upper surface of the N + type substrate and integrally forms a convex structure with the N + type substrate;
based on an N-type silicon epitaxial layer formed on the surface of the convex-shaped structure, P-type base regions are respectively formed in the left end region and the right end region of the upper portion of the N-type silicon epitaxial layer, and an N + type source region, a P + channel substrate contact and a corresponding channel are formed in each P-type base region;
etching the middle region of the N-type silicon epitaxial layer to form a groove, wherein the width of the groove is smaller than that of the N-type gallium nitride epitaxial layer, the bottom of the groove extends into the middle region of the upper part of the N-type gallium nitride epitaxial layer, and the depth of the groove is larger than that of a PN junction between the P-type base region and the N-type silicon epitaxial layer;
the gate oxide layer covers the inner wall of the groove;
the grid is filled in the grid oxide layer;
a passivation layer covering an upper surface of the gate electrode;
the source electrode covers the upper surface of a region where the P + channel substrate contact and the N + type source region are connected; two source electrodes are connected in common;
the drain electrode is positioned on the lower surface of the N + type substrate;
the thickness and the doping concentration of the N-type gallium nitride epitaxial layer and the N-type silicon epitaxial layer are determined by the voltage-resistant requirement of the device, wherein the doping concentration of the N-type gallium nitride epitaxial layer and the N-type silicon epitaxial layer is lower than that of the N + type substrate.
On the basis of the scheme, the invention further optimizes the following steps:
the two source electrodes are connected into a whole through the same material metal (namely, the same metal as the source electrode material) covering the upper surface of the passivation layer.
The bottom of the groove extends into the middle area of the upper part of the N-type gallium nitride epitaxial layer, and the corresponding etching depth L of the N-type gallium nitride epitaxial layer n Is 0.5 to 2 μm.
The N-type silicon epitaxial layer is formed on the upper surfaces of the N + type substrate and the N-type gallium nitride epitaxial layer through a heteroepitaxy technology or a bonding technology; the P-type base region and the N + type source region thereof are contacted with the P + channel substrate and are formed on the upper part of the N-type silicon epitaxial layer by adopting an ion implantation technology.
The doping concentrations of the N-type silicon epitaxial layer and the N-type gallium nitride epitaxial layer are determined by the designed breakdown voltage, and are about 4-6 orders of magnitude different from those of the N + -type substrate.
The doping concentration of the N-type silicon epitaxial layer and the N-type gallium nitride epitaxial layer is determined according to the designed breakdown voltage, and the doping concentration of the N-type silicon epitaxial layer is 1 multiplied by 10 15 ～3×10 15 The doping concentration of the N-type GaN epitaxial layer is 3 x 10 15 ～6×10 15 cm -3 。
The grid electrode is a polysilicon grid electrode, the source electrode is a metalized source electrode, and the drain electrode is a metalized drain electrode.
The height difference L between the bottom of the groove and the PN junction m 2-4 μm.
The distance W from the side surface of the groove to the side surface of the N-type gallium nitride epitaxial layer n 0.5 to 2 μm.
A method of fabricating the above U-MOSFET having a partial gallium nitride/silicon semiconductor material heterojunction, comprising the steps of:
1) Forming the N-type gallium nitride epitaxial layer on the upper surface of the N + type substrate made of the gallium nitride semiconductor material in an extending mode;
2) Forming a metalized drain on the lower surface of the N + type substrate;
3) Partially etching the N-type gallium nitride epitaxial layer by adopting a partial etching technology, etching and extending to the upper surface of the N + type substrate, and integrally forming a convex structure with the N + type substrate;
4) Forming an N-type silicon epitaxial layer on the upper surfaces of the N + type substrate and the N-type gallium nitride epitaxial layer by using a heteroepitaxial growth technology (or by using a bonding technology);
5) Forming a P-type base region, an N + type source region and a P + channel substrate in the left end region and the right end region of the upper part of the N-type silicon epitaxial layer by adopting an ion implantation technology, and notching the region between the two N + type source regions to ensure that the notching depth is greater than the depth of a PN junction between the P-type base region and the N-type silicon epitaxial layer, wherein the notching extends into the N-type gallium nitride epitaxial layer; depositing a gate oxide layer on the inner wall of the notch groove;
6) Depositing a gate oxide layer on the inner wall of the groove by adopting a local oxidation technology, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate;
7) Depositing a passivation layer on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
8) And depositing metal in the contact hole and etching to form a source electrode, and forming a source-level integrated structure covering the whole P-type base region and the upper surface of the passivation layer.
The technical scheme of the invention has the following beneficial effects:
the invention combines a gallium nitride semiconductor material with a silicon semiconductor material, adopts the gallium nitride semiconductor material as a substrate of a U-MOSFET, epitaxially grows on an N + type substrate of the gallium nitride semiconductor material to form an N type gallium nitride semiconductor material epitaxial layer with lower doping concentration, partially etches the N type gallium nitride semiconductor material epitaxial layer to form a convex structure, then heteroepitaxially grows (or forms by utilizing a bonding technology) the N type silicon semiconductor material epitaxial layer by taking the N type gallium nitride epitaxial layer as a base, and forms an active region of the U-MOSFET device by adopting a silicon mature process. By utilizing the high critical breakdown electric field characteristic of the gallium nitride semiconductor material and through breakdown point transfer, a strong electric field of gate oxide at the corner of a device groove gate is introduced into the gallium nitride semiconductor material, the longitudinal electric field peak of the device is raised, the U-MOSFET device can bear higher breakdown voltage, the limitation that the traditional silicon-based U-MOSFET device is limited by the critical breakdown electric field of a single silicon semiconductor material is broken through, the reliability of the device is improved, and the performance of the device is effectively improved.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Wherein, the 1-N + type source region; 2-P + channel substrate contact (P + body region); 3-a grid; 4-a passivation layer; 5-a source electrode; 6-gate oxide layer; 7-P type base region; an 8-N type gallium nitride epitaxial layer; 9-N type silicon epitaxial layer; a 10-N + type substrate; 11-drain electrode.
Detailed Description
The invention will be described below by taking an N-channel U-MOSFET as an example in conjunction with the accompanying drawings.
As shown in fig. 1, the present embodiment includes:
an N + type substrate 10 of gallium nitride material;
an N-type epitaxial layer of gallium nitride semiconductor material formed on the upper surface of the N + type substrate is marked as an N-type gallium nitride epitaxial layer 8;
an N-type silicon epitaxial layer 9 which is formed on the upper surfaces of the N + type substrate 10 and the N-type gallium nitride epitaxial layer 8 through heteroepitaxial growth or by utilizing a bonding technology;
two P-type base regions 7 respectively formed in the left and right end regions of the upper part of the N-type silicon epitaxial layer 9; a channel, an N + type source region 2 and a P + channel substrate contact 1 are formed in each P type base region 7; notching a region, between two N + type source regions 2, of the N type silicon epitaxial layer into the N type silicon epitaxial layer 9, and simultaneously, notching depth is larger than that of a PN junction between the P type base region 7 and the N type silicon epitaxial layer 9, the notching extends into the N type gallium nitride epitaxial layer 8, the notching depth is set according to different withstand voltage grades, and a gate oxide layer 6 is deposited on the inner wall of the notching; the grid 3 is arranged on the inner wall of the grid oxide layer 6; the upper surface of the grid 3 is covered with a passivation layer 4;
the source electrode 5 covers the upper surface of a region where the P + channel substrate contact 1 is connected with the N + type source region 2; the two source electrodes 5 are connected together;
and the drain electrode 9 is positioned on the lower surface of the N + type substrate 10.
The doping concentration of the N-type silicon epitaxial layer is 1 multiplied by 10 15 ～3×10 15 The doping concentration of the N-type GaN epitaxial layer is 3 × 10 15 ～6×10 15 cm -3 The doping concentration of the N + type substrate is 4-6 orders of magnitude smaller than that of the N + type substrate; the bottom of the groove extends into the middle area of the upper part of the N-type gallium nitride epitaxial layer, and the corresponding etching depth L of the N-type gallium nitride epitaxial layer n 0.5 to 2 μm; the bottom of the groove andthe height difference L between the PN junctions m 2-4 μm; the distance W from the side surface of the groove to the side surface of the N-type gallium nitride epitaxial layer n 0.5 to 2 μm.
Taking an N-channel U-MOSFET as an example, the method can be specifically prepared by the following steps:
1) Forming the N-type gallium nitride epitaxial layer 8 on the upper surface of an N + type substrate 10 made of gallium nitride semiconductor material in an extending way;
2) Forming a metalized drain electrode 9 on the lower surface of the N + type substrate 10;
3) Partially etching the N-type gallium nitride epitaxial layer 8 by adopting a partial etching technology, and etching and extending to the upper surface of the N + type substrate 10 to form a convex structure;
4) Forming an N-type silicon epitaxial layer 9 on the upper surfaces of the N + type substrate 10 and the N-type gallium nitride epitaxial layer 8 by using a heteroepitaxial growth technology (or by using a bonding technology);
5) Forming a P-type base region 7, an N + type source region 2 and a P + channel substrate contact 1 in the left end region and the right end region of the upper part of an N-type silicon epitaxial layer 9 by adopting an ion implantation technology, and notching the region between the two N + type source regions 2 to ensure that the notching depth is greater than the depth of a PN junction between the P-type base region 7 and the N-type silicon epitaxial layer 9, wherein the notching extends into an N-type gallium nitride epitaxial layer 8; a gate oxide layer 6 is deposited on the inner wall of the groove;
6) Depositing a gate oxide layer 6 on the inner wall of the groove by adopting a local oxidation technology, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate 3;
7) Depositing a passivation layer 4 on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
8) And depositing metal in the contact hole and etching to form a source electrode, and forming a source electrode integrated structure covering the whole P-type base region 7 and the upper surface of the passivation layer 4.
Sentaurus TCAD simulation shows that the device has improved performance compared with the traditional silicon-based U-MOSFET, and under the condition that the lengths of drift regions of two devices are the same, the breakdown voltage of the device is improved by 1.5-2 times compared with the traditional silicon-based U-MOSFET. For example, when the drift region length of the U-MOSFET is 10 μm, the breakdown voltage breaks through 300V.
The U-MOSFET of the present invention may also be a P-channel (in this case, 9 is a P-type silicon epitaxial layer), and the structure thereof is equivalent to that of an N-channel U-MOSFET, and it is considered to fall within the protection scope of the claims of the present application, and the details thereof are not repeated herein.
In the U-MOSFET of the present invention, 8 and 9 may be of the same type or different types, that is: 8 is an N-type gallium nitride epitaxial layer, and 9 can also be a P-type silicon epitaxial layer; or 8 is a P-type gallium nitride epitaxial layer, and 9 is an N-type silicon epitaxial layer; alternatively, 8 may be a P-type gan epitaxial layer and 9 may be a P-type si epitaxial layer. The structure of the U-MOSFET device is still the same, and should be considered as falling within the scope of the claims of the present application, and will not be described in detail herein.
Claims (10)
1. A U-MOSFET having a partial gallium nitride/silicon semiconductor material heterojunction, comprising:
an N + type substrate (10) of gallium nitride material;
the N-type gallium nitride epitaxial layer (8) is positioned in the middle area of the upper surface of the N + type substrate (10) and integrally forms a convex structure with the N + type substrate (10);
based on an N-type silicon epitaxial layer (9) formed on the surface of the convex-shaped structure, P-type base regions (7) are respectively formed in the left end region and the right end region of the upper portion of the N-type silicon epitaxial layer (9), and an N + type source region (2), a P + channel substrate contact (1) and corresponding channels are formed in each P-type base region (7);
etching the middle area of the N-type silicon epitaxial layer (9) to form a groove, wherein the width of the groove is smaller than that of the N-type gallium nitride epitaxial layer (8), the bottom of the groove extends into the middle area of the upper part of the N-type gallium nitride epitaxial layer (8), and the depth of the groove is larger than that of a PN junction between the P-type base region (7) and the N-type silicon epitaxial layer (9);
a gate oxide layer (6) covering the inner wall of the groove;
the grid electrode is filled in the grid oxide layer (6);
a passivation layer (4) covering the upper surface of the gate electrode (3);
the source electrode (5) covers the upper surface of a region where the P + channel substrate contact (1) is connected with the N + type source region (2); two source electrodes (5) are connected together;
the drain electrode (11) is positioned on the lower surface of the N + type substrate (10);
the thickness and the doping concentration of the N-type gallium nitride epitaxial layer (8) and the N-type silicon epitaxial layer (9) are determined by the voltage-resistant requirement of the device, wherein the doping concentration of the N-type gallium nitride epitaxial layer (8) and the N-type silicon epitaxial layer (9) is lower than that of the N + type substrate (10).
2. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the two source electrodes (5) are connected into a whole through metal which is covered on the upper surface of the passivation layer (4) and is made of the same material.
3. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the bottom of the groove extends into the middle area of the upper part of the N-type gallium nitride epitaxial layer (8), and the corresponding etching depth L of the N-type gallium nitride epitaxial layer (8) n 0.5 to 2 μm.
4. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the N-type silicon epitaxial layer (9) is formed on the upper surfaces of the N + type substrate (10) and the N-type gallium nitride epitaxial layer (8) through a heteroepitaxy technology or a bonding technology; the P-type base region (7), the N + type source region (2) thereof and the P + channel substrate contact (1) are formed on the upper part of the N-type silicon epitaxial layer (9) by adopting an ion implantation technology.
5. A U-MOSFET having a partial gallium nitride/silicon semiconductor material heterojunction as claimed in claim 1 wherein: the doping concentration of the N-type silicon epitaxial layer (9) and the N-type gallium nitride epitaxial layer (8) is 4-6 orders of magnitude smaller than that of the N + type substrate (10).
6. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the doping concentration of the N-type silicon epitaxial layer (9) is 1 multiplied by 10 15 ～3×10 15 cm -3 The doping concentration of the N-type gallium nitride epitaxial layer (8) is 3 multiplied by 10 15 ～6×10 15 cm -3 。
7. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the grid electrode (3) is a polysilicon grid electrode, the source electrode (5) is a metalized source electrode, and the drain electrode (11) is a metalized drain electrode.
8. The U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, wherein: the height difference L between the bottom of the groove and the PN junction m 2-4 μm.
9. A U-MOSFET having a partial gallium nitride/silicon semiconductor material heterojunction as claimed in claim 1 wherein: the distance W from the side surface of the groove to the side surface of the N-type gallium nitride epitaxial layer (8) n 0.5 to 2 μm.
10. A method of fabricating the U-MOSFET of claim 1 having a partial gallium nitride/silicon semiconductor material heterojunction, comprising the steps of:
1) Forming an N-type gallium nitride epitaxial layer (8) by extending the upper surface of an N + type substrate (10) made of gallium nitride material;
2) Forming a metalized drain electrode (11) on the lower surface of the N + type substrate (10);
3) Partial etching is carried out on the N-type gallium nitride epitaxial layer (8) by adopting a partial etching technology, the left side and the right side are etched and extended to the upper surface of the N + type substrate (10), and the N + type substrate (10) form a convex structure integrally;
4) Heteroepitaxially growing or forming an N-type silicon epitaxial layer (9) on the upper surfaces of the N + type substrate (10) and the N-type gallium nitride epitaxial layer (8) by utilizing a bonding technology;
5) Forming a P-type base region (7), an N + type source region (2) and a P + channel substrate contact (1) in the left end region and the right end region of the upper part of an N-type silicon epitaxial layer (9) by adopting an ion implantation technology, notching the region between the two N + type source regions (2), wherein the notch extends into the N-type gallium nitride epitaxial layer (8), the depth of the notch is larger than the depth of a PN junction between the P-type base region (7) and the N-type silicon epitaxial layer (9), the bottom of the groove extends into the N-type gallium nitride epitaxial layer (8), the width of the groove is smaller than the width of the N-type gallium nitride epitaxial layer (8), and a gate oxide layer (6) is deposited on the inner wall of the notch;
6) Depositing a gate oxide layer (6) on the inner wall of the groove by adopting a local oxidation technology, depositing polycrystalline silicon, and then etching the polycrystalline silicon and the gate oxide layer to form a polycrystalline silicon gate (3);
7) Depositing a passivation layer (4) on the surface of the device, and etching a contact hole at a position corresponding to the source electrode;
8) And depositing metal in the contact hole and etching to form a source electrode, and forming a source electrode integrated structure covering the whole P-type base region (7) and the upper surface of the passivation layer (4).
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