KR101167530B1 - Super heterojunction semiconductor device structure and its fabrication method - Google Patents
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Abstract
The present invention relates to a super heterojunction power semiconductor device having a simple structure and easy to manufacture, and improved on resistance and operating characteristics, and a method of manufacturing the same.
Such a super heterojunction semiconductor device according to the present invention includes an n + type silicon semiconductor substrate; An n-type filler formed by an epi layer remaining after continuously etching an n-type silicon epi layer formed on the substrate; a p-type filler formed by selectively epitaxially growing at least one epitaxial layer of a SiGe-based semiconductor in an etched trench between n-type fillers; P-channels formed through activating the ion implanted boron and drive-in diffusion; A gate formed by depositing a polysilicon thin film; High concentration n + and p + layers formed in the p-channel layer; And a metal thin film for metal-semiconductor ohmic bonding.
Further, this method of manufacturing a semiconductor device are n-p to the SEG technique for forming a trench by etching the epitaxial layer so as to grow the epitaxial layer and includes a super heterojunction process of forming a p- filler.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device and a method for manufacturing the same, and more particularly, to a super heterojunction semiconductor device having a simple structure and easy to manufacture, and having improved on resistance and operating characteristics, and a method for manufacturing the same.
In general, power MOS devices are used in power electronic application circuits because they have a large input impedance, a fast switching speed, thermal stability, and a large SOA (Safe Operating Area) compared to bipolar transistors.
An example of such a power MOS device is shown in FIG. 1, wherein FIG. 1A is a VDMOS, B is a TDMOS, and C is a cross-sectional structure of an SJ-MOS semiconductor device. Double diffused MOSFET (DMOS) devices are the most traditional and representative method in silicon semiconductors, and the vertical VDMOS devices are used for power control from 100 to 1,000V. However, it is still used for low voltage of 400V or less because of high on-resistance and high heat generation at high voltage, low power efficiency and limited use for a long time.
Recently, in order to solve the problems of low efficiency due to on-resistance and heat generation of VDMOS, technology development for TDMOS (Trench-gate DMOS) or SJ-MOS (Super-junction MOS) has been in progress. In particular, SJ-MOS is known to be the best device structure because it can provide superior on-resistance and operation characteristics compared to DMOS or TDMOS because it is used at high voltage of 600 ~ 2000V. However, SJ-MOS is difficult to develop technology that can stabilize the best performance due to the complicated manufacturing process and device structure.
On-resistance is proportional to BV 2.5 in general Si MOS, whereas on-resistance is linearly proportional to BV in SJ-MOS, which is the best device structure for lowering on-resistance in high voltage devices with high breakdown voltage.
For a paper on superjunction, see G. Deboy, F. Udrea, "Superjunction & Technologies-Benefits and Limitations of a Revolutionary Step in Power Electronics," EPE 2007, Aalborg, Denmark, Sept. 2-5 (2007) reviewed the structure and characteristics of super-junction MOSFET, 3D-RESURF. On-resistance of 10 to 100 mΩcm 2 in horizontal and vertical superjunction MOSFETs has been shown to be developed in 500-700V breakdown voltage devices, and the importance of charge compensation and process margin is described.
2 is an example of a typical horizontal SJ-MOS device of the prior art, (A) is a sapphire, (B) is a cross-sectional structure of a semiconductor device configured using a BOX. Although SJ-MOS excels in high voltage characteristics, additional efforts on horizontal device structures are required when fabricating Intelligent Power Control chips integrated with power control ICs. However, the horizontal SJ-MOS has a problem in that the area with the substrate increases and the leakage current increases due to the high voltage applied to the junction. Therefore, sapphire or box was placed between the horizontal SJ-MOS and the substrate to solve the problems such as the increase of capacitance by the junction and the increase of leakage current. However, when sapphire is still used, there is a problem in deterioration of stability due to a decrease in thermal conductivity, and in the case of using BOX, the difficulty of manufacturing and packaging an ultra-thin structure remains a problem.
Meanwhile, S. Yamauchi, T. Shibata, S. Nogami, T. Yamaoka, Y. Hattori, H. Yamaguchi, "200V Super junction MOSFET fabricated by high aspect ratio trench filling," Proceedings of the 18th International Symposium on Power Semiconductor Devices &IC's,"" Naples, Italy, June 4-8 (2006). Introduced the trench filling technique for superjunction devices. The trench structure with unit cell pitch of 2.7 um and aspect ratio of 18 was implemented by selective epitaxial growth using DCS and HCl gas. The breakdown voltage is 225 V and the on-resistance is 1.5 mΩΩcm 2 , a 67% improvement over the silicon MOSFET limit.
In addition, Motorola Freescale Semiconductor Inc. patents include Bose; Amitava ,, Khemka; Vishnu, Parthasarthy; Vijay Zhu; Ronghua, "Trench MOS RESURF super-junction devices," US6750524, (May 14, 2002), proposed a structure for a SJ-MOSFET of RESURF structure in the US patent. Unlike the conventional structure, an insulator material was deposited between the n-pillar and the p-pillar to electrically insulate between the junctions. Although this structure has an effect of isolation, a large number of oxide film junctions are formed in the semiconductor drift channel, thereby deteriorating characteristics due to an interface trap. And since the p-filler is deposited in a polycrystalline state, it is difficult to achieve superior performance compared to a general SJ-MOSFET.
FIG. 3 is an example of a typical vertical SJ-MOS device of the prior art, in which (A) uses an orthogonal trench gate, and (B) shows a cross section of a semiconductor device using a parallel trench gate. Structure. Initially, a device having a balanced trench gate structure was developed, and a lot of technical developments have recently been made for SJ-MOS employing a vertical trench gate to increase current driving capability.
On the other hand, M. Kitada, S. Kunori, T. Kyrosaki, "Dependence of electrical properties of super junction diode on voids within trench refill region," Proceedings of the 19th international Symposium on Power Semiconductor Device & ICs, Jeju, May 27-30 (2007) announced the effect of voids remaining after refilling trenches for supermatching. The larger the pore size, the higher the reverse leakage run, and the reverse recovery time was 800 ns when there was no air gap, but was measured as small as 200 ~ 600ns due to the presence of the air gap. The voids and dislocations increase the leakage current and severely degrade the device's performance.
On the other hand, as a patent of Fuji Electric Systems Co., LTD., M, Takei, "Super-junction semiconductor device," (July, 13,2010, WO2011 / 07560 A1) has a p-filler compared to the conventional SJ-MOSFET. In addition, a structure formed at the bottom of the gate is proposed. It seems to increase the breakdown voltage and lower the on-resistance by controlling the current flow. However, additionally inserted p-filler increases the area of the chip, so it is considered that the loss of the substrate area is large.
Starting with the DMOS as described above, the technical development of silicon semiconductors for high voltage power devices has been developed into various device structures. However, recently, due to the global high oil prices and the importance of eco-friendliness, the need for power devices for new and renewable energy fields such as solar cells, fuel cells and wind power has increased. In order to meet the industrial requirements of this era, future power devices must be lowered to minimize on-resistance at higher voltages. Therefore, SJ-MOS developed in various forms of the prior art also requires innovative performance improvements using new materials and new structures.
4 is a cross-sectional structure of a unit cell of a representative SJ-MOS semiconductor device of the prior art. SJ-MOS, which is a homojunction that forms n- and p-fillers by repeating ion implantation and epitaxial growth, is now widely used, and SJ-MOS, which is a homojunction that forms p-filler as epitaxial growth, is now widely used. It is used.
J. Sakakibara, Y. Noda, T. Shibata, S. Nogami, T. Yamaoka, H. Yamaguchi, "600-V Class Super Junction MOSFET with High Aspect Ratio P / N Columns Structure," Proceedings of the 20th International Symposium on Power Semiconductor Devices & ICs, Orlando, May 18-22 (2008), announced a 600 V superjunction MOSFET with lower on-resistance than IGBT. The width and depth of the trench were 1.3 um and 37 um with 25 aspect ratios. The breakdown voltage of 685 V and low on-resistance of 8 ~ 9 mΩcm 2 resulted in the characteristics comparable to that of IGBT in the 600 V class device.
The cross-sectional structure of a unit cell of a typical SJ-MOS semiconductor device in the prior art of FIG. 4A shows various problems. That is, since the p-filler is selectively epitaxially grown at high temperature, it is difficult to control the doping concentration and the position of the junction interface due to co-doping due to diffusion between the junctions, and thus the charge balance represented by Qn and Qp. Difficult to control In addition, minute voids are easily formed in the trench, which increases leakage current or serves as a starting point for crack propagation, thereby lowering reliability. In addition, the process technology for the device structure in which the trench width is extremely reduced to the level of 1 um and the aspect ratio is increased to 20 or more is a very difficult problem in the mass production process that needs to manage the reproducibility and yield.
In FIG. 4B, the on-resistance of the SJ-MOS is smaller than the DMOS or silicon limit, and can be minimized as the aspect ratio of the pillar trench is increased. In other words, if the aspect ratio of the filler is increased to 10 or more, it is possible to manufacture up to 7 to 9 mΩcm 2 which is the on resistance of the IGBT at 600 V class. Therefore, as the on-resistance is lowered at high voltage, there is a problem of performing a difficult process step of forming a deep trench and filling it with p-type epitaxial growth.
Meanwhile, J.G., a patent of Fairchild Korea Semiconductor Ltd. Lee, J.Y. Jung, H.C. Jang, "Superjunction Semiconductor Device," (US 7,301,203 B2, Nov. 27, 2007) has proposed a structure that adds a guard ring at the edge of the device as a way to enhance high voltage immunity in a conventional SJ-MOSFET. The SJ structure, which repeatedly forms the P-pillar and the n-pillar, is disposed at the edge, and the uppermost p-pillar is made of metal wires to arrange the guard ring generally used in high voltage devices. In this patent, a commonly known method is used for the unit cell, which is the core of the SJ-MOS.
The present invention was developed to solve the above problems of the prior art, and an object of the present invention is to provide a super heterojunction MOS device (hereinafter referred to as "SHJ-MOS") device made by a SiGe hetero epi junction.
In particular, the present invention forms a p-filler of the device by SiGe to alleviate the problems associated with high temperature selective epitaxial growth, and in the heterojunction by controlling the injection phenomenon of electrons and holes, the operating speed, on-resistance, Significantly improved electrical characteristics such as leakage current, 600 ~ 2000V by implementing a device structure with small pitch of superjunction unit-cell and large aspect ratio of trench An object of the present invention is to provide a super-heterojunction semiconductor device capable of operating at a resistance of <10 mΩcm 2 at a high voltage of and a manufacturing method thereof.
A super heterojunction semiconductor device according to the present invention for achieving the above object, the first conductive semiconductor substrate doped with a high concentration, the first conductive epitaxial layer formed on the substrate, the first conductive epitaxial layer A plurality of pillar-shaped first conductive pillars formed by etching at intervals of the plurality of pillars, and a plurality of second conductive pillars filled with a heterojunction epitaxial layer in the etched interior between the first conductive pillars; The carrier channel is formed at the heterojunction of the second conductive filler.
In a preferred embodiment of the present invention, the first conductive filler is an n-type Si epi layer, and the second conductive filler is a p-type SiGe epi layer.
As a preferred embodiment of the present invention, the second conductive filler is characterized in that the SiGe single epi layer of a single composition or SiGe having a plurality of compositions is formed of a plurality of epi layers.
The method for manufacturing a super hetero epijunction semiconductor device according to the present invention configured as described above includes (A) forming an n-type silicon epi layer on an n + type silicon semiconductor substrate and growing a silicon oxide film (B) a photoresist ( Forming a trench by photolithography, and subsequently etching the oxide film and the n-type silicon epi layer to form a trench (C) forming a p-type SiGe epi filler in the trench ( D) Planarizing the surface of the substrate (E) After growing a protective oxide film on top of the substrate, a p-channel pattern is formed by PR photolithography and ion implanted boron, and the ion implanted boron is activated and drive-in -in) forming a p-type MOS channel layer through diffusion (F) depositing a polysilicon thin film to form a gate (G) forming a pattern by photolithography to form a source of MOS Forming a junction of a high concentration layer for an ohmic junction by implanting n + for p and ion for a diode (H) depositing an oxide film on a semiconductor surface, and then forming a contact window through photolithography and etching (I) depositing a metal thin film on top of the substrate to form a metal-semiconductor ohmic junction. (J) Mirror the back surface of the substrate to adjust the thickness of the n + substrate layer, and then apply a metal thin film on the back of the polished substrate. Depositing to form a metal-semiconductor ohmic junction and (K) packaging step.
The present invention can minimize the co-doping due to the interdiffusion between the p-filler and n-filler by manufacturing a semiconductor device with a super-heterojunction structure, it is possible to control the concentration of impurities in each filler constantly, There is an effect that can provide a high-density semiconductor having a cell pitch of 1 ~ 2um level.
In addition, the present invention can provide a semiconductor device having a characteristic of increasing the operation speed of the semiconductor device, a small leakage current, a high breakdown voltage, and a low on-resistance by fabricating the semiconductor device using the superhetero bonding method.
1 is a device structure diagram of an example of a conventional semiconductor,
2 is a device structure of another example of a conventional semiconductor,
3 is another example device structure of a conventional semiconductor,
4 is a structural diagram and characteristic graph of a typical representative SJ-MOS,
5 is a semiconductor device structure diagram using the super heterojunction (SHJ) of the present invention,
6A is a comparison table comparing the characteristics of the SHJ-MOS of the present invention and a conventional semiconductor,
6B is a graph showing the IV characteristics of the SHJ-MOS semiconductor of the present invention.
7A to 7J are PT structural diagrams using a single hetero epi layer as an embodiment of the manufacturing process of the SHJ-MOS semiconductor device of the present invention.
8A to 8J are NPT structure diagrams using a plurality of hetero epi layers as an embodiment of a manufacturing process of the SHJ-MOS semiconductor device of the present invention.
Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. It should be understood, however, that the appended drawings illustrate only the contents and scope of technology of the present invention, and the technical scope of the present invention is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the technical idea of the present invention based on these examples.
The present invention is to provide a semiconductor device having a high density of cell pitch and a method of manufacturing the same, which can control the impurity concentration constant in the filler because it can minimize the inter-doping, it is super between the n-pillar and p-pillar It is characterized by forming a carrier channel by heterojunction (Super Heterojunction).
In the semiconductor device according to the present invention, it is preferable to grow the p - epitaxial layer using a selective epitaxial growth of silicon technique in the trench formed by etching the n - epitaxial layer. One or more epilayers may be formed in the p-pillar.
In addition, the super heterojunction semiconductor device according to the present invention can be any one of the devices forming the SBD, FRD, MOSFET, MESFET, JFET, HEMT structure.
The method for manufacturing a super heterojunction semiconductor device as described above comprises the steps of: (A) forming an n-type silicon epitaxial layer on an n + type silicon semiconductor substrate and growing a silicon oxide film; (B) forming a trench pattern by photolithography using photoresist (PR), and successively etching the oxide film and the n-type silicon epi layer to form a trench; (C) forming a p-type filler in the trench; (D) planarizing the surface of the substrate; (E) After the protective oxide film is grown on the substrate, a p-channel pattern is formed by PR photolithography and ion implanted boron, and the ion implanted boron is activated through p-channel through activation and drive-in diffusion. Forming a MOS channel layer of a type; (F) depositing a polysilicon thin film to form a gate; (G) forming a pattern by photolithography and implanting n + and p + ions to form a junction of a high concentration layer for ohmic bonding; (H) depositing an oxide film on the surface of the semiconductor and then forming a contact window through photolithography and etching; (I) depositing a metal thin film on top of the substrate to form a metal-semiconductor ohmic junction; (J) mirror-polishing the back side of the substrate to adjust the thickness of the n + substrate layer, and then depositing a metal thin film on the back side of the polished substrate to form a metal-semiconductor ohmic junction and (K) packaging step.
As will be described in detail below, in the step of forming an n-type silicon epitaxial layer on the n + type silicon semiconductor substrate and growing the silicon oxide film, an n + type silicon semiconductor substrate is used and an n-type buffer layer is further formed thereon. can do.
5 is a structural diagram showing another example of the super heterojunction semiconductor device according to the present invention, Figure 5 (A) is a SHJ-Schottky Barrier Diode, Figure 5 (B) is a cross-sectional structure of the SHJ-MOS semiconductor device Shows.
In the present invention, by manufacturing a device with a super heterojunction (hereinafter referred to as "SHJ") structure by inter-diffusion between the p-pillar (p-Pillar) and n-Pillar (n-Pillar) Since co-doping can be minimized, the impurity concentration can be uniformly controlled in each filler, and it is advantageous to manufacture a high-density structure having a cell pitch of 1 to 2 um.
In the structure of the super heterojunction in Fig. 5, the n-filler is subjected to tensile stress, and the compressive stress is applied to the p-pillar, so in each case, the mobility of electrons and holes, which are the majority carriers, increases, resulting in high speed. The movement increases the operating speed of the device. In particular, the n-filler interposed between the p-pillars may increase the mobility of electrons in the drift-channel of electrons and uniformly distribute the electric field distribution, thereby increasing the reverse breakdown voltage of the device at a high voltage.
Also, since the structure of heterojunction of n-Si / p-SiGe is high, the injection efficiency of electrons from n-Si to p-SiGe is high while the injection efficiency of holes injected from p-SiGe to n-Si is low. . Therefore, as the transient electrons disappear quickly, the reverse recovery time (trr) becomes small.
In contrast to conventional SJ-MOS structures, the width of n-Si and p-SiGe and the concentration of doped impurities can be controlled in SHJ-MOS. In terms of process, SiGe is advantageous to selective epitaxial growth at low temperature, so it is easy to form p-filler fabricated while filling the trench. Since the epilayer growth step of filling the trench takes place at low temperature, the co-doping by diffusion in the junction is small, and the pillars can be filled accurately since Ge moves well on the epilayer surface.
As described above, the SHJ structure is used in a semiconductor device to increase the operation speed, obtain a characteristic of low leakage current, high breakdown voltage, and low on-resistance. In particular, the pitch of the unit cell is 1 ~ 2um or smaller, providing a very useful solution for power semiconductor devices with high output density. In addition, the SHJ structure of the present invention can be applied to devices of SBD, MOS, and MESFET to increase breakdown voltage, and can be commonly used for multicomponent compound semiconductors such as GaAs, GaN, SiC, and InAs.
6A is a table summarizing the structures, features, and advantages and disadvantages of the semiconductor device and the conventional semiconductor device according to the present invention.
In the case of VD-MOS, the structure and manufacturing method are relatively simple and useful at a low voltage of 30 to 400 V, but the on-resistance is relatively high. The horizontal SJ-MOS is suitable for integration into a planar structure, but there is a limit to increasing the breakdown voltage. Vertical SJ-MOS is best suited for fabricating single chips that operate at high voltages.
However, as described above, the SJ-MOS still contains various engineering problems, so it is difficult to improve performance or to obtain high yield in mass production.
In order to solve these problems, the present invention can provide a semiconductor having a new structure of SHJ-MOS, in which the structure of the filler is improved in the SJ-MOS.
6B is a diagram showing I-V characteristics of the semiconductor device and the conventional semiconductor device according to the present invention.
As shown, it can be seen that the power device according to the present invention has higher DC gain (Gm) and breakdown voltage (BV) than conventional semiconductor devices. This achievement is the effect of increasing the mobility of the carrier electron in the superheterojunction.
Conventional techniques can be cited as examples of performance improvements that can be obtained by controlling stress and energy bandgap in semiconductor devices using heterojunctions. K.H. Shim, S.S. Choi, A.R. Choi, "Transistor structure and manufacturing method," (Aug. 31, 2010, US 7,786,510 B2) presents the fabrication of high performance HBT devices using stress. Park, Byung-Kwan, Yang Ha-Yong, Cheol-Jong Choi, Kyu-Hwan Shim, "Junction Field Effect Transistor Device and Its Manufacturing Method," (July 27, 2011, 10-1053639), are used in JFETs using heterojunctions to control stress and bandgap. About technology. These conventional techniques have shown that heterojunctions with different physical properties can be used to improve performance in hetero semiconductor junctions.
High voltage semiconductor devices must first have high breakdown voltages and low on-resistance at high voltages. In addition, the energy efficiency of power conversion in a power control circuit operating at a high speed and operating in a recent switching mode should be high. Energy efficient semiconductor devices can reduce the load of additional cooling functions and improve the long-term reliability of power devices, resulting in longer lifespan. In particular, it is considered that the most important practical effect is to increase the yield of mass production that satisfies the high specifications of breakdown voltage and on-resistance.
The technology related to the SHJ structure newly provided by the present invention may be applied to SBD, MOS, and MESFET as well as similar devices as the type of semiconductor device to increase the breakdown voltage. In addition, the present invention can be commonly applied to multicomponent compound semiconductors such as Si, SiGe, GaAs, GaN, SiC, InAs as well as semiconductors used in the fabrication of devices.
Hereinafter, a manufacturing process of the semiconductor device according to the present invention will be described.
7A to 7J illustrate an embodiment of a manufacturing process of a SHJ-MOS semiconductor device operating with a punch through (PT) according to the present invention, and describe a step-by-step cross-sectional structure and a process technology of the manufacturing process.
First, as shown in FIG. 7A, an n− type
The
Next, a trench pattern is formed by photolithography using photoresist PR, and the oxide film and the n-type
In this step, as shown in FIG. 7B, a trench pattern is formed by photolithography using a conventional photoresist (PR), and the
As shown in FIG. 7C, in the forming of the p-type filler in the trench, the epitaxial layer of Si 1 - x Ge x (x = 0.0˜0.2) is selectively epitaxially grown in the
In order to grow the epitaxial layer, a native oxide layer having a thickness of several atomic layers formed on the surface of a semiconductor substrate, that is, a wafer, between the silicon wafer and the epitaxial growth chamber is 900 o C to 1000 o. It is removed by heat treatment at a temperature of C for about 2 minutes in a hydrogen atmosphere.
The growth chamber is then adapted to the temperature and gas atmosphere for epitaxial growth. The epitaxial growth apparatus described above is equipped with a rapid thermal process (RTP) such as a halogen lamp or an RF induction heater to enable the epitaxial layers to be continuously grown in a complex structure. Can be. In epitaxial growth, an n-type or p-type impurity can control the concentration of elements such as P. As and B in the range of 10 15 -10 18 cm -3 .
To minimize the effects from the underlayer of the semiconductor thin film, to enhance the effect of electrical isolation, and to produce high quality epi growth, silane (SiH 4 ) or disilane (Si 2 H 6 ) or Dichlorosilane (SiCl 2 H 2 ) gas may be used as the main reaction gas. For the doping of impurities, a gas such as AsH 3 , PH 3 , B 2 H 6 is diluted with hydrogen gas or helium gas.
7D illustrates an example of planarizing the surface of a substrate using CMP. After the LT-SEG for filling the trench, a curved shape is formed in the surface shape of the trench filling epi on the surface of the substrate. Therefore, the uneven surface generated during epitaxial growth should be planarized using CMP. The surface of the planarized substrate also removes defects through heat treatment to allow parts such as the source, channel and gate of the MOS device to form a complete physical junction.
FIG. 7E illustrates a step of forming a channel layer, in which a
FIG. 7F is a diagram illustrating a
FIG. 7G illustrates a step of forming a junction of a high concentration layer for an ohmic junction, wherein a pattern is formed by photolithography, n + for a source of MOS and p + ion implantation for a diode to form an ohmic junction. To form a junction of the high concentration layer. Impurities such as As, P, and Sb are used for ion implantation of the high concentration n + layer 708, and boron atoms are ion implanted into the p + layer 709. Subsequently, annealing is performed through heat treatment to adjust the concentration of impurities in the surface portion of 10 19 -10 21 cm -3 . The characteristics of contact resistance in high-voltage devices are not only directly related to the value of the on-term, but also minimized because they are related to long-term reliability of the device.
7H is a step of forming a contact window. In order to protect the semiconductor surface, an
7I is a step of forming a metal-semiconductor ohmic junction. A metal
7J is a step of controlling the thickness of the substrate layer, and then depositing a metal thin film on the back side of the polished substrate to form a metal-semiconductor ohmic junction.
The back surface of the substrate is mirror polished to adjust the n + substrate layer to a thickness of 30 to 100 μm, and then a metal
8A to 8J illustrate a process of fabricating a SHJ-MOS semiconductor device operating as a non-punch through type (NPT: Non-Punch through), which is another example of the present invention. Although there are parts, they may be duplicated to make it easier to understand the flow of the whole manufacturing process.
In the SHJ-MOS semiconductor device operating with this NPT, an n-type buffer layer is placed between an n + substrate and an n-type epi layer. The breakdown voltage and on resistance are controlled by the thickness and concentration of the n-type buffer layer. Since the NPT type SHJ-MOS is manufactured through a process step similar to that shown in FIGS. 7A to 7J, the present embodiment will be briefly described below.
8A utilizes an n + type silicon semiconductor substrate 800-1, on which an n-type buffer layer 800-2 is formed, followed by an n-type
In FIG. 8B, a trench pattern is formed by photolithography using PR, and a
Figure 8c is a Si 1 in the trench (803) selectively epitaxially growing a x Ge x (x = 0.0 ~ 0.2) to form a p- type filler 804. Here, the SiGe epilayer is grown using epitaxial growth methods such as RPCVD, UHVCVD, and LPCVD. The SiGe epilayer is doped with boron to precisely control the p-type impurity concentration. The SiGe layer filling the
As shown in FIG. 7C, the structure using the SiGe
As shown in Fig. 8D, the surface of the substrate is planarized using CMP.
8E is a cross-sectional view after the
As shown in FIG. 8F, a gate of a polysilicon film is deposited to form a
FIG. 8G shows a pattern formed by photolithography to implant n + for a source of MOS and p + ion implantation for a diode to form an n + doping layer 808 and a p + doping layer 809 for an ohmic junction. It is the state which formed the junction in high concentration.
An
FIG. 8I is a cross-sectional view of a metal-semiconductor ohmic junction formed by depositing a metal
As shown in FIG. 8J, the back surface of the substrate is mirror polished to adjust the n + substrate layer to a thickness of 30 to 100 μm, and then a metal
As an example of the above, the fabrication process associated with two types of device structures has been described above. However, the SHJ structure provided by the present invention can be used in the fabrication of high voltage semiconductor devices using various compound semiconductors such as Si / SiGe, GaAs / InGaAs, GaN / AlGaN, SiC / SiGeC. Likewise, it is combined with not only MOS devices but also device structures such as Schottky barrier diode (SBD), Fast recovery diode (FRD), Rectifier, MESFET (Metal Semiconductor FET), JFET (Junction FET), HEMT (High Electron Mobility Transistor). Can be used to fabricate high voltage devices.
700 semiconductor substrate 701 n-
703: trench 704: p-type epi (p filler) 705: surface protection oxide film
706 p-channel ion implantation layer
707 polycrystalline gate 708 n + ion implantation layer
709: p + ion implantation layer 710: oxide film 711: contact window
712 source-
800-1: semiconductor substrate 800-2: buffer epi layer 801: n- epi layer
802: surface protection oxide film 803: trench 804-1: p-type primary epi
804-2: p-type secondary epi 805: surface protective oxide film
806 p-channel ion implantation layer
807 polycrystalline gate 808 n + ion implantation layer 809 p + ion implantation layer
810
813: Back side-metal joint
Claims (5)
The second conductive filler is a super hetero epijunction semiconductor device, characterized in that a single epitaxial layer of SiGe or a plurality of epitaxial layers of SiGe having a plurality of compositions to prevent co-doping of impurities. .
And a p + -pn diode is formed in the second conductive filler between the high voltage MOS devices.
(A) forming an n-type silicon epitaxial layer and growing a silicon oxide film on the n + type silicon semiconductor substrate
(B) forming a trench pattern on the surface of the silicon oxide film by photolithography using photoresist (PR), and subsequently etching the oxide film and the n-type silicon epi layer to form a trench
(C) forming a p-type SiGe epi filler in the trench
(D) planarizing the surface on which the p-type SiGe epi filler is formed
(E) After forming a protective oxide film on the planarized substrate, a p-channel pattern is formed by photolithography to ion implant boron, and the ion implanted boron is p-activated through activation and drive-in diffusion. Forming a -type MOS channel layer
(F) depositing a polysilicon thin film to form a gate
(G) forming a pattern by photolithography to form a high concentration layer for ohmic bonding by implanting n + for the source of the MOS and p + ion implantation for the diode ;
(H) depositing an oxide film and then forming a contact window through photolithography and etching
(I) depositing a metal thin film to form a metal-semiconductor ohmic junction
(J) mirror-polishing the back side of the substrate to control the thickness of the n + substrate layer, and then depositing a metal thin film on the back side of the polished substrate to form a metal-semiconductor ohmic junction. Method for manufacturing a high voltage semiconductor device using a junction.
Forming an n-type silicon epitaxial layer on the n + type silicon semiconductor substrate and growing a silicon oxide layer, a super hetero epi junction is formed using an n + type silicon semiconductor substrate and further forming an n-type buffer layer thereon. High voltage semiconductor device manufacturing method using.
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