CN107346738A - The preparation method of super junction power device - Google Patents
The preparation method of super junction power device Download PDFInfo
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- CN107346738A CN107346738A CN201610290915.XA CN201610290915A CN107346738A CN 107346738 A CN107346738 A CN 107346738A CN 201610290915 A CN201610290915 A CN 201610290915A CN 107346738 A CN107346738 A CN 107346738A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000407 epitaxy Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims description 26
- 238000002347 injection Methods 0.000 claims description 13
- 239000007924 injection Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The embodiment of the present invention provides a kind of preparation method of super junction power device, and this method includes：Substrate is provided, and in the surface growing epitaxial layers of the substrate；The first p-type post and the second p-type post are made on said epitaxial layer there；Ion implanting is carried out on the surface of the first p-type post and the second p-type post, to reduce the ion concentration on the first p-type post and the second p-type post surface, the depth of the ion implanting is less than the depth of the first p-type post and the second p-type post；Source region is made in the first p-type post and the second p-type post, the depth of the source region is more than the depth of the ion implanting, less than the depth of the first p-type post and the second p-type post；Gate oxide, grid, dielectric layer and the metal level of making devices.It method provided in an embodiment of the present invention, can avoid because high temperature drives in process in traditional handicraft, the charge unbalance problem between caused p-type post and N-type epitaxy layer, improve the pressure-resistant performance of device.
Description
Technical field
The present embodiments relate to technical field of semiconductors, more particularly to a kind of preparation method of super junction power device.
Background technology
In the prior art, reduce the method for power attenuation by reducing the conducting resistance of semiconductor devices, be partly to lead
Common method in body field.
However, due to inversely, therefore, working as conducting resistance between the breakdown voltage and conducting resistance of semiconductor devices
During reduction, often the breakdown voltage of device is adversely affected.In order to solve this problem, this area introduces superjunction
Power device, it includes the alternate p type island region and N-type region below device active region.Alternate p-type in super junction power device
Area and N-type region are in charge balance state in the ideal situation, and these alternate p type island regions and N-type region are under reverse voltage condition
Mutually exhaust, preferable resistance to sparking energy can be provided for device.
But due to the process that drive in of high temperature can be passed through in making for existing manufacture craft Zhong Ti areas, this can make p type island region and
Counterdiffusion occurs in high temperature environments for N-type region, causes the distribution of charges between p type island region and N-type region uneven, so as to reduce device
Resistance to sparking energy.
The content of the invention
The embodiment of the present invention provides a kind of preparation method of super junction power device, to solve in traditional handicraft due to high temperature
Process is driven in, the problem of charge unbalance between caused p-type post and N-type epitaxy layer.
The preparation method of super junction power device provided in an embodiment of the present invention, including：
Substrate is provided, and in the surface growing epitaxial layers of the substrate；
Make the first p-type post and the second p-type post on said epitaxial layer there, the first p-type post and the second p-type post are mutually from setting
Put；
Ion implanting is carried out on the surface of the first p-type post and the second p-type post, to reduce by first p-type
Ion concentration on post and the second p-type post surface, the depth of the ion implanting are less than the first p-type post and the 2nd P
The depth of type post；
Source region is made in the first p-type post and the second p-type post, the depth of the source region is more than the ion implanting
Depth, less than the depth of the first p-type post and the second p-type post；
Gate oxide, grid, dielectric layer and the metal level of making devices.
The embodiment of the present invention, by after making and forming the first p-type post and the second p-type post, to the first p-type post and the 2nd P
The surface region of type post carries out ion implanting, not only reduces the ion concentration on the first p-type post and the second p-type post surface, reaches
To the purpose of adjusting means cut-in voltage, the manufacture craft in existing manufacture craft Zhong Ti areas is omitted, avoids the making of body area
During, caused by being driven in due to high temperature the problem of charge unbalance between p-type post and N-type epitaxy layer, improve device
Pressure-resistant performance, reduce the cost of manufacture of device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, without having to pay creative labor, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is the schematic flow sheet of the preparation method for the super junction power device that one embodiment of the invention provides；
Fig. 2 is the structural representation that making forms device after the first p-type post and the second p-type post in the embodiment of the present invention；
Fig. 3 is that the device junction after the ion implanting on the first p-type post and the second p-type post surface is completed in the embodiment of the present invention
Structure schematic diagram；
Fig. 4 is that the device architecture schematic diagram formed after source region is made in the embodiment of the present invention；
Fig. 5 is the execution flow chart of steps of step S105 in the embodiment of the present invention；
Fig. 6 is that the device architecture formed after gate oxide, grid, dielectric layer and metal level is made in the embodiment of the present invention
Schematic diagram.
Reference：
10- substrates；20- epitaxial layer 30- gate oxides；
40- grids；50- dielectric layers；60- metal levels；
21- the first p-type posts；22- the second p-type posts；23- injection regions；
The source regions of 24- first；The source regions of 25- second；The source regions of 26- the 3rd；
The source regions of 27- the 4th.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The term " comprising " and " having " of description and claims of this specification and their any deformation, it is intended that
Be to cover it is non-exclusive include, for example, the device for the process or structure for containing series of steps is not necessarily limited to clearly arrange
It is that those structures or step for going out but may include are not listed clearly or for the intrinsic other steps of these processes or device
Rapid or structure.
Fig. 1 is the schematic flow sheet of the preparation method for the super junction power device that one embodiment of the invention provides, such as Fig. 1 institutes
Show, the preparation method of super junction power device provided in an embodiment of the present invention, comprise the following steps：
Step S101, substrate 10 is provided, and in the surface growing epitaxial layers 20 of the substrate 10.
Specifically, the substrate 10 provided in the present embodiment, the preferably N-type substrate doped with N+ ions.Epitaxial layer 20 is
Doped with the N-type epitaxy layer of N- ions.The growing method of the present embodiment epitaxial layers is no longer superfluous herein similarly to the prior art
State.
Step S102, the first p-type post 21 and the second p-type post 22, the first p-type post 21 are made on the epitaxial layer 20
With the phase of the second p-type post 22 from setting.
Fig. 2 is the structural representation that making forms device after the first p-type post and the second p-type post in the embodiment of the present invention.Tool
Body, the preparation method of structure shown in Fig. 2 is specifically as follows：
First, first groove and second groove are etched on epitaxial layer 20 by etching technics, wherein, first groove and
The depth of two grooves is less than the depth of epitaxial layer 20.After first groove and second groove is formed, then by epitaxy technique the
The first p-type post 21 doped with P+ ions is formed in one groove, and the second p-type doped with P+ ions is formed in second groove
Post 22, ultimately form structure as shown in Figure 2.Wherein, the etching technics and epitaxy technique employed in the present embodiment, with showing
There is the related process in technology is similar to repeat no more herein.
Further, in order to reduce the volume of device, the cost of manufacture of device is saved, preferably by the first P in the present embodiment
The distance between p-type post 22 of type post 21 and second is arranged in traditional handicraft 0.5 times of distance between p-type post, by the first p-type post
21 and second the width of p-type post 22 be arranged to 1.2 times or so of p-type post width in traditional handicraft.Such as p-type post in traditional handicraft
The distance between be 6 microns, then the distance between the first p-type post 21 and the second p-type post 22 are arranged to 3 microns in embodiment.
The width of p-type post is 5 microns in traditional handicraft, then the width of the first p-type post 21 and the second p-type post 22 is arranged into 6-7 microns.
Step S103, ion implanting is carried out on the surface of the first p-type post 21 and the second p-type post 22, is formed
Injection region 23, to reduce the ion concentration on the first p-type post 21 and the surface of the second p-type post 22, the ion implanting
Depth be less than the depth of the first p-type post 21 and the second p-type post 22.
Fig. 3 is that the device junction after the ion implanting on the first p-type post and the second p-type post surface is completed in the embodiment of the present invention
Structure schematic diagram.Specifically, shown in Fig. 3 can be by autoregistration injection technology in the first p-type post 21 and the table of the second p-type post 22
Ion implanting is carried out on face, wherein, the ion of injection is preferably P- ions, and the implantation dosage of the P- ions is preferably 1 × 1014
~8 × 1014, Implantation Energy is preferably 50KeV.
In the present embodiment, used autoregistration injection technology similarly to the prior art, repeats no more herein.
Step S104, source region is made in the first p-type post 21 and the second p-type post 22, the depth of the source region is more than
The depth of the ion implanting, less than the depth of the first p-type post and the second p-type post.
Fig. 4 is that the device architecture schematic diagram formed after source region is made in the embodiment of the present invention.As shown in figure 4, the present embodiment
In, two source regions are included respectively in the first p-type post 21 and in the second p-type post 22, wherein, the source region formed in the first p-type post 21
For the first source region 24 and the second source region 25, the interior source region formed of the second p-type post is respectively the 3rd source region 26 and the 4th source region 27.Its
In, from setting, the depth of the first source region 24 and the second source region 25 is more than injection region 23 for the first source region 24 and the phase of the second source region 30
Depth, less than the depth of the first p-type post 21.3rd source region 26 and the phase of the 4th source region 27 are from setting, the 3rd source region 26 and
The depth of four source regions 27 is more than the depth of injection region 23, less than the depth of the second p-type post 22.
Further, in the present embodiment, the first source region 24, the second source region 25, the 3rd source region 26 and the 4th source region 27,
To be formed with being made by autoregistration injection technology.The ion of autoregistration injection is N+ ions.
Self-registered technology employed in the present embodiment repeats no more herein similarly to the prior art.
Step S105, the gate oxide 30 of making devices, grid 40, dielectric layer 50 and metal level 60.
Fig. 5 is the execution flow chart of steps of step S105 in the embodiment of the present invention.Fig. 6 is to make shape in the embodiment of the present invention
Into the device architecture schematic diagram after gate oxide, grid, dielectric layer and metal level.As shown in figure 5, step in the present embodiment
S105 execution step includes：
Step S1051, the gate oxide 30 and polysilicon layer are grown successively on the surface of the device.
The executive mode of this step repeats no more herein similarly to the prior art.
Step S1052, the polysilicon layer is performed etching by photoetching process, forms the grid 40 of the device.
Specifically, the part on the first p-type post 21 and the surface of the second p-type post 22 is pointed under the coverage of photoresist first
The polysilicon layer in region performs etching, and after the polysilicon layer on the region is etched away completely, removes photoresist, forms grid
Pole 40.
Step S1053, the dielectric layer 50 is grown on the surface of the device, and by etching technics to the medium
Layer 50 and the gate oxide 30 perform etching, and form the first contact hole positioned at the surface of the first p-type post 21 and position
The second contact hole in the surface of the second p-type post 22.
The technique of this step the first contact hole of making and the second contact hole similarly to the prior art, repeats no more herein.
Step S1054, metal is deposited on the surface of the device, forms the metal level 60.
In this step, the preparation method of metal level in the prior art can be used to make metal level 60, herein
Repeat no more.
The present embodiment, by after making and forming the first p-type post and the second p-type post, to the first p-type post and the second p-type post
Surface region carry out ion implanting, not only reduce the ion concentration on the first p-type post and the second p-type post surface, reach tune
The purpose of device cut-in voltage is saved, the manufacture craft in existing manufacture craft Zhong Ti areas is omitted, avoids body area manufacturing process
In, caused by being driven in due to high temperature the problem of charge unbalance between p-type post and N-type epitaxy layer, improve the pressure-resistant of device
Performance, reduce the cost of manufacture of device.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than its limitations；To the greatest extent
The present invention is described in detail with reference to foregoing embodiments for pipe, it will be understood by those within the art that：Its according to
The technical scheme described in foregoing embodiments can so be modified, either which part or all technical characteristic are entered
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is departed from various embodiments of the present invention technology
The scope of scheme.
Claims (6)
- A kind of 1. preparation method of super junction power device, it is characterised in that including：Substrate is provided, and in the surface growing epitaxial layers of the substrate；The first p-type post and the second p-type post are made on said epitaxial layer there, and the first p-type post and the second p-type post are mutually from setting；Ion implanting is carried out on the surface of the first p-type post and the second p-type post, injection region is formed, with described in reduction Ion concentration on first p-type post and the second p-type post surface, the depth of the injection region be less than the first p-type post and The depth of second p-type post；Source region is made in the first p-type post and the second p-type post, the depth of the source region is more than the depth of the ion implanting Degree, less than the depth of the first p-type post and the second p-type post；Gate oxide, grid, dielectric layer and the metal level of making devices.
- 2. according to the method for claim 1, it is characterised in that described to make the first p-type post and the on said epitaxial layer there Two p-type posts, including：First groove and second groove, the first groove and second ditch are etched by etching technics on said epitaxial layer there The depth of groove is less than the depth of the epitaxial layer；The first p-type post is formed in the first groove by epitaxy technique, described is formed in the second groove Two p-type posts.
- 3. according to the method for claim 2, it is characterised in that the width of the first p-type post and the second p-type post is 6 microns or 7 microns；The distance between the first p-type post and the second p-type post are 3 microns.
- 4. according to the method described in claim requirement 1, it is characterised in that the ion of the ion implanting is P- ions, described The implantation dosage of P- ions is 1 × 1014~8 × 1014, Implantation Energy 50KeV.
- 5. according to the method for claim 1, it is characterised in that described to be made in the first p-type post and the second p-type post Source region, including：First source region and the second source region are made in the first p-type post by self-registered technology, and in the second p-type post Make the 3rd source region and the 4th source region；Wherein, first source region and second source region are mutually from setting, the depth of first source region and second source region More than the depth of the injection region, less than the depth of the first p-type post；Mutually from setting, the depth of the 3rd source region and the 4th source region is more than institute for 3rd source region and the 4th source region The depth of injection region is stated, less than the depth of the second p-type post.
- 6. according to the method for claim 1, it is characterised in that the gate oxide of the making devices, grid, dielectric layer with And metal level, including：Grow the gate oxide and polysilicon layer successively on the surface of the device；The polysilicon layer is performed etching by photoetching process, forms the grid of the device；The dielectric layer is grown on the surface of the device, and by etching technics to the dielectric layer and the gate oxide Perform etching, formed positioned at the first contact hole of the first p-type post surface and positioned at the second p-type post surface The second contact hole；Metal is deposited on the surface of the device, forms the metal level.
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| CN201610290915.XA CN107346738B (en) | 2016-05-04 | 2016-05-04 | Manufacturing method of super junction power device |
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|---|---|---|---|
| CN201610290915.XA CN107346738B (en) | 2016-05-04 | 2016-05-04 | Manufacturing method of super junction power device |
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| CN107346738B CN107346738B (en) | 2020-03-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341827A (en) * | 2018-12-18 | 2020-06-26 | 深圳尚阳通科技有限公司 | N-type super junction device and manufacturing method thereof |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070013000A1 (en) * | 2005-07-12 | 2007-01-18 | Masaki Shiraishi | Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter |
| US20100032752A1 (en) * | 2008-08-08 | 2010-02-11 | Sony Corporation | Semiconductor device and method of manufacturing the same |
| KR101167530B1 (en) * | 2012-01-05 | 2012-07-20 | 주식회사 시지트로닉스 | Super heterojunction semiconductor device structure and its fabrication method |
| CN103123898A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Manufacturing method for super junction double diffusion metal-oxide semiconductor device |
| US8999789B2 (en) * | 2013-05-22 | 2015-04-07 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFETs with short terminations |
| CN104517855A (en) * | 2014-09-11 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Super-junction semiconductor device manufacturing method |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN105336777A (en) * | 2014-07-11 | 2016-02-17 | 北大方正集团有限公司 | Super-junction MOS device and manufacturing method thereof |
| CN105428397A (en) * | 2015-11-17 | 2016-03-23 | 深圳尚阳通科技有限公司 | Super-junction device and manufacturing method therefor |
| CN105448997A (en) * | 2016-01-13 | 2016-03-30 | 无锡新洁能股份有限公司 | Super-junction MOS device for improving reverse recovery feature and avalanche capability, and manufacturing method thereof |
-
2016
- 2016-05-04 CN CN201610290915.XA patent/CN107346738B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070013000A1 (en) * | 2005-07-12 | 2007-01-18 | Masaki Shiraishi | Semiconductor device and manufacturing method of the same, and non-isolated DC/DC converter |
| US20100032752A1 (en) * | 2008-08-08 | 2010-02-11 | Sony Corporation | Semiconductor device and method of manufacturing the same |
| CN103123898A (en) * | 2011-11-21 | 2013-05-29 | 上海华虹Nec电子有限公司 | Manufacturing method for super junction double diffusion metal-oxide semiconductor device |
| KR101167530B1 (en) * | 2012-01-05 | 2012-07-20 | 주식회사 시지트로닉스 | Super heterojunction semiconductor device structure and its fabrication method |
| US8999789B2 (en) * | 2013-05-22 | 2015-04-07 | Force Mos Technology Co., Ltd. | Super-junction trench MOSFETs with short terminations |
| CN105336777A (en) * | 2014-07-11 | 2016-02-17 | 北大方正集团有限公司 | Super-junction MOS device and manufacturing method thereof |
| CN104517855A (en) * | 2014-09-11 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Super-junction semiconductor device manufacturing method |
| CN105244369A (en) * | 2015-09-16 | 2016-01-13 | 重庆平伟实业股份有限公司 | Super junction VDMOSFET (Vertical Double-diffused MOSFET) preparation method and device formed by using same |
| CN105428397A (en) * | 2015-11-17 | 2016-03-23 | 深圳尚阳通科技有限公司 | Super-junction device and manufacturing method therefor |
| CN105448997A (en) * | 2016-01-13 | 2016-03-30 | 无锡新洁能股份有限公司 | Super-junction MOS device for improving reverse recovery feature and avalanche capability, and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111341827A (en) * | 2018-12-18 | 2020-06-26 | 深圳尚阳通科技有限公司 | N-type super junction device and manufacturing method thereof |
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