CN106298479B - A kind of the knot terminal expansion structure and its manufacturing method of power device - Google Patents
A kind of the knot terminal expansion structure and its manufacturing method of power device Download PDFInfo
- Publication number
- CN106298479B CN106298479B CN201510318913.2A CN201510318913A CN106298479B CN 106298479 B CN106298479 B CN 106298479B CN 201510318913 A CN201510318913 A CN 201510318913A CN 106298479 B CN106298479 B CN 106298479B
- Authority
- CN
- China
- Prior art keywords
- groove
- expansion structure
- silicon oxide
- knot terminal
- terminal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 65
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 38
- 239000003989 dielectric material Substances 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000002347 injection Methods 0.000 description 15
- 239000007924 injection Substances 0.000 description 15
- 238000000407 epitaxy Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 description 2
- 102000013275 Somatomedins Human genes 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000034655 secondary growth Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention relates to the knot terminal expansion structures and its manufacturing method of a kind of power device, the power device includes active region, knot terminal expansion structure, end ring region and street area, wherein the knot terminal expansion structure is set to the periphery of the active area, the cut-off ring region is set to the periphery of the knot terminal expansion structure, the street area is set to the periphery of the cut-off ring region, the knot terminal expansion structure includes substrate layer, epitaxial layer and silicon oxide layer, the epitaxial layer includes multiple ion implanted regions, from the active region to the cut-off ring region direction, the depth of the multiple ion implanted region, width and ion concentration are gradually reduced.The gradual change of the depth and ion concentration of the ion implanted region of the knot terminal expansion structure of power device of the invention can be improved the voltage dividing ability of power device, reduce influence of the interface charge of silicon oxide layer to power device surface potential.
Description
Technical field
The present invention relates to a kind of knot terminal expansion structure of power device, the knot terminal of specifically a kind of power device extends
Structure and its manufacturing method.
Background technique
The most important performance of power device is exactly blocking voltage, and device can connect by design in PN junction, metal-semiconductor
It touches, bears high pressure on the depletion layer at the interface MOS, with the increase of applied voltage, depletion layer electric field strength also be will increase, final super
It crosses material limits and avalanche breakdown occurs.Increase in device edge depletion region electric field curvature, will lead to electric field ratio die internal
Greatly, die edge avalanche breakdown can occur earlier than die internal during voltage is raised, in order to maximize the performance of device,
It needs to design partial-pressure structure in device edge, reduces the curvature of active area (cellular region) edge PN junction, be laterally extended depletion layer,
The voltage endurance capability for enhancing horizontal direction makes the edge of device and internal while puncturing.End ring in partial-pressure structure and scribing
Between slot region, it is distributed in the outermost of chip, is indispensable on the device that high reliability request and module encapsulate.
Junction terminal extension technology is one of the partial-pressure structure generallyd use the most in current power device.Its simple process,
It can be diffuseed to form together with active region, without increase processing step.Junction terminal extension technology is the main knot in active region
Around the one p type island region domain that is lightly doped of circle of production.When main knot is reverse-biased, knot terminal extended area can be depleted simultaneously.At this time
It is equivalent to and introduces negative electrical charge inside the depletion region of drift region, these negative electrical charges extend depletion region, and itself can also be inhaled
A part of electric field is received, to reduce the electric field spike of main knot edge, and then improves the breakdown characteristics of device.
The common knot terminal expansion structure signal of power device at present is as shown in Figure 1, wherein 1 indicate silicon wafer, 2 indicate N
Type epitaxial layer, 3 indicate main knot, and 4 indicate P-type ion injection region, and 5 indicate N-type injection region.The surface oxide layer of this structure is frequent
There are some impurity, its surface is caused to generate interface charge, to can be produced a very large impact to power device surface potential, influenced
Effect is divided, so that breakdown voltage be made to reduce.
Summary of the invention
The technical problem to be solved by the present invention is to the interface charges of silicon oxide layer in the prior art to power device surface
Potential has a significant impact, to influence to divide effect, reduces breakdown voltage.
Multiple ion implanted regions are set in knot terminal expansion structure for this purpose, the invention proposes one kind, and from institute
Active region is stated to the cut-off ring region direction, the depth and ion concentration of multiple ion implanted region are gradually reduced, thus
Influence of the interface charge to power device surface potential can be reduced, while improving one kind of power device surface breakdown voltage
The knot terminal expansion structure of power device and and its manufacturing method.
The invention discloses a kind of knot terminal expansion structure of power device, the power device includes active region, knot
Termination extension structure, cut-off ring region and street area, wherein the knot terminal expansion structure is set to the active region
Periphery, the cut-off ring region is set to the periphery of the knot terminal expansion structure, and the street area is set to described
End the periphery of ring region,
The knot terminal expansion structure includes substrate layer, epitaxial layer and silicon oxide layer, and the epitaxial layer includes multiple ions
Injection region, from the active region to the cut-off ring region direction, the depth and ion concentration of the multiple ion implanted region
It is gradually reduced.
Preferably, the silicon oxide layer in the knot terminal expansion structure is provided with multiple corresponding with the ion implanted region
Groove, and the width of each groove is gradually reduced from active area to the cut-off ring region direction.
Preferably, dielectric material is filled in each groove.
Preferably, the ionic type for including in the ion in the ion implanted region and the epitaxial layer is not identical.
The present invention also provides a kind of method of knot terminal expansion structure for manufacturing power device, the power device includes
Source region, knot terminal expansion structure, cut-off ring region and street area, wherein the knot terminal expansion structure be set to it is described
The periphery of active region, the cut-off ring region are set to the periphery of the knot terminal expansion structure, and the street area is set
It is placed in the periphery of the cut-off ring region, this method comprises:
Formation silicon oxide layer on the epitaxial layer of predetermined knot terminal expansion structure；
Multiple grooves are formed on the silicon oxide layer, from active area to cut-off ring region direction, the multiple groove
Width is gradually reduced；
Carry out ion implanting, then filled media material, the ion implanting and the filling in each groove
Dielectric material alternately so that the small groove groove bigger than width of width first filled by dielectric material it is full；
After the last time ion implanting, full dielectric material will be filled in each groove and is covered with dielectric material
Cover the surface of the silicon oxide layer.
Preferably, described to form multiple grooves on the silicon oxide layer and include:
Photoresist exposure mask is formed on the silicon oxide layer of the predetermined knot terminal expansion structure, wherein by active region
To cut-off ring region direction, the width of multiple etching windows of not set photoresist is gradually reduced；
Silicon oxide layer described in dry etching forms a groove in each etching window, the bottom of the groove and
The epitaxial layer contact.
Preferably, the ion implanting carries out after removing photoresist for the first time.
Preferably, the filled media material includes:
Continuous dielectric material is grown in the surface of the silicon oxide layer and the groove, then etches away the oxidation
The dielectric material on the surface of silicon layer and the bottom surface of the groove, carry out every time the filled media material all fill up this time before not by
The groove of the minimum widith filled up.
Preferably, the etching window is not less than three.
Preferably, the number of the filled media material is no less than three times.
By using the knot terminal expansion structure of power device disclosed in this invention, the knot terminal expansion structure includes
Substrate layer, epitaxial layer and silicon oxide layer, the epitaxial layer include that multiple ions enter area, from the active region to the cut-off ring
Region direction, the depth and width and ion concentration of the multiple ion implanted region are gradually reduced.The ion of knot terminal of the present invention is infused
The gradual change for entering the depth and width and ion concentration in area can be improved the voltage dividing ability of power device, reduce the interface of silicon oxide layer
Influence of the charge to power device surface potential.
Detailed description of the invention
The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, and attached drawing is schematically without that should manage
Solution is carries out any restrictions to the present invention, in the accompanying drawings:
Fig. 1 is the knot terminal expansion structure schematic diagram of power device in the prior art；
Fig. 2 shows the planar structure schematic diagrams of the power device of the embodiment of the present invention one；
Fig. 3 shows the knot terminal expansion structure schematic diagram of the power device of the embodiment of the present invention one；
The process that Fig. 4 (a)~Fig. 4 (j) shows the knot terminal expansion structure manufacturing method of the embodiment of the present invention two is shown
It is intended to.
Specific embodiment
Below in conjunction with attached drawing, embodiments of the present invention is described in detail.
Embodiment one:
Fig. 2 is the planar structure schematic diagram of power device provided in an embodiment of the present invention, as shown in Fig. 2, the power device
Part includes active region 11, knot terminal expansion structure 12, cut-off ring region 13 and street area 14, wherein the knot terminal expands
Structure setting is opened up in the periphery of the active region, the cut-off ring region is set to the periphery of the knot terminal expansion structure,
The street area is set to the periphery of the cut-off ring region.
Fig. 3 is the structural schematic diagram of knot terminal expansion structure one embodiment of power device provided by the invention.Such as figure
3, structure shown in the present embodiment is as follows:
The knot terminal expansion structure includes substrate layer, and substrate layer is, for example, silicon wafer 1 herein.In the silicon wafer 1
Surface be equipped with epitaxial layer 2, on the surface of epitaxial layer 2 be equipped with silicon oxide layer 7；Epitaxial layer 2 includes multiple ion implanted regions
4, in active region to cut-off ring region, the depth and ion concentration of multiple ion implanted regions 4 are gradually reduced.Here the class of ion
The ionic type for including in type and epitaxial layer 2 is related, i.e., if epitaxial layer 2 be N-type epitaxy layer, ion implanted region 4 be p-type from
Sub- injection region, if the type of epitaxial layer 2 is p-type epitaxial layer, ion implanted region 4 is N-type ion implanted region.
In the present embodiment, epitaxial layer is N-type epitaxy layer 2, and the ion implanted region is P-type ion injection region 4.In N-type
2 surface of epitaxial layer is equipped with silicon oxide layer 7.The silicon oxide layer 7 is provided with multiple corresponding with the P-type ion injection region 4
Groove 91, and the width of each groove 91 from active area to cut-off ring region direction be gradually reduced.It is filled out in each groove 91
Filled with dielectric material.It should be noted that if these 91 width of groove are generally in the trend being gradually reduced, such as its
In two adjacent groove widths can be identical, that is to say, that the depth and ion concentration of P-type ion injection region 4 are only required in
Generally in the variation tendency being gradually reduced.
Further, knot terminal expansion structure further includes the dielectric layer 9 by being made of dielectric material.Dielectric material is oxidation
Silicon or silicon nitride.
The knot terminal expansion structure of power device of the invention passes through the dense with P-type ion of the depth of P-type ion injection region
Degree, makes the ion concentration on power device surface can be improved the voltage dividing ability of power device, reduces the area of power device, reduces
The cost of power device.
Embodiment two:
The present invention also provides a kind of knot terminal manufacturing methods, to solve the boundary on power device surface in the prior art
Surface charge has an impact power device surface potential, influences the technical issues of dividing effect.The manufacturing method includes:
Step 1, the formation silicon oxide layer as shown in Fig. 4 (a), in the N-type epitaxy layer 2 of predetermined knot terminal expansion structure
7。
The epitaxial layer is N-type epitaxy layer 2 in the present embodiment, is not limited to N-type epitaxy layer in practical manufacturing process,
It can be p-type epitaxial layer.
Step 2 forms photoetching on the silicon oxide layer 7 of the predetermined knot terminal expansion structure as shown in Fig. 4 (b)
Glue exposure mask 6, wherein from active region to cut-off ring region direction, the width of multiple etching windows of not set photoresist gradually subtracts
It is small.
Step 3, as shown in Fig. 4 (c), silicon oxide layer 7 described in dry etching form one in each etching window
Ditch 91, the bottom of the groove and the N-type epitaxy layer 2 contact.
Step 4 etches away the photoresist as shown in Fig. 4 (d), and to the N-type epitaxy layer 2 of 6 lower section of silicon oxide layer into
The injection of row first time P-type ion.In the present embodiment, since epitaxial layer 2 uses N-type epitaxy layer, so here in ion implanting
Region injecting p-type ion according to the ionic type of epitaxial layer, determines ion implanted regions in other embodiments of the invention
The ionic type of injection, for example, injecting N-type ion in ion implanted regions for p-type epitaxial layer.To under groove
It is rectangular at corresponding ion implanted region 4.
Step 5 grows continuous dielectric material on 7 surface of silicon oxide layer, keeps dielectric material complete as shown in Fig. 4 (e)
Cover upper surface and the groove side wall of the silicon oxide layer 7.The dielectric material is silicon oxide or silicon nitride.
Step 6 etches away the medium material of 7 upper surface of silicon oxide layer and the channel bottom as shown in Fig. 4 (f)
Material, retains the dielectric material on the trenched side-wall, to form medium side wall 8.Retain the groove in the embodiment of the present invention
Dielectric material on side wall is the width for adjusting the groove to form the purpose of medium side wall 8.
Step 7, as shown in Fig. 4 (g), injecting p-type ion in the groove.After the step 6, the groove
Width narrow, after re-injecting P-type ion, the ion concentration of a P-type ion injection region 4 will increase, due to the width of groove
Spending from active area to cut-off region direction is in the trend being gradually reduced, then the P-type ion concentration of P-type ion injection region 4 is by active
It area also will be in the trend being gradually reduced to cut-off region direction.The width of the groove can according to implement P-type ion concentration come
Adjustment then will for example, if only carrying out an injecting p-type ion, can meet the requirements for groove the smallest for width
The width of the smallest groove of width is set to the thickness less than or equal to 2 times of dielectric layers, as first secondary growth Jie of progress
When material, the dielectric material expires the smallest trench fill of the width, and corresponding P-type ion injection region will no longer
Injecting p-type ion.
Step 8 in the 7 surface somatomedin material of silicon oxide layer, keeps the dielectric material complete as shown in Fig. 4 (h)
The upper surface of silicon oxide layer 7 described in all standing simultaneously forms medium side wall 8.
Step 9 etches the dielectric material of silicon oxide layer 7 upper surface and channel bottom as shown in Fig. 4 (i), retains
Dielectric material on trenched side-wall, to form medium side wall 8.
Step 10, as shown in Fig. 4 (j), injecting p-type ion in the groove.
Step 11 makes the dielectric material that the oxygen be completely covered in the 7 surface somatomedin material of silicon oxide layer
The upper surface of SiClx layer 7 simultaneously forms medium side wall 8.
Then ion implanting is carried out again and forms dielectric layer again, and etching forms medium side wall again, so repeats,
It is whole to form knot as shown in Figure 3 until the dielectric layer 9 that all grooves are filled up by dielectric material, and reservation last time is formed
Hold expansion structure
Wherein groove number is preferably not less than 3, and ion implanting number is preferably not less than 3.
In conclusion the present invention is by the silicon oxide layer 7 of the knot terminal expansion structure in power device to cut-off ring direction
The groove that etching width is gradually reduced, and be repeatedly formed dielectric sidewall on trenched side-wall and carry out p-type injection, make P-type ion
Injection region forms the depth and width and ion concentration of gradual change, to improve the voltage dividing ability of power device, reduces device area,
Device cost is reduced, device performance is improved.And present invention only requires a photoetching, simple process, lower production costs.
Although the embodiments of the invention are described in conjunction with the attached drawings, but those skilled in the art can not depart from this hair
Various modifications and variations are made in the case where bright spirit and scope, such modifications and variations are each fallen within by appended claims
Within limited range.
Claims (5)
1. a kind of manufacturing method of the knot terminal expansion structure of power device, the power device includes active region, knot terminal
Expansion structure, cut-off ring region and street area, wherein the knot terminal expansion structure is set to the outer of the active region
It encloses, the cut-off ring region is set to the periphery of the knot terminal expansion structure, and the street area is set to the cut-off
The periphery of ring region, which is characterized in that this method comprises:
Silicon oxide layer is formed on the epitaxial layer of predetermined knot terminal expansion structure；
Multiple grooves are formed on the silicon oxide layer, from active region to cut-off ring region direction, the width of the multiple groove
Degree is gradually reduced；
Ion implanting is carried out, then filled media material, the ion implanting and the filled media in each groove
Material alternately so that the small groove groove bigger than width of width first filled by dielectric material it is full；
After the last time ion implanting, full dielectric material will be filled in each groove and cover institute with dielectric material
State the surface of silicon oxide layer；
The filled media material includes:
Continuous dielectric material is grown in the surface of the silicon oxide layer and the groove, then etches away the silicon oxide layer
Surface and the groove bottom surface dielectric material, carry out every time the filled media material all fill up this time before be not filled
Minimum widith the groove.
2. the manufacturing method according to claim 1, which is characterized in that described to form multiple grooves on the silicon oxide layer
Include:
On the silicon oxide layer of the predetermined knot terminal expansion structure formed photoresist exposure mask, wherein from active region to cut
The width in only ring region direction, multiple etching windows of not set photoresist is gradually reduced；
Silicon oxide layer described in dry etching forms a groove in each etching window, the bottom of the groove and described
Epitaxial layer contact.
3. manufacturing method according to claim 2, which is characterized in that the ion implanting is after removing photoresist for the first time
It carries out.
4. the manufacturing method according to any one of Claims 2 or 3, which is characterized in that
The etching window is not less than three.
5. manufacturing method according to claim 4, which is characterized in that
The number of the filled media material is no less than three times.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510318913.2A CN106298479B (en) | 2015-06-11 | 2015-06-11 | A kind of the knot terminal expansion structure and its manufacturing method of power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510318913.2A CN106298479B (en) | 2015-06-11 | 2015-06-11 | A kind of the knot terminal expansion structure and its manufacturing method of power device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106298479A CN106298479A (en) | 2017-01-04 |
| CN106298479B true CN106298479B (en) | 2019-05-07 |
Family
ID=57659614
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510318913.2A Active CN106298479B (en) | 2015-06-11 | 2015-06-11 | A kind of the knot terminal expansion structure and its manufacturing method of power device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106298479B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108063159B (en) * | 2017-12-08 | 2020-09-18 | 上海芯龙半导体技术股份有限公司 | Terminal structure of semiconductor power device, semiconductor power device and manufacturing method thereof |
| CN108110042A (en) * | 2017-12-13 | 2018-06-01 | 深圳市晶特智造科技有限公司 | Super-junction structure of semiconductor power device and preparation method thereof |
| CN111146273B (en) * | 2019-12-27 | 2021-08-24 | 西安电子科技大学 | Junction terminal extension terminal structure with adjustable intermediate layer coverage and preparation method thereof |
| CN112310195B (en) * | 2020-09-27 | 2022-09-30 | 东莞南方半导体科技有限公司 | Stepped SiC groove field limiting ring terminal structure, preparation method and device thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270346A (en) * | 1988-04-22 | 1989-10-27 | Fuji Electric Co Ltd | Semiconductor device |
| CN102610635A (en) * | 2012-03-26 | 2012-07-25 | 大连理工大学 | High-density graded field limiting ring structure and manufacturing process thereof |
| JP2014038937A (en) * | 2012-08-16 | 2014-02-27 | Mitsubishi Electric Corp | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006073740A (en) * | 2004-09-01 | 2006-03-16 | Toshiba Corp | Semiconductor device and its manufacturing method |
| JP5515922B2 (en) * | 2010-03-24 | 2014-06-11 | 富士電機株式会社 | Semiconductor device |
-
2015
- 2015-06-11 CN CN201510318913.2A patent/CN106298479B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01270346A (en) * | 1988-04-22 | 1989-10-27 | Fuji Electric Co Ltd | Semiconductor device |
| CN102610635A (en) * | 2012-03-26 | 2012-07-25 | 大连理工大学 | High-density graded field limiting ring structure and manufacturing process thereof |
| JP2014038937A (en) * | 2012-08-16 | 2014-02-27 | Mitsubishi Electric Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106298479A (en) | 2017-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102769037B (en) | Structure for reducing surface electric field and LDMOS device | |
| CN104733531A (en) | Dual oxide trench gate power mosfet using oxide filled trench | |
| US20100200915A1 (en) | Lateral trench mosfet having a field plate | |
| JP2008103683A (en) | Semiconductor device having space-saving edge structure | |
| CN108091573B (en) | Manufacturing method of shielded gate trench MOSFET ESD structure | |
| CN101872724A (en) | Manufacturing method of super junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) | |
| KR101955055B1 (en) | Power semiconductor device and method of fabricating the same | |
| CN103178093B (en) | The structure of high-voltage junction field-effect transistor and preparation method | |
| KR20170030122A (en) | Power Semiconductor Device | |
| CN106298479B (en) | A kind of the knot terminal expansion structure and its manufacturing method of power device | |
| US9520463B2 (en) | Super junction semiconductor device including edge termination | |
| CN103050541A (en) | Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof | |
| US20100044839A1 (en) | Semiconductor device and manufacturing method thereof | |
| CN105655402A (en) | Low-voltage super-junction MOSFET (metal-oxide-semiconductor field effect transistor) terminal structure and method for manufacturing same | |
| CN110797389A (en) | MOSFET device with shielded region and method of making the same | |
| CN105575781A (en) | Manufacturing method for trench type super junction | |
| JP6391136B2 (en) | High voltage diode | |
| CN103199018B (en) | Manufacturing method of field blocking type semiconductor device and device structure | |
| US9431286B1 (en) | Deep trench with self-aligned sinker | |
| KR100902585B1 (en) | Trench gate mosfet and method for fabricating of the same | |
| CN104103693A (en) | U-groove power device and manufacturing method thereof | |
| US11430780B2 (en) | TVS device and manufacturing method therefor | |
| CN108447896B (en) | Manufacturing method of terminal structure of silicon carbide power device | |
| CN107994067B (en) | Semiconductor power device, terminal structure of semiconductor power device and manufacturing method of terminal structure | |
| CN108063159B (en) | Terminal structure of semiconductor power device, semiconductor power device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220727 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, fangzheng building, 298 Fu Cheng Road, Beijing, Haidian District Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |