CN108447896B - Manufacturing method of terminal structure of silicon carbide power device - Google Patents

Manufacturing method of terminal structure of silicon carbide power device Download PDF

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CN108447896B
CN108447896B CN201810307901.3A CN201810307901A CN108447896B CN 108447896 B CN108447896 B CN 108447896B CN 201810307901 A CN201810307901 A CN 201810307901A CN 108447896 B CN108447896 B CN 108447896B
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region
junction
sacrificial layer
silicon carbide
doped region
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CN108447896A (en
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颜世桃
郑渚
杨彬
李程
丁庆
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Shenzhen Huaxun Ark Photoelectric Technology Co ltd
Shenzhen Institute of Terahertz Technology and Innovation
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China Communication Technology Co Ltd
Shenzhen Institute of Terahertz Technology and Innovation
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Priority to PCT/CN2019/080921 priority patent/WO2019196700A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

The invention relates to a manufacturing method of a terminal structure of a silicon carbide power device, which comprises the following steps: providing a silicon carbide substrate prepared with a main junction; forming a first doped region in the silicon carbide substrate adjacent to the main junction; forming a first gradually-changing region with sequentially increasing ion concentration along the direction far away from the main junction in the first doping region; on the basis of the same junction terminal window, performing reverse type ion implantation on the first gradient area at the same time to form a second gradient area with sequentially decreasing ion concentration along the direction far away from the main junction; the ion types doped in the silicon carbide substrate, the first doped region and the first gradient region are a first conductive type, and the ion types doped in the main junction and the second gradient region are a second conductive type. The method has simple process, and the terminal structure of the silicon carbide power device prepared by the method is not easy to generate electric field concentration.

Description

Manufacturing method of terminal structure of silicon carbide power device
Technical Field
The invention relates to the field of manufacturing of silicon carbide power devices, in particular to a method for manufacturing a terminal structure of a silicon carbide power device.
Background
Silicon carbide (SiC) is a semiconductor material with high electric field strength, thermal conductivity, forbidden bandwidth and saturation drift velocity, and is widely used in working environments requiring high switching frequency and high junction temperature.
Generally, silicon carbide power devices are prone to electric field concentration when subjected to high reverse voltages. In the conventional method, the problem is overcome by etching the silicon carbide material and forming an ion concentration gradient region on the junction terminal by adopting a junction terminal extension technology.
However, in the ion concentration gradient region formed by the conventional method, since each concentration region is formed separately, the ion concentration variation tendency is too steep, and electric field concentration is likely to occur in the region where the ion concentration is varied.
Disclosure of Invention
Therefore, there is a need for a method for manufacturing a terminal structure of a silicon carbide power device, so as to eliminate the silicon carbide etching process, reduce the process difficulty, and prevent electric field concentration of the produced device.
A method of fabricating a termination structure for a silicon carbide power device, the method comprising:
providing a silicon carbide substrate prepared with a main junction;
forming a first doped region in the silicon carbide substrate adjacent to the main junction;
forming a first gradually-changing region with sequentially increasing ion concentration along the direction far away from the main junction in the first doping region;
on the basis of the same junction terminal window, performing reverse type ion implantation on the first gradient area at the same time to form a second gradient area with sequentially decreasing ion concentration along the direction far away from the main junction;
the ion types doped in the silicon carbide substrate, the first doped region and the first gradient region are a first conductive type, and the ion types doped in the main junction and the second gradient region are a second conductive type.
In one embodiment, the forming of the first graded region in the first doped region with the ion concentration increasing sequentially in a direction away from the main junction includes:
performing ion implantation on a partial region of the first doped region to form a second doped region;
performing ion implantation on a partial region of the second doped region to form a third doped region;
wherein the ion type doped in the second doped region and the second doped region is the first conductive type; and the parts of the first doped region, the second doped region and the third doped region which are not subjected to ion implantation form the first gradient region.
In one embodiment, the forming a first doped region adjacent to the main junction in the silicon carbide substrate includes:
forming a first sacrificial layer on the silicon carbide substrate;
etching the first sacrificial layer to form a first junction terminal window;
and carrying out ion implantation through the first junction terminal window to form the first doped region.
In one embodiment, the ion implantation of the partial region of the first doped region to form a second doped region includes:
removing the first sacrificial layer;
forming a second sacrificial layer on the silicon carbide substrate;
etching the second sacrificial layer to form a second junction terminal window;
and carrying out ion implantation through the second junction terminal window to form the second doped region.
In one embodiment, the material of the first sacrificial layer and the second sacrificial layer is photoresist, and the etching the second sacrificial layer to form the second junction terminal window includes:
and photoetching the part of the second sacrificial layer corresponding to the second doping area to form the second junction terminal window.
In one embodiment, the ion implantation of a partial region of the second doped region to form a third doped region includes:
removing the second sacrificial layer;
forming a third sacrificial layer on the silicon carbide substrate;
etching the third sacrificial layer to form a third junction terminal window;
performing ion implantation through the third junction terminal to form the third doped region;
and the rest of the first doped region, the rest of the second doped region and the third doped region form the first gradient region.
In one embodiment, the third sacrificial layer is photoresist; the etching the third sacrificial layer to form a third junction termination window includes:
and photoetching the part of the third sacrificial layer corresponding to the third doped region to form the third junction terminal window.
In one embodiment, the performing, based on the same junction termination window, reverse type ion implantation on the first gradual change region at the same time to form a second gradual change region with sequentially decreasing ion concentration along a direction away from the main junction includes:
removing the third sacrificial layer;
forming a fourth sacrificial layer on the silicon carbide substrate;
etching the part of the fourth sacrificial layer corresponding to the first gradual change area to form a fourth junction terminal window exposing the upper surface of the first gradual change area;
and simultaneously performing ion implantation on the first gradient area through the fourth junction terminal window to form the second gradient area.
In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type.
In the manufacturing method of the terminal structure of the silicon carbide power device, the second gradual change region is formed without depending on direct etching of the silicon carbide substrate, so that the manufacturing process of the terminal structure of the silicon carbide power device is greatly simplified, and the process difficulty is correspondingly reduced. Meanwhile, the second gradient area is based on the first gradient area, and ion implantation is carried out through the same junction terminal window, so that in the ion implantation process, implanted second conductive type ions can be fully diffused in an area corresponding to the first gradient area, the change of ion concentration among all parts in the formed second gradient area tends to be moderate, and the possibility of electric field concentration can be greatly reduced.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating a method for fabricating a termination structure of a silicon carbide power device in one embodiment;
fig. 2 to 7 are schematic structural flow diagrams of a manufacturing method of a terminal structure of a silicon carbide power device in another embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a termination structure of a silicon carbide power device according to an embodiment, and as shown in fig. 1, the embodiment provides a method for manufacturing a termination structure of a silicon carbide power device, which may include the following steps:
step S10 provides a silicon carbide substrate prepared with the main junction.
Specifically, silicon carbide (SiC) is a third-generation wide bandgap semiconductor material having many excellent physicochemical characteristics, for example, silicon carbide has an electric field strength of about 10 times that of silicon, a thermal conductivity of 3 times that of silicon, a bandgap width of 3 times that of silicon, and a saturation drift velocity of one time higher. Moreover, the high-voltage high-power device made of silicon carbide also has the latent advantages that: the structure has the advantages of smaller volume, higher efficiency, low switching loss, low drain current, higher switching frequency than a standard semiconductor (a pure silicon semiconductor) and capability of working at a junction temperature of above 125 ℃, and can be used in high-voltage and high-heat nuclear reactors, space and other limited occasions.
However, when the silicon carbide power device bears a reverse high voltage, an electric field concentration phenomenon occurs at the corner of the chip, so that the voltage which needs to be borne by the main junction can be shared by arranging an ion concentration gradient region which is the same as the main junction conductivity type at the junction terminal of the silicon carbide power device.
To achieve the above object, a silicon carbide substrate prepared with a main junction, wherein the main junction may be doped with ions of the second conductivity type, may be provided.
In step S11, a first doped region is formed in the silicon carbide substrate adjacent to the main junction.
Specifically, a first doped region may be formed in a silicon carbide substrate by selecting a region near the main junction and implanting ions of the first conductivity type into the selected region by performing a process such as ion implantation.
In step S12, a first graded region is formed in the first doped region with ion concentration increasing in order in a direction away from the main junction.
Specifically, after the first doped region is formed at a position of the silicon carbide substrate close to the main junction, the ion implantation process may be continued for a plurality of times based on the first doped region to form a first graded region in which the concentration of the first conductivity type ions increases in sequence along the direction away from the main junction.
In step S13, based on the same junction terminal window, the reverse type ion implantation is simultaneously performed on the first graded region to form a second graded region in which the ion concentration decreases in the direction away from the main junction.
Specifically, on the basis of the first gradation region that has been formed in the above-described step, it is possible to continue to form a junction termination window on the first gradation region, and to simultaneously implant ions of the second conductivity type into respective portions of the first gradation region through the junction termination window.
Since the first-conductivity-type ions are sequentially decreased in concentration in the direction away from the main junction in the first graded region formed in step S12, and the reverse-type ions are simultaneously implanted into the first graded region in this step, the second-conductivity-type ions implanted in this step will neutralize the first-conductivity-type ions in the first graded region in step S12 and further only ions of the second conductivity type will be present in the first graded region; moreover, since the ion implantation is carried out through the same terminal window, the second conductive type ions implanted in the first gradual change region are uniformly distributed, so that a second gradual change region with the concentration of the second conductive type ions decreasing in sequence along the direction far away from the main junction can be formed after the ion neutralization process is finished.
In the embodiment, because the formation of the second gradient region does not rely on direct etching of the silicon carbide substrate, the manufacturing process of the terminal structure of the silicon carbide power device is greatly simplified, and the process difficulty is correspondingly reduced. Meanwhile, the second gradient area is based on the first gradient area, and ion implantation is carried out through the same junction terminal window, so that in the ion implantation process, implanted second conductive type ions can be fully diffused in an area corresponding to the first gradient area, the change of ion concentration among all parts in the formed second gradient area tends to be moderate, and the possibility of electric field concentration can be greatly reduced.
FIGS. 2-7 are schematic structural flow diagrams illustrating methods for fabricating termination structures of silicon carbide power devices in another embodiment. It should be noted that the first conductive type ions may be N-type ions, and the second conductive type ions are P-type ions; the first conductive type ions may also be P-type ions, and the second conductive type ions are N-type ions at this time. In some embodiments, the N-type ions may be 5-valent ions such as nitrogen, phosphorus, and arsenic, and the P-type ions may be trivalent ions such as boron and aluminum, which ions can be specifically applied can be determined according to actual process conditions and requirements, which is not limited in this embodiment. For convenience of description, the first conductive type ions in the present embodiment refer to N-type ions, and the second conductive type ions refer to P-type ions.
As shown in fig. 2 to 7, the present embodiment provides another method for manufacturing a termination structure of a silicon carbide power device, which may include the following steps:
a silicon carbide substrate prepared with a main junction is provided. Specifically, as shown in fig. 2, an initial silicon carbide substrate 21 may be provided, and the initial silicon carbide substrate 21 may be doped with ions of the first conductivity type. Further, an epitaxial layer 22 of the same material (i.e., silicon carbide) may be grown on the initial silicon carbide substrate 21, wherein the epitaxial layer 22 is doped with ions of the first conductivity type. Further, the main junction 23 may be formed on the epitaxial layer 22 by photolithography etching, ion implantation, or the like, and the main junction 23 is doped with the second conductive type ions. The initial silicon carbide substrate 21, epitaxial layer 22, and main junction 23 collectively comprise the silicon carbide substrate 20 for subsequent ion implantation operations.
A first doped region is formed in the silicon carbide substrate adjacent to the main junction. Specifically, as shown in fig. 3, a first sacrificial layer 30 may be deposited on the silicon carbide substrate 20 and the first sacrificial layer 30 may be etched, whereby a first junction termination window 31 may be formed adjacent to the main junction 23. Further, ions of the first conductivity type may be implanted into the epitaxial layer 22 through the first junction termination window 31. By means of an ion implantation process, the first conductivity type ions will be diffusively doped in the epitaxial layer 22 and form a first doped region 33 at a position corresponding to the first junction termination window 31. The process avoids direct etching of the epitaxial layer, and the doped region is formed by etching the sacrificial layer and injecting ions, so that the process difficulty is low, and the subsequent processes can be conveniently carried out.
And forming a first gradual change region in which the ion concentration is sequentially increased along the direction far away from the main junction in the first doping region. Specifically, referring to fig. 4, the first sacrificial layer 30 previously deposited may be removed and the second sacrificial layer 41 may be redeposited in the epitaxial layer 22. Further, the second sacrificial layer 41 corresponding to a partial region of the first doping region 33 may be etched, thereby forming a second junction terminal window 42. Further, first conductive type ions may be implanted into the epitaxial layer 22 through the second junction termination window 42 and form a second doped region 43. Wherein the portion of the first doped region 33 not covered by the second doped region 43 (i.e., the portion not ion implanted) forms, in conjunction with the second doped region 43, a region in the epitaxial layer 22 having a sequentially increasing concentration of ions of the first conductivity type in a direction away from the main junction 23.
Further, referring to fig. 5, the second sacrificial layer 41 may be removed, the third sacrificial layer 51 may be deposited again, and a third junction terminal window 52 may be etched at a position of the third sacrificial layer 51 corresponding to a portion of the second doped region 43. Similar to the above steps, the implantation of the first conductivity type ions may be continued into the epitaxial layer 22 through the third junction termination window 52 to form the third doped region 53. Up to this point, the regions of the first doped region 33, the second doped region 43 and the third doped region 53 that are not ion-implanted (i.e., the regions that are not covered by other doped regions) together constitute the first graded region 50, and the first conductivity type ion concentration sequentially increases in a direction away from the main junction 23.
And on the basis of the same junction terminal window, performing reverse type ion implantation on the first gradient area at the same time to form a second gradient area with the ion concentration decreasing in sequence along the direction away from the main junction. For proper operation of the silicon carbide power device, the conductivity type of the doped ions in the main junction 23 and the first graded region 50 should be consistent. Therefore, after the first graded region 50 is formed, the first graded region 50 is also subjected to the reverse type ion implantation. Specifically, as shown in fig. 6, the third sacrificial layer 51 formed in the above step may be removed, and the fourth sacrificial layer 61 may be re-deposited. The fourth sacrificial layer 61 may be etched and a fourth junction terminal window 62 may be formed at a position corresponding to the first graded region 50. Through the fourth junction termination window 62, the second conductive type ions can be simultaneously and uniformly implanted into the respective portions of the first graded region 50. With the continuous implantation of the second conductivity type ions, the first conductivity type ions originally existing in the first graded region 50 will be continuously neutralized. Finally, as shown in fig. 7, a second graded region 60 in which the concentration of the second conductivity type ions decreases in a direction away from the main junction 23 may be formed in the epitaxial layer 22.
The second gradual change region is formed by ion implantation through the same junction terminal window, so that in the ion implantation process, second conductive type ions can be more fully diffused in the epitaxial layer, the ion concentration change trend of the junction region where the ion concentrations change in the second gradual change region is more moderate, and electric field concentration is not easy to occur at the position.
It should be understood by those skilled in the art that the first and second graded regions may also be formed by two or more doped regions without ion implantation, and when there are more doped regions, the ion concentration variation in the formed first and second graded regions may be more gradual, according to the actual requirement.
In some embodiments, the sacrificial layer may be a photoresist, and the sacrificial layer may be etched using a photolithography process to form the junction termination window. However, in other embodiments, the sacrificial layer may be silicon dioxide, silicon carbide, or the like.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A method of fabricating a termination structure for a silicon carbide power device, the method comprising:
providing a silicon carbide substrate prepared with a main junction;
forming a first doped region in the silicon carbide substrate adjacent to the main junction;
forming a first gradually-changing region with sequentially increasing ion concentration along the direction far away from the main junction in the first doping region;
on the basis of the same junction terminal window, performing reverse type ion implantation on the first gradient area at the same time to form a second gradient area with sequentially decreasing ion concentration along the direction far away from the main junction;
the ion types doped in the silicon carbide substrate, the first doped region and the first gradient region are a first conductive type, and the ion types doped in the main junction and the second gradient region are a second conductive type;
wherein, the forming of the first gradual change region with the ion concentration increasing in sequence along the direction far away from the main junction in the first doping region comprises:
performing ion implantation on a partial region of the first doped region to form a second doped region;
performing ion implantation on a partial region of the second doped region to form a third doped region;
wherein the ion type doped in the second doped region and the second doped region is the first conductive type; the rest of the first doping region, the rest of the second doping region and the third doping region form the first gradual change region.
2. The method of claim 1, wherein the step of simultaneously implanting ions of opposite type into the first graded region based on the same junction termination window to form a second graded region having sequentially decreasing ion concentration in a direction away from the main junction comprises:
and forming a junction terminal window on the first gradual change region on the basis of the first gradual change region, and simultaneously injecting ions of a second conductivity type into each part of the first gradual change region through the junction terminal window.
3. The method of claim 1, wherein forming a first doped region in the silicon carbide substrate adjacent to the main junction comprises:
forming a first sacrificial layer on the silicon carbide substrate;
etching the first sacrificial layer to form a first junction terminal window;
and carrying out ion implantation through the first junction terminal window to form the first doped region.
4. The method of claim 3, wherein the ion implanting a partial region of the first doped region to form a second doped region comprises:
removing the first sacrificial layer;
forming a second sacrificial layer on the silicon carbide substrate;
etching the second sacrificial layer to form a second junction terminal window;
and carrying out ion implantation through the second junction terminal window to form the second doped region.
5. The method of claim 4, wherein the first sacrificial layer and the second sacrificial layer are made of photoresist, and the etching the second sacrificial layer to form a second junction termination window comprises:
and photoetching the part of the second sacrificial layer corresponding to the second doping area to form the second junction terminal window.
6. The method of claim 4, wherein the ion implanting a partial region of the second doped region to form a third doped region comprises:
removing the second sacrificial layer;
forming a third sacrificial layer on the silicon carbide substrate;
etching the third sacrificial layer to form a third junction terminal window;
performing ion implantation through the third junction terminal to form the third doped region;
and the rest of the first doped region, the rest of the second doped region and the third doped region form the first gradient region.
7. The method of claim 6, wherein the third sacrificial layer is a photoresist; the etching the third sacrificial layer to form a third junction termination window includes:
and photoetching the part of the third sacrificial layer corresponding to the third doped region to form the third junction terminal window.
8. The method according to claim 6, wherein the performing the reverse type ion implantation on the first graded region based on the same junction termination window simultaneously to form a second graded region with sequentially decreasing ion concentration in a direction away from the main junction comprises:
removing the third sacrificial layer;
forming a fourth sacrificial layer on the silicon carbide substrate;
etching the part of the fourth sacrificial layer corresponding to the first gradual change area to form a fourth junction terminal window exposing the upper surface of the first gradual change area;
and simultaneously performing ion implantation on the first gradient area through the fourth junction terminal window to form the second gradient area.
9. The method according to any one of claims 1 to 8, wherein the first conductivity type is P-type and the second conductivity type is N-type.
10. The method according to any one of claims 1 to 8, wherein the first conductivity type is N-type and the second conductivity type is P-type.
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