CN107342224B - Manufacturing method of VDMOS device - Google Patents
Manufacturing method of VDMOS device Download PDFInfo
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- CN107342224B CN107342224B CN201610287331.7A CN201610287331A CN107342224B CN 107342224 B CN107342224 B CN 107342224B CN 201610287331 A CN201610287331 A CN 201610287331A CN 107342224 B CN107342224 B CN 107342224B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 69
- 238000005530 etching Methods 0.000 claims abstract description 66
- 229920005591 polysilicon Polymers 0.000 claims abstract description 33
- 210000000746 body region Anatomy 0.000 claims abstract description 31
- 238000001259 photo etching Methods 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 23
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 229920006395 saturated elastomer Polymers 0.000 claims abstract description 11
- 239000012495 reaction gas Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 42
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ions Chemical class 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000000717 retained effect Effects 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention provides a manufacturing method of a VDMOS device, which comprises the following steps: growing a gate oxide layer on the N-type epitaxial layer and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer; photoetching and etching the intrinsic polycrystalline silicon layer and the gate oxide layer, and reserving the gate oxide layers and the intrinsic polycrystalline silicon layer in the left side region and the right side region; manufacturing a body region of the VDMOS device; carrying out intrinsic polysilicon doping by taking phosphorus oxychloride as a reaction gas to form a gate with a saturated N-type polysilicon layer and form a source region in a body region; forming a dielectric layer on the pattern after the source region is formed, wherein the dielectric layer is groove-shaped; photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and etching a source region below the bottom of the groove-type dielectric layer; and forming a metal layer on the pattern formed after etching the source region below the bottom of the groove-type dielectric layer, and manufacturing a metal lead, so that the high performance of the VDMOS device is ensured.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a VDMOS device.
Background
The single vertical double diffusion metal-oxide semiconductor transistor (VDMOS) has the advantages of both bipolar transistor and common MOS device. VDMOS is an ideal power device regardless of switching or linear applications. The VDMOS device is mainly used for motor speed regulation, inverters, uninterrupted power supplies, electronic switches, high-fidelity acoustics, automobile electric appliances, electronic ballasts and the like. The VDMOS device is classified into an enhancement type VDMOS device and a depletion type VDMOS device.
Fig. 11 is a schematic cross-sectional view of a prior art VDMOS device, and fig. 12 is a flowchart illustrating a method for fabricating the prior art VDMOS device, and as shown in fig. 11 and 12, the prior art VDMOS device fabrication method includes the following steps. Step 1201, forming a gate oxide layer 3 and an intrinsic polycrystalline silicon layer on the N-type epitaxial layer 2 in sequence; step 1202, in a furnace tube, taking phosphorus oxychloride as a reaction gas, carrying out N-type saturation doping on an intrinsic polycrystalline silicon layer, and doping the intrinsic polycrystalline silicon layer into a saturated N-type polycrystalline silicon layer; step 1203, carrying out photoetching and etching on the saturated N-type polycrystalline silicon layer to form a grid electrode 6 and carrying out injection and drive-in of the body region 5; step 1204, forming photoresist between the two gates 6 of the gate oxide layer 3, injecting the source region 7 with the photoresist as a barrier, removing the photoresist after injection, and driving the source region 7; and step 1205, depositing a dielectric layer 8, etching a contact hole, depositing a metal layer 9, and making a metal lead.
As can be seen from the manufacturing process of the VDMOS device in the prior art, when the doping of the polysilicon layer is performed in step 1202 and the implantation and driving of the source region are performed in step 1204, N-type ions are mixed, but a plurality of repeated manufacturing links are required, so that the manufacturing process is complicated, and the manufacturing cost of the VDMOS device is increased.
Disclosure of Invention
The embodiment of the invention provides a manufacturing method of a VDMOS device, and solves the problems that a plurality of repeated manufacturing links are needed when the VDMOS device is manufactured in the prior art, so that the manufacturing process is complex, and the manufacturing cost of the VDMOS device is increased.
The embodiment of the invention provides a manufacturing method of a VDMOS device, which comprises the following steps:
growing a gate oxide layer on the N-type epitaxial layer and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer;
photoetching and etching the intrinsic polycrystalline silicon layer and the gate oxide layer, and reserving the gate oxide layers and the intrinsic polycrystalline silicon layer in the left side region and the right side region;
manufacturing a body region of the VDMOS device;
carrying out intrinsic polysilicon doping by taking phosphorus oxychloride as a reaction gas to form a gate with a saturated N-type polysilicon layer and form a source region in a body region;
forming a dielectric layer on the pattern after the source region is formed, wherein the dielectric layer is groove-shaped;
photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and etching a source region below the bottom of the groove-type dielectric layer;
and forming a metal layer on the pattern formed after etching the source region below the bottom of the groove-type dielectric layer, and manufacturing a metal lead.
Further, in the above method, the performing photolithography and etching on the recessed dielectric layer to etch away the bottom of the recessed dielectric layer and etch away the source region below the bottom of the recessed dielectric layer specifically includes:
photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and reserving photoresist above the photoetching and etched dielectric layer;
and under the blocking of the photoresist, continuously etching the source region, and etching the source region below the bottom of the groove-type dielectric layer.
Further, the method as described above, growing a gate oxide layer on the N-type epitaxial layer and depositing an intrinsic polysilicon layer on the gate oxide layer specifically includes:
growing a gate oxide layer on the N-type epitaxial layer by adopting a dry thermal oxidation growth process;
and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer by adopting a chemical vapor deposition process.
Further, according to the method, the manufacturing of the body region of the VDMOS device specifically includes:
and carrying out P-type ion implantation and high-temperature drive-in on the VDMOS device, and forming a body region in the N-type epitaxial layer.
Further, in the above method, the P-type ion implantation ions are boron ions, the dose is 1.0E13-1.0E15 ions/cm, and the energy may be 60-120 KEV.
Further, in the method, the temperature of the high-temperature drive-in is 900-1150 ℃, and the time of the high-temperature drive-in is 50-300 minutes.
Further, in the method, the thickness of the gate oxide layer is 500-1500 angstroms, and the thickness of the intrinsic polysilicon layer is 4000-8000 angstroms.
Further, as in the method described above, the intrinsic polysilicon layer has a thickness of 6000 angstroms.
The embodiment of the invention provides a manufacturing method of a VDMOS device, which comprises the steps of growing a gate oxide layer on an N-type epitaxial layer and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer; photoetching and etching the intrinsic polycrystalline silicon layer and the gate oxide layer, and reserving the gate oxide layers and the intrinsic polycrystalline silicon layer in the left side region and the right side region; manufacturing a body region of the VDMOS device; carrying out intrinsic polysilicon doping by taking phosphorus oxychloride as a reaction gas to form a gate with a saturated N-type polysilicon layer and form a source region in a body region; forming a dielectric layer on the pattern after the source region is formed, wherein the dielectric layer is groove-shaped; photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and etching a source region below the bottom of the groove-type dielectric layer; and forming a metal layer on the pattern formed after etching the source region below the bottom of the groove-type dielectric layer, and manufacturing a metal lead. When the grid electrode is manufactured by doping the intrinsic polycrystalline silicon layer, the source region is injected, so that the photoetching and injection processes of the source region are avoided, repeated manufacturing links of the VDMOS device are reduced, the manufacturing cost of the VDMOS device is reduced, and the high performance of the VDMOS device is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a flow chart of a first embodiment of a method for fabricating a VDMOS device according to the present invention;
FIG. 2 is a schematic cross-sectional view of a device after step 101 according to the first embodiment of the present invention;
FIG. 3 is a cross-sectional view of the device after step 102 according to the first embodiment of the present invention;
FIG. 4 is a cross-sectional view of the device after step 103 according to the first embodiment of the present invention;
FIG. 5 is a cross-sectional view of the device after step 104 according to the first embodiment of the present invention;
FIG. 6 is a cross-sectional view of the device after step 105 according to the first embodiment of the present invention;
FIG. 7 is a cross-sectional view of the device after step 106 according to the first embodiment of the present invention;
FIG. 8 is a cross-sectional view of the device after step 107 according to the first embodiment of the present invention;
FIG. 9 is a flow chart of a second embodiment of a method for fabricating a VDMOS device according to the present invention;
FIG. 10 is a cross-sectional view of the device after step 207 of example two is performed in accordance with the present invention;
FIG. 11 is a schematic cross-sectional view of a prior art VDMOS device;
fig. 12 is a flow chart of a prior art VDMOS device fabrication process.
Reference numerals:
1-N type substrate 2-N type epitaxial layer 3-gate oxide
4-intrinsic poly 5-body 6-gate
7-source region 8-dielectric layer 9-metal layer
10-Photoresist
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a first method for manufacturing a VDMOS device according to an embodiment of the present invention, and as shown in fig. 1, the method for manufacturing a VDMOS device according to the present embodiment includes the following steps.
Specifically, in this embodiment, fig. 2 is a schematic cross-sectional structure diagram of the device after step 101 of the first embodiment of the present invention is executed, and as shown in fig. 2, before a gate oxide layer 3 is grown on an N-type epitaxial layer 2 and an intrinsic polysilicon layer 4 is deposited on the gate oxide layer 3, the N-type epitaxial layer 2 is epitaxially grown on an N-type substrate 1. The N-type substrate 1 is a heavily doped N-type substrate 1, and the N-type epitaxial layer 2 is a lightly doped N-type epitaxial layer 2. The doping concentration of the N-type substrate 1 and the doping concentration of the N-type epitaxial layer 22 are the same as those in the prior art, and are not described in detail herein.
In this embodiment, the gate oxide layer 3 may be grown on the N-type epitaxial layer 2 by a dry thermal oxidation growth process, or the gate oxide layer 3 may be grown by other processes, which is not limited in this embodiment. When the intrinsic polysilicon layer 4 is deposited on the gate oxide layer 3, a chemical vapor deposition process may be adopted, or other processes may also be adopted, which is not limited in this embodiment.
And 102, photoetching and etching the intrinsic polycrystalline silicon layer 4 and the gate oxide layer 3, and reserving the gate oxide layer 3 and the intrinsic polycrystalline silicon layer 4 in the left and right side areas.
Specifically, in this embodiment, fig. 3 is a schematic cross-sectional structure diagram of the device after step 102 of the first embodiment of the present invention is executed, as shown in fig. 3, in this embodiment, the intrinsic polysilicon layer 4 and the gate oxide layer 3 are etched and etched together until the upper surface of the N-type epitaxial layer 2, the intrinsic polysilicon layer 4 and the gate oxide layer 3 in the middle region are etched away, and the gate oxide layer 3 and the intrinsic polysilicon layer 4 in the left and right side regions are retained. Wherein, after the gate oxide layer 3 and the intrinsic polycrystalline silicon layer 4 are etched, the etched window formed by the section is rectangular.
And 103, manufacturing a body region 5 of the VDMOS device.
Specifically, fig. 4 is a schematic cross-sectional structure diagram of the device after step 103 of the first embodiment of the present invention is executed, as shown in fig. 4, in this embodiment, a P-type ion implantation and a high-temperature drive-in process may be performed on the VDMOS device, a body region 5 is formed in the N-type epitaxial layer 2, the thickness of the body region 5 is smaller than that of the N-type epitaxial layer 2, and the body region is formed below a window after the gate oxide layer 3 and the intrinsic polysilicon layer 4 are subjected to photolithography etching in step 102, where the width of the body region 5 is greater than the width of the window after the gate oxide layer 3 and the intrinsic polysilicon layer 4 are subjected to photolithography etching.
And step 104, doping the intrinsic polycrystalline silicon by taking phosphorus oxychloride as reaction gas to form a gate 6 with a saturated N-type polycrystalline silicon layer, and forming a source region 7 in the body region 5.
Specifically, fig. 5 is a schematic cross-sectional structure diagram of the device after step 104 of the first embodiment of the present invention, as shown in fig. 5, in this embodiment, a VDMOS device is placed in a furnace tube, phosphorus oxychloride is used as a reaction gas to perform intrinsic polysilicon doping, N-type ions enter the intrinsic polysilicon layer 4 and are injected into the body region 5 from an etched window, so that not only the gate 6 having a saturated N-type polysilicon layer is formed, but also the source region 7 is formed in the body region 5.
In this embodiment, the thickness of the source region 7 is smaller than the thickness of the body region 5, and the width of the source region 7 is smaller than the width of the body region 5.
Specifically, fig. 6 is a schematic cross-sectional structure diagram of the device after step 105 of the first embodiment of the present invention, as shown in fig. 6, in this embodiment, a dielectric layer 8 is formed on the pattern after forming the source region 7, that is, the dielectric layer 8 is formed on the gate 6, and on the top and side of the window formed after performing the photolithography etching on the gate oxide layer 3 and the intrinsic polysilicon layer 4, and the cross-sectional shape of the dielectric layer 8 is a groove shape.
And 106, photoetching and etching the groove-shaped dielectric layer 8, etching the bottom of the groove-shaped dielectric layer 8, and etching the source region 7 below the bottom of the groove-shaped dielectric layer 8.
Specifically, fig. 7 is a schematic cross-sectional structure diagram of the device after step 106 of the first embodiment of the present invention is executed, as shown in fig. 7, in this embodiment, the trench-type dielectric layer 8 is subjected to photolithography and etching, the dielectric layer 8 above the gate 6, on the side of the gate 6 and the gate oxide layer 3 is retained, the bottom of the trench-type dielectric layer 8 is etched away, the source region 7 below the bottom of the trench-type dielectric layer 8 is etched away, and the source region 7 below the gate oxide layer 3 and below the dielectric layer 8 on the side of the gate oxide layer 3 is retained, that is, the original left and right regions of the source region 7.
And step 107, forming a metal layer 9 on the pattern formed after etching the source region 7 below the bottom of the groove-type dielectric layer 8, and manufacturing a metal lead.
Specifically, fig. 8 is a schematic cross-sectional structure diagram of the device after step 107 according to the first embodiment of the present invention, as shown in fig. 8, in this embodiment, a metal layer 9 is formed on a pattern formed after etching away the source region 7 below the bottom of the recessed dielectric layer 8, that is, the metal layer 9 is formed above the dielectric layer 8, on the side surface of the source region 7, and on the upper surface of the body region 5, and a metal lead is fabricated.
In this embodiment, the operation of fabricating the metal leads is the same as that in the prior art, and is not described in detail herein.
In the method for manufacturing the VDMOS device provided in this embodiment, a gate oxide layer 3 is grown on an N-type epitaxial layer 2, and an intrinsic polysilicon layer 4 is deposited on the gate oxide layer 3; photoetching and etching the intrinsic polycrystalline silicon layer 4 and the gate oxide layer 3, and reserving the gate oxide layer 3 and the intrinsic polycrystalline silicon layer 4 in the left and right side areas; manufacturing a body region 5 of the VDMOS device; carrying out intrinsic polysilicon doping by taking phosphorus oxychloride as a reaction gas to form a gate 6 with a saturated N-type polysilicon layer and form a source region 7 in the body region 5; forming a dielectric layer 8 on the pattern after the source region 7 is formed, wherein the dielectric layer 8 is groove-shaped; photoetching and etching the groove-shaped dielectric layer 8, etching the bottom of the groove-shaped dielectric layer, and etching the source region 7 below the bottom of the groove-shaped dielectric layer 8; and forming a metal layer 9 on the pattern formed after etching the source region 7 below the bottom of the groove-type dielectric layer 8, and manufacturing a metal lead. When the grid electrode 6 is manufactured by doping the intrinsic polycrystalline silicon layer 4, the source region 7 is injected, so that the photoetching and injection processes of the source region 7 are avoided, repeated manufacturing links of the VDMOS device are reduced, and the manufacturing cost of the VDMOS device is reduced. And ensures the high performance of the VDMOS device.
Fig. 2 is a flowchart of a second embodiment of a method for manufacturing a VDMOS device according to the present invention, and as shown in fig. 2, the method for manufacturing a VDMOS device provided in this embodiment is a more preferred embodiment than the first embodiment, and the method for manufacturing a VDMOS device provided in this embodiment includes the following steps.
Step 201, growing a gate oxide layer 3 on the N-type epitaxial layer 2 by using a dry thermal oxidation growth process.
Further, the thickness of the gate oxide layer 3 is 500-1500 angstroms.
Further, the thickness of the intrinsic polycrystalline silicon layer 4 is 4000-.
In this embodiment, the implementation manner of step 203 is the same as that of step 102 in the first embodiment of the present invention, and is not described in detail here.
And step 204, performing P-type ion implantation and high-temperature drive-in on the VDMOS device to form a body region 5 in the N-type epitaxial layer 2.
Further, in the present embodiment, the ions implanted by the P-type ions are boron ions, the dose is 1.0E13-1.0E15 ions/cm, and the energy can be 60-120 KEV.
Further, the temperature of the high-temperature drive-in is 900-1150 ℃, and the time of the high-temperature drive-in is 50-300 minutes.
In this embodiment, P-type ion implantation and high-temperature drive-in are performed on the VDMOS device, the thickness of the body region 5 formed in the N-type epitaxial layer 2 is smaller than the thickness of the N-type epitaxial layer 2, and the width of the body region 5 in the device cross section is smaller than the width of the N-type epitaxial layer 2.
In this embodiment, the implementation manners of steps 205 to 206 are the same as the implementation manners of steps 104 to 105 in the first embodiment of the present invention, and are not described in detail herein.
Further, fig. 10 is a schematic cross-sectional structure diagram of the device after step 207 of the second embodiment of the present invention is executed, as shown in fig. 10, in this embodiment, after the trench-type dielectric layer 8 is subjected to photolithography and etching, the dielectric layer 8 at the bottom of the trench-type dielectric layer 8 is etched away, the dielectric layers 8 above the gate 6, on the gate 6 and on the side surface of the gate oxide layer 3 are retained, and the photoresist 10 above the dielectric layer 8 after the photolithography and etching is retained, so as to subsequently etch the source region 7.
And step 208, continuing to etch the source region 7 under the barrier of the photoresist 10, and etching the source region 7 below the bottom of the groove-type dielectric layer 8.
Further, in this embodiment, the photoresist 10 used for performing the photolithography of the dielectric layer 8 is used, and the source region 7 is continuously etched under the blocking of the photoresist 10, so as to etch away the source region 7 below the bottom of the groove-type dielectric layer 8 until the upper surface of the body region 5, and the source region 7 below the gate oxide layer 3 and below the dielectric layer 8 on the side of the gate oxide layer 3 are retained, that is, the left and right regions of the original source region 7 are retained.
In this embodiment, after the source region 7 below the bottom of the trench-type dielectric layer 8 is etched away, the photoresist 10 above the dielectric layer 8 after the photolithography and etching is removed, and the specific removal process is not limited in this embodiment.
In this embodiment, the implementation manner of step 209 is the same as the implementation manner of step 107 in the first embodiment of the present invention, and is not described again here.
The method for manufacturing the VDMOS device provided by the embodiment comprises the steps of growing a gate oxide layer 3 on an N-type epitaxial layer 2 by adopting a dry thermal oxidation growth process, depositing an intrinsic polycrystalline silicon layer 4 on the gate oxide layer 3 by adopting a chemical vapor deposition process, photoetching and etching the intrinsic polycrystalline silicon layer 4 and the gate oxide layer 3, reserving the gate oxide layer 3 and the intrinsic polycrystalline silicon layer 4 in the left side and the right side areas, carrying out P-type ion injection and high-temperature drive-in on the VDMOS device, forming a body area 5 in the N-type epitaxial layer 2, carrying out intrinsic polycrystalline silicon doping by taking phosphorus oxychloride as a reaction gas to form a gate 6 with a saturated N-type polycrystalline silicon layer, forming a source area 7 in the body area 5, forming a dielectric layer 8 on a pattern after the source area 7 is formed, carrying out photoetching and etching on a groove-type dielectric layer 8 to etch the bottom of the groove-type dielectric layer 8, and reserving the photoresist 10 above the dielectric layer 8 after photoetching and etching, continuously etching the source region 7 under the blocking of the photoresist 10, etching the source region 7 below the bottom of the groove-shaped dielectric layer 8, removing the photoresist 10 above the dielectric layer 8 after photoetching and etching, forming a metal layer 9 on a pattern formed after etching the source region 7 below the bottom of the groove-shaped dielectric layer 8, manufacturing a metal lead, and repeatedly using the photoresist 10 when etching the dielectric layer 8 and the source region 7, thereby further reducing the repeated manufacturing links of the VDMOS device and reducing the manufacturing cost of the VDMOS device. And ensures the high performance of the VDMOS device.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (7)
1. A method for manufacturing a VDMOS device is characterized by comprising the following steps:
growing a gate oxide layer on the N-type epitaxial layer and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer;
photoetching and etching the intrinsic polycrystalline silicon layer and the gate oxide layer, and reserving the gate oxide layers and the intrinsic polycrystalline silicon layer in the left side region and the right side region;
manufacturing a body region of the VDMOS device;
carrying out intrinsic polysilicon doping by taking phosphorus oxychloride as a reaction gas to form a gate with a saturated N-type polysilicon layer and forming a source region in the body region;
forming a dielectric layer on the pattern after the source region is formed, wherein the dielectric layer is groove-shaped;
photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and etching a source region below the bottom of the groove-type dielectric layer;
forming a metal layer on a pattern formed after etching a source region below the bottom of the groove-type dielectric layer, and manufacturing a metal lead;
the photoetching and etching of the groove-shaped dielectric layer are carried out, the bottom of the groove-shaped dielectric layer is etched, and the etching of the source region below the bottom of the groove-shaped dielectric layer specifically comprises the following steps:
photoetching and etching the groove-type dielectric layer, etching the bottom of the groove-type dielectric layer, and reserving photoresist above the photoetching and etched dielectric layer;
and under the blocking of the photoresist, continuously etching the source region, and etching the source region below the bottom of the groove-type dielectric layer.
2. The method of claim 1, wherein growing a gate oxide layer on an N-type epitaxial layer and depositing an intrinsic polysilicon layer on the gate oxide layer, specifically comprises:
growing a gate oxide layer on the N-type epitaxial layer by adopting a dry thermal oxidation growth process;
and depositing an intrinsic polycrystalline silicon layer on the gate oxide layer by adopting a chemical vapor deposition process.
3. The method according to claim 2, wherein the fabricating the body region of the VDMOS device is specifically:
and carrying out P-type ion implantation and high-temperature drive-in on the VDMOS device, and forming a body region in the N-type epitaxial layer.
4. The method of claim 3, wherein the P-type ions are boron ions at a dose of 1.0E13-1.0E15 ions per square centimeter and at an energy of 60-120 KEV.
5. The method as claimed in claim 3 or 4, wherein the temperature of the high temperature drive-in is 900-1150 ℃ and the time of the high temperature drive-in is 50-300 minutes.
6. The method as claimed in claim 2, wherein the gate oxide layer has a thickness of 500-1500 angstroms, and the intrinsic polysilicon layer has a thickness of 4000-8000 angstroms.
7. The method of claim 6, wherein the intrinsic polysilicon layer has a thickness of 6000 angstroms.
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| KR100532082B1 (en) * | 2001-12-28 | 2005-11-30 | 엘지.필립스 엘시디 주식회사 | An poly-crystalline thin film transistor and a method of fabricating thereof |
| JP2008130983A (en) * | 2006-11-24 | 2008-06-05 | Nec Electronics Corp | Semiconductor device and its manufacturing method |
| CN104900526B (en) * | 2014-03-07 | 2018-07-24 | 北大方正集团有限公司 | The manufacturing method and VDMOS of VDMOS |
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| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
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