CN107342224A - The preparation method of VDMOS device - Google Patents
The preparation method of VDMOS device Download PDFInfo
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- CN107342224A CN107342224A CN201610287331.7A CN201610287331A CN107342224A CN 107342224 A CN107342224 A CN 107342224A CN 201610287331 A CN201610287331 A CN 201610287331A CN 107342224 A CN107342224 A CN 107342224A
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- gate oxide
- source region
- fluted body
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 67
- 229920005591 polysilicon Polymers 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000001259 photo etching Methods 0.000 claims abstract description 35
- 238000000407 epitaxy Methods 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 23
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 230000008021 deposition Effects 0.000 claims abstract description 14
- 229910019213 POCl3 Inorganic materials 0.000 claims abstract description 10
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- 230000015572 biosynthetic process Effects 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000002347 injection Methods 0.000 description 9
- 239000007924 injection Substances 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention provides a kind of preparation method of VDMOS device, this method includes：Gate oxide and the deposition of intrinsic polysilicon layer on gate oxide are grown in N-type epitaxy layer；Photoetching, etching are carried out to intrinsically polysilicon layer and gate oxide, retain the gate oxide and intrinsically polysilicon layer in left and right sides region；Make the body area of VDMOS device；Using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, forms the grid with saturation N-type polycrystalline silicon layer, Bing Ti forms source region in area；Dielectric layer is formed on the pattern after forming source region, dielectric layer is fluted body；Photoetching, etching are carried out to fluted body dielectric layer, etches away the bottom of fluted body dielectric layer, and etch away the source region of the bottom part down of fluted body dielectric layer；Metal level is formed on the pattern formed after the source region of the bottom part down of fluted body dielectric layer is etched away, and makes metal lead wire, ensure that the high-performance of VDMOS device.
Description
Technical field
The present embodiments relate to semiconductor fabrication techniques field, more particularly to a kind of VDMOS device
Preparation method.
Background technology
Single vertical double diffused metal-oxide semi conductor transistor is (referred to as：VDMOS bipolar transistor) is had concurrently
The advantages of with common MOS device.No matter switch application or linear applications, VDMOS is preferable
Power device.VDMOS device be mainly used in electric machine speed regulation, inverter, uninterrupted power source, electronic switch,
High-fidelity music center, car electrics and electric ballast etc..VDMOS device is divided into enhanced VDMOS devices
Part and depletion type VDMOS device.
Figure 11 is the cross-sectional view of VDMOS device in the prior art, and Figure 12 is prior art
The Making programme figure of middle VDMOS device, as is illustrated by figs. 11 and 12, existing VDMOS device
Preparation method include following steps.Step 1201, grid oxygen is sequentially formed in N-type epitaxy layer 2
Change layer 3 and intrinsically polysilicon layer；Step 1202, it is right using POCl3 as reacting gas in boiler tube
Intrinsically polysilicon layer carries out N-type saturation doping, and intrinsically polysilicon layer is doping into saturation N-type polycrystalline silicon layer；
Step 1203, photoetching, etching are carried out to saturation N-type polycrystalline silicon layer, grid 6 is formed and carries out body area 5
Injection and drive in；Step 1204, photoresist is formed between two grids 6 of gate oxide 3, with light
Photoresist does the injection of source region 7 to stop, photoresist is removed after injection, and carry out driving in for source region 7；Step
Rapid 1205, metallization medium layer 8, contact hole etching, deposited metal layer 9 are carried out, and make metal lead wire.
The Making programme of VDMOS device be can be seen that from the prior art, and polycrystalline is carried out in step 1202
The doping of silicon layer, and carry out the injection of source region in step 1204 and when driving in, be mixed with N-type from
Son, but the making link of multiple repetitions is needed, make complex manufacturing technology, and add VDMOS device
Cost of manufacture.
The content of the invention
The embodiment of the present invention provides a kind of preparation method of VDMOS device, solves and makes in the prior art
Make to need the making link of multiple repetitions during VDMOS device, make complex manufacturing technology, and add
The problem of cost of manufacture of VDMOS device.
The embodiment of the present invention provides a kind of preparation method of VDMOS device, including：
Gate oxide and the deposition of intrinsic polysilicon layer on the gate oxide are grown in N-type epitaxy layer；
Photoetching, etching are carried out to the intrinsically polysilicon layer and the gate oxide, retain left and right sides area
The gate oxide and intrinsically polysilicon layer in domain；
Make the body area of the VDMOS device；
Using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, formation has saturation N-type polycrystalline
The grid of silicon layer, Bing Ti form source region in area；
Dielectric layer is formed on the pattern after forming source region, the dielectric layer is fluted body；
Photoetching, etching are carried out to fluted body dielectric layer, etches away the bottom of fluted body dielectric layer, and etch
Fall the source region of the bottom part down of fluted body dielectric layer；
Metal level is formed on the pattern formed after the source region of the bottom part down of fluted body dielectric layer is etched away,
And make metal lead wire.
Further, method as described above, it is described that photoetching, etching are carried out to fluted body dielectric layer, carve
The bottom of eating away groove dielectric layer, and the source region for etching away the bottom part down of fluted body dielectric layer is specifically wrapped
Include：
Photoetching, etching are carried out to fluted body dielectric layer, etches away the bottom of fluted body dielectric layer, and retain
Carry out the photoresist above the dielectric layer after photoetching, etching；
Under the stop of the photoresist, source region is continued to etch, etches away fluted body dielectric layer
The source region of bottom part down.
Further, method as described above, it is described gate oxide to be grown in N-type epitaxy layer and in institute
Deposition of intrinsic polysilicon layer on gate oxide is stated, is specifically included：
Using dry method thermal oxide growth technique, gate oxide is grown in the N-type epitaxy layer；
Using chemical vapor deposition method, the deposition of intrinsic polysilicon layer on the gate oxide.
Further, method as described above, the body area of the making VDMOS device are specially：
P-type ion implanting is carried out to the VDMOS device and high temperature drives in, in the N-type epitaxy layer
Interior formation body area.
Further, method as described above, the ion of the p-type ion implanting are boron ion, dosage
For 1.0E13-1.0E15/square centimeter, energy can be 60-120KEV.
Further, method as described above, the temperature that the high temperature drives in are 900-1150 degrees Celsius,
The time that the high temperature drives in is 50-300 minutes.
Further, method as described above, the thickness of the gate oxide is 500-1500 angstroms, described
The thickness of intrinsically polysilicon layer is 4000-8000 angstroms.
Further, method as described above, the thickness of the intrinsically polysilicon layer is 6000 angstroms.
The embodiment of the present invention provides a kind of preparation method of VDMOS device, by N-type epitaxy layer
Grow gate oxide and the deposition of intrinsic polysilicon layer on gate oxide；To intrinsically polysilicon layer and gate oxidation
Layer carries out photoetching, etching, retains the gate oxide and intrinsically polysilicon layer in left and right sides region；Make
The body area of VDMOS device；Using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, is formed
Grid with saturation N-type polycrystalline silicon layer, Bing Ti form source region in area；Pattern after source region is formed
Upper formation dielectric layer, dielectric layer are fluted body；Photoetching, etching are carried out to fluted body dielectric layer, is etched away
The bottom of fluted body dielectric layer, and etch away the source region of the bottom part down of fluted body dielectric layer；Etching away
Metal level is formed on the pattern formed after the source region of the bottom part down of fluted body dielectric layer, and makes metal and draws
Line.When doping due to carrying out intrinsically polysilicon layer makes grid, together with the injection for carrying out source region, keep away
Exempt from the photoetching of progress source region and injection process again, reduce the making of the repetition of VDMOS device
Link, reduces the cost of manufacture of VDMOS device, and ensure that the high-performance of VDMOS device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to reality
The required accompanying drawing used in example or description of the prior art is applied to be briefly described, it should be apparent that, under
Accompanying drawing in the description of face is some embodiments of the present invention, for those of ordinary skill in the art,
On the premise of not paying creative labor, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart of the preparation method embodiment one of VDMOS device of the present invention；
Fig. 2 is that the present invention performs the device profile structural representation after the step 101 of embodiment one；
Fig. 3 is that the present invention performs the device profile structural representation after the step 102 of embodiment one；
Fig. 4 is that the present invention performs the device profile structural representation after the step 103 of embodiment one；
Fig. 5 is that the present invention performs the device profile structural representation after the step 104 of embodiment one；
Fig. 6 is that the present invention performs the device profile structural representation after the step 105 of embodiment one；
Fig. 7 is that the present invention performs the device profile structural representation after the step 106 of embodiment one；
Fig. 8 is that the present invention performs the device profile structural representation after the step 107 of embodiment one；
Fig. 9 is the flow chart of the preparation method embodiment two of VDMOS device of the present invention；
Figure 10 is that the present invention performs the device profile structural representation after the step 207 of embodiment two；
Figure 11 is the cross-sectional view of VDMOS device in the prior art；
Figure 12 is the Making programme figure of VDMOS device in the prior art.
Reference：
1-N type substrate 2-N type epitaxial layer 3- gate oxides
4- intrinsically polysilicon layer 5- bodies area 6- grids
7- source region 8- dielectric layer 9- metal levels
10- photoresists
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with this hair
Accompanying drawing in bright embodiment, the technical scheme in the embodiment of the present invention is clearly and completely described,
Obviously, described embodiment is part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained under the premise of creative work is not made
The every other embodiment obtained, belongs to the scope of protection of the invention.
Fig. 1 is the flow chart of the preparation method embodiment one of VDMOS device of the present invention, as shown in figure 1,
The preparation method for the VDMOS device that the present embodiment provides includes following steps.
Step 101, gate oxide 3 and the deposition of intrinsic on gate oxide 3 are grown in N-type epitaxy layer 2
Polysilicon layer 4.
Specifically, in the present embodiment, Fig. 2 is that the present invention performs the device after the step 101 of embodiment one
Cross-sectional view, as shown in Fig. 2 growing gate oxide 3 in N-type epitaxy layer 2 and in gate oxidation
On layer 3 before deposition of intrinsic polysilicon layer 4, in the Epitaxial growth N-type epitaxy layer 2 of N-type substrate 1.Its
In, N-type substrate 1 is heavily doped N-type substrate 1, and N-type epitaxy layer 2 is lightly doped n type epitaxial layer 2.Tool
The doping concentration of the N-type substrate 1 of body and the doping concentration of N-type epitaxy layer 22 with it is of the prior art
Doping concentration is identical, and this is no longer going to repeat them.
In the present embodiment, dry method thermal oxide growth technique growth gate oxidation can be used in N-type epitaxy layer 2
Layer 3, other techniques growth gate oxide 3 can be also used, is not limited in this implementation.In gate oxide 3
During upper deposition of intrinsic polysilicon layer 4, other techniques can also be used using the technique of chemical vapor deposition,
Do not limited in the present embodiment.
Step 102, photoetching, etching are carried out to intrinsically polysilicon layer 4 and gate oxide 3, retains left and right
The gate oxide 3 and intrinsically polysilicon layer 4 of two side areas.
Specifically, in the present embodiment, Fig. 3 is that the present invention performs the device after the step 102 of embodiment one
Cross-sectional view, as shown in figure 3, in the present embodiment, by intrinsically polysilicon layer 4 and gate oxide
3 carry out photoetching, etching in the lump, until the upper surface of N-type epitaxy layer 2, etch away the sheet of intermediate region
Polysilicon layer 4 and gate oxide 3 are levied, retains the gate oxide 3 and intrinsic polysilicon in left and right sides region
Layer 4.Wherein, after the gate oxide 3 and intrinsically polysilicon layer 4 that etch away, after the etching that section is formed
Window it is rectangular.
Step 103, the body area 5 of VDMOS device is made.
Specifically, Fig. 4 is that the present invention performs the device profile structural representation after the step 103 of embodiment one
Figure, as shown in figure 4, in the present embodiment, p-type ion implanting and high temperature can be carried out to VDMOS device
Injection process, body area 5 is formed in N-type epitaxy layer 2, the thickness in the body area 5 is less than N-type epitaxy layer
2 thickness, formed after step 102 carries out chemical wet etching to gate oxide 3 and intrinsically polysilicon layer 4
Window lower section, wherein the width in body area 5 be more than gate oxide 3 and intrinsically polysilicon layer 4 are carried out
The width of window after chemical wet etching.
Step 104, using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, is formed to have and satisfied
With the grid 6 of N-type polycrystalline silicon layer, source region 7 is formed in Bing Ti areas 5.
Specifically, Fig. 5 is that the present invention performs the device profile structural representation after the step 104 of embodiment one
Figure, as shown in figure 5, in the present embodiment, VDMOS device is put into boiler tube, using POCl3 as
Reacting gas, intrinsic polysilicon doping being carried out, N-type ion is entered in intrinsically polysilicon layer 4, and from
Window after etching is injected into body area 5, not only forms the grid 6 with saturation N-type polycrystalline silicon layer,
And source region 7 is formd in body area 5.
In the present embodiment, the thickness of source region 7 is less than the thickness in body area 5, and the width of source region 7 is less than body area
5 width.
Step 105, dielectric layer 8 is formed on the pattern after forming source region 7, dielectric layer 8 is fluted body.
Specifically, Fig. 6 is that the present invention performs the device profile structural representation after the step 105 of embodiment one
Figure, as shown in fig. 6, in the present embodiment, dielectric layer 8 is formed on the pattern after forming source region 7, i.e.,
Above grid 6, to the window formed after gate oxide 3 and the progress chemical wet etching of intrinsically polysilicon layer 4
Top and side are respectively formed dielectric layer 8, and the section shape of dielectric layer 8 is fluted body.
Step 106, photoetching, etching are carried out to fluted body dielectric layer 8, etches away fluted body dielectric layer 8
Bottom, and etch away the source region 7 of the bottom part down of fluted body dielectric layer 8.
Specifically, Fig. 7 is that the present invention performs the device profile structural representation after the step 106 of embodiment one
Figure, as shown in fig. 7, in the present embodiment, photoetching, etching are carried out to groove dielectric layer 8, retains grid
The dielectric layer 8 of the top of pole 6, grid 6 and the side of gate oxide 3, etches away fluted body dielectric layer 8
Bottom, and the source region 7 of the bottom part down of fluted body dielectric layer 8 is etched away, retain the lower section of gate oxide 3
And the source region 7 of the lower section of 3 side dielectric layer of gate oxide 8, that is, retain original region of source region 7 or so.
Step 107, the pattern formed after the source region 7 of the bottom part down of fluted body dielectric layer 8 is etched away
Upper formation metal level 9, and make metal lead wire.
Specifically, Fig. 8 is that the present invention performs the device profile structural representation after the step 107 of embodiment one
Figure, as shown in figure 8, in the present embodiment, in the source for the bottom part down for etching away fluted body dielectric layer 8
Formation metal level 9, the i.e. top in dielectric layer 8 on the pattern formed behind area 7, the side of dielectric layer 8,
The side of source region 7 and the upper surface in body area 5 are respectively formed metal level 9, and make metal lead wire.
In the present embodiment, the operation of metal lead wire is made with of the prior art identical, herein no longer one by one
Repeat.
The preparation method for the VDMOS device that the present embodiment provides, by being grown in N-type epitaxy layer 2
Gate oxide 3 and the deposition of intrinsic polysilicon layer 4 on gate oxide 3；To intrinsically polysilicon layer 4 and grid
Oxide layer 3 carries out photoetching, etching, retains the gate oxide 3 and intrinsically polysilicon layer in left and right sides region
4；Make the body area 5 of VDMOS device；Using POCl3 as reacting gas, carry out intrinsic polysilicon and mix
It is miscellaneous, the grid 6 with saturation N-type polycrystalline silicon layer is formed, source region 7 is formed in Bing Ti areas 5；In shape
Dielectric layer 8 is formed on into the pattern after source region 7, dielectric layer 8 is fluted body；To fluted body dielectric layer 8
Carry out photoetching, etching, etch away the bottom of fluted body dielectric layer, and etch away fluted body dielectric layer 8
Bottom part down source region 7；Formed after the source region 7 of the bottom part down of fluted body dielectric layer 8 is etched away
Pattern on form metal level 9, and make metal lead wire.Due to carrying out the doping of intrinsically polysilicon layer 4
When making grid 6, together with the injection for having carried out source region 7, the photoetching for carrying out source region 7 again is avoided
And injection process, reduce the making link of the repetition of VDMOS device, reduce VDMOS device
Cost of manufacture.And it ensure that the high-performance of VDMOS device.
Fig. 2 is the flow chart of the preparation method embodiment two of VDMOS device of the present invention, as shown in Fig. 2
The preparation method for the VDMOS device that this implementation provides is more highly preferred to compared to embodiment one for one
Embodiment, the then preparation method of VDMOS device that the present embodiment provides include following steps.
Step 201, using dry method thermal oxide growth technique, gate oxide 3 is grown in N-type epitaxy layer 2.
Further, the thickness of gate oxide 3 is 500-1500 angstroms.
Step 202, using chemical vapor deposition method, the deposition of intrinsic polysilicon layer on gate oxide 3
4。
Further, the thickness of intrinsically polysilicon layer 4 is 4000-8000 angstroms, it is preferable that intrinsic polycrystalline
The thickness of silicon layer 4 is 6000 angstroms.
Step 203, photoetching, etching are carried out to intrinsically polysilicon layer 4 and gate oxide 3, retains left and right
The gate oxide 3 and intrinsically polysilicon layer 4 of two side areas.
In the present embodiment, the realization of step 102 in the implementation and the embodiment of the present invention one of step 203
Mode is identical, and this is no longer going to repeat them.
Step 204, p-type ion implanting is carried out to VDMOS device and high temperature drives in, in N-type epitaxy layer
Formation body area 5 in 2.
Further, in the present embodiment, the ion of p-type ion implanting is boron ion, and dosage is
1.0E13-1.0E15 individual/square centimeter, energy can be 60-120KEV.
Further, the temperature that high temperature drives in is 900-1150 degrees Celsius, and the time that high temperature drives in is
50-300 minutes.
In the present embodiment, p-type ion implanting is carried out to VDMOS device and high temperature drives in, outside N-type
The thickness for prolonging the body area 5 of the formation in floor 2 is less than the thickness of N-type epitaxy layer 2, device profile Zhong Ti areas 5
Width be less than N-type epitaxy layer 2 width.
Step 205, using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, formation has
The grid 6 of saturation N-type polycrystalline silicon layer, source region 7 is formed in Bing Ti areas 5.
Step 206, dielectric layer 8 is formed on the pattern after forming source region 7, dielectric layer 8 is fluted body.
In the present embodiment, implementation and the step in the embodiment of the present invention one of step 205- steps 206
The implementation of 104- steps 105 is identical, and this is no longer going to repeat them.
Step 207, photoetching, etching are carried out to fluted body dielectric layer 8, etches away fluted body dielectric layer 8
Bottom, and retain the photoresist 10 of the top of dielectric layer 8 after carrying out photoetching, etching.
Further, Figure 10 is that the present invention performs the device profile structure after the step 207 of embodiment two
Schematic diagram, as shown in Figure 10, in the present embodiment, after photoetching, etching are carried out to fluted body dielectric layer 8,
The dielectric layer 8 of the bottom of groove dielectric layer 8 is etched away, retains the top of grid 6, grid 6 and gate oxide
The dielectric layer 8 of 3 sides, and retain the photoresist 10 of the top of dielectric layer 8 after carrying out photoetching, etching,
Subsequently to be performed etching to source region 7.
Step 208, under the stop of photoresist 10, source region 7 is continued to etch, etches away groove
The source region 7 of the bottom part down of type dielectric layer 8.
Further, in the present embodiment, using the photoresist 10 when carrying out 8 photoetching of dielectric layer, in light
Under the stop of photoresist 10, source region 7 is continued to etch, under the bottom for etching away fluted body dielectric layer 8
The source region 7 of side, until the upper surface in body area 5, retain the lower section of gate oxide 3 and in the side of gate oxide 3
The source region 7 of the lower section of dielectric layer 8, that is, retain the left and right region of original source region 7.
Step 209, the photoresist 10 of the top of dielectric layer 8 after carrying out photoetching, etching is got rid of.
In the present embodiment, after the source region 7 for the bottom part down for etching away fluted body dielectric layer 8, removal is fallen into
The photoresist 10 of the top of dielectric layer 8 after row photoetching, etching, it is specific to remove in technique the present embodiment
Do not limit.
Step 210, the pattern formed after the source region 7 of the bottom part down of fluted body dielectric layer 8 is etched away
Upper formation metal level 9, and make metal lead wire.
In the present embodiment, in the step 107 in the implementation and the embodiment of the present invention one of step 209
The implementation of step is identical, and this is no longer going to repeat them.
The preparation method for the VDMOS device that the present embodiment provides, by using dry method thermal oxide growth
Technique, gate oxide 3 is grown in N-type epitaxy layer 2, using chemical vapor deposition method, in grid oxygen
Change deposition of intrinsic polysilicon layer 4 on layer 3, photoetching is carried out to intrinsically polysilicon layer 4 and gate oxide 3, carved
Erosion, retain the gate oxide 3 and intrinsically polysilicon layer 4 in left and right sides region, VDMOS device is entered
Row p-type ion implanting and high temperature drive in, the formation body area 5 in N-type epitaxy layer 2, using POCl3 as
Reacting gas, intrinsic polysilicon doping is carried out, form the grid 6 with saturation N-type polycrystalline silicon layer, and
Source region 7 is formed in body area 5, dielectric layer 8 is formed on the pattern after forming source region 7, dielectric layer 8 is
Fluted body, photoetching, etching are carried out to fluted body dielectric layer 8, etch away the bottom of fluted body dielectric layer 8,
And retain the photoresist 10 of the top of dielectric layer 8 after carrying out photoetching, etching, in the stop of photoresist 10
Under, source region 7 is continued to etch, etches away the source region 7 of the bottom part down of fluted body dielectric layer 8,
The photoresist 10 of the top of dielectric layer 8 after carrying out photoetching, etching is got rid of, is situated between etching away fluted body
Metal level 9 is formed on the pattern formed after the source region 7 of the bottom part down of matter layer 8, and makes metal lead wire,
When carrying out dielectric layer 8 and source region 7 etches, photoresist 10 is reused, further reduces VDMOS
The making link of the repetition of device, reduce the cost of manufacture of VDMOS device.And it ensure that
The high-performance of VDMOS device.
Finally it should be noted that：Various embodiments above is merely illustrative of the technical solution of the present invention, rather than right
It is limited；Although the present invention is described in detail with reference to foregoing embodiments, this area it is common
Technical staff should be understood：It can still be repaiied to the technical scheme described in foregoing embodiments
Change, equivalent substitution either is carried out to which part or all technical characteristic；And these are changed or replaced
Change, the essence of appropriate technical solution is departed from the scope of various embodiments of the present invention technical scheme.
Claims (8)
- A kind of 1. preparation method of VDMOS device, it is characterised in that including：Gate oxide and the deposition of intrinsic polysilicon layer on the gate oxide are grown in N-type epitaxy layer；Photoetching, etching are carried out to the intrinsically polysilicon layer and the gate oxide, retain left and right sides area The gate oxide and intrinsically polysilicon layer in domain；Make the body area of the VDMOS device；Using POCl3 as reacting gas, intrinsic polysilicon doping is carried out, formation has saturation N-type polycrystalline The grid of silicon layer, and form source region in the body area；Dielectric layer is formed on the pattern after forming source region, the dielectric layer is fluted body；Photoetching, etching are carried out to fluted body dielectric layer, etches away the bottom of fluted body dielectric layer, and etch Fall the source region of the bottom part down of fluted body dielectric layer；Metal level is formed on the pattern formed after the source region of the bottom part down of fluted body dielectric layer is etched away, And make metal lead wire.
- 2. according to the method for claim 1, it is characterised in that described that fluted body dielectric layer is entered Row photoetching, etching, etch away the bottom of groove dielectric layer, and etch away the bottom of fluted body dielectric layer The source region of lower section specifically includes：Photoetching, etching are carried out to fluted body dielectric layer, etches away the bottom of fluted body dielectric layer, and retain Carry out the photoresist above the dielectric layer after photoetching, etching；Under the stop of the photoresist, source region is continued to etch, etches away fluted body dielectric layer The source region of bottom part down.
- 3. method according to claim 1 or 2, it is characterised in that described in N-type epitaxy layer Upper growth gate oxide and the deposition of intrinsic polysilicon layer on the gate oxide, are specifically included：Using dry method thermal oxide growth technique, gate oxide is grown in the N-type epitaxy layer；Using chemical vapor deposition method, the deposition of intrinsic polysilicon layer on the gate oxide.
- 4. according to the method for claim 3, it is characterised in that described to make the VDMOS The body area of device is specially：P-type ion implanting is carried out to the VDMOS device and high temperature drives in, in the N-type epitaxy layer Interior formation body area.
- 5. according to the method for claim 4, it is characterised in that the ion of the p-type ion implanting For boron ion, dosage is 1.0E13-1.0E15/square centimeter, and energy can be 60-120KEV.
- 6. the method according to claim 4 or 5, it is characterised in that the temperature that the high temperature drives in For 900-1150 degrees Celsius, the time that the high temperature drives in is 50-300 minutes.
- 7. according to the method for claim 3, it is characterised in that the thickness of the gate oxide is 500-1500 angstroms, the thickness of the intrinsically polysilicon layer is 4000-8000 angstroms.
- 8. according to the method for claim 7, it is characterised in that the thickness of the intrinsically polysilicon layer For 6000 angstroms.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108922852A (en) * | 2018-08-31 | 2018-11-30 | 江苏丽隽功率半导体有限公司 | A kind of compound grid structure power device of extension and preparation method thereof |
| CN113363156A (en) * | 2021-05-31 | 2021-09-07 | 电子科技大学 | Method for optimizing VDMOS processing technology |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030122196A1 (en) * | 2001-12-28 | 2003-07-03 | Han-Wook Hwang | Poly-crystalline thin film transistor and fabrication method thereof |
| US20080142799A1 (en) * | 2006-11-24 | 2008-06-19 | Nec Electronics Corporation | Semiconductor device having zener diode and method for manufacturing the same |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN104900526A (en) * | 2014-03-07 | 2015-09-09 | 北大方正集团有限公司 | VDMOS and manufacture method for the same |
-
2016
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030122196A1 (en) * | 2001-12-28 | 2003-07-03 | Han-Wook Hwang | Poly-crystalline thin film transistor and fabrication method thereof |
| US20080142799A1 (en) * | 2006-11-24 | 2008-06-19 | Nec Electronics Corporation | Semiconductor device having zener diode and method for manufacturing the same |
| CN104766799A (en) * | 2014-01-07 | 2015-07-08 | 北大方正集团有限公司 | Field effect transistor manufacturing method and corresponding field effect transistor |
| CN104900526A (en) * | 2014-03-07 | 2015-09-09 | 北大方正集团有限公司 | VDMOS and manufacture method for the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108922852A (en) * | 2018-08-31 | 2018-11-30 | 江苏丽隽功率半导体有限公司 | A kind of compound grid structure power device of extension and preparation method thereof |
| CN108922852B (en) * | 2018-08-31 | 2023-11-17 | 江苏丽隽功率半导体有限公司 | Epitaxial composite gate structure power device and manufacturing method thereof |
| CN113363156A (en) * | 2021-05-31 | 2021-09-07 | 电子科技大学 | Method for optimizing VDMOS processing technology |
| CN113363156B (en) * | 2021-05-31 | 2022-05-24 | 电子科技大学 | Method for optimizing VDMOS processing technology |
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