CN108054210B - Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof - Google Patents
Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof Download PDFInfo
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- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 31
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000009792 diffusion process Methods 0.000 title description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 210000000746 body region Anatomy 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 28
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910000676 Si alloy Inorganic materials 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000002513 implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000007669 thermal treatment Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
A manufacturing method of a groove type vertical double-diffused metal oxide transistor comprises the following steps: providing an N-type substrate, and sequentially forming an N-type epitaxial layer, a P-type body region, a first groove and a second groove on the N-type substrate; forming polysilicon on the gate oxide layers in the first and second trenches and on the P-type body region; carrying out heat treatment on the polysilicon, so that N-type impurities in the polysilicon enter the surface of the P-type body region adjacent to the polysilicon, an N-type source region is formed on the surface of the P-type body region adjacent to the polysilicon, and the polysilicon outside the groove is oxidized into silicon dioxide located on the N-type source region; forming a contact hole which penetrates through the silicon dioxide and the N-type source region on two sides of the first groove and the second groove and extends into the P-type body region; and forming a front metal layer and a back metal layer.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductor manufacturing processes, in particular to a groove type vertical double-diffusion metal oxide transistor and a manufacturing method thereof.
[ background of the invention ]
The trench-type VDMOS (vertical double-diffused metal oxide transistor) is widely applied to the field of switching power supplies. A groove type vertical double-diffusion metal oxide semiconductor transistor (groove type VDMOS for short) forms a channel by forming longitudinal diffusion distance difference after source ions and body ions are injected, and is widely applied to the fields of switching power supplies and synchronous rectification. Compared with a planar VDMOS, the trench VDMOS has very small internal resistance because a JFET area is eliminated.
However, the conventional trench-type VDMOS has problems of complicated process, high cost, and the like, and needs to be improved.
[ summary of the invention ]
It is an object of the present invention to provide a trench type vertical double diffused metal oxide transistor and a method for fabricating the same.
A manufacturing method of a groove type vertical double-diffused metal oxide transistor comprises the following steps:
providing an N-type substrate, and sequentially forming an N-type epitaxial layer, an initial oxide layer and a silicon nitride layer on the N-type substrate;
injecting and driving a P-type body region, so that a P-type body region is formed on one side, adjacent to the initial oxide layer, of the N-type epitaxial layer;
forming a first groove and a second groove which penetrate through the silicon nitride layer, the initial oxide layer and the P-type body region and extend into the N-type epitaxial layer;
forming gate oxide layers on the inner walls of the first groove and the second groove in the P-type body region and the N-type epitaxial layer;
removing the silicon nitride layer and the initial oxide layer;
forming polysilicon on the gate oxide layers in the first and second trenches and on the P-type body region;
carrying out heat treatment on the polysilicon, so that N-type impurities in the polysilicon enter the surface of the P-type body region adjacent to the polysilicon, an N-type source region is formed on the surface of the P-type body region adjacent to the polysilicon, and the polysilicon outside the groove is oxidized into silicon dioxide located on the N-type source region;
etching the silicon dioxide, the N-type source region and the P-type body region to form a contact hole which penetrates through the silicon dioxide and the N-type source region on two sides of the first and second grooves and extends to the P-type body region;
forming a front metal layer on the silicon dioxide, wherein the front metal is connected with the P-type body region through the contact hole;
and forming back metal on the surface of the N-type substrate far away from the N-type epitaxial layer.
In one embodiment, the initial oxide layer is grown on the N-type epitaxial layer, the initial oxide layer growth temperature is in the range of 900-1100 degrees celsius, and the thickness is in the range of 0.01-0.10 um.
In one embodiment, the silicon nitride layer is grown on the initial oxide layer, the growth temperature of the silicon nitride layer is in the range of 600-1100 ℃, and the thickness of the silicon nitride layer is in the range of 0.02-0.20 um.
In one embodiment, the implanted ions of the P-type body region include boron, the dose of the implantation is in a range of 1 power per square centimeter to 14 powers per square centimeter, and the energy of the implantation is in a range of 100KEV to 400 KEV; the step of performing the drive-in of the P-type body region is performed at a temperature in a range of 1100 degrees celsius to 1200 degrees celsius for a time in a range of 50 minutes to 200 minutes.
In one embodiment, the gate oxide layer is grown on the inner walls of the first and second trenches, the growth temperature of the gate oxide layer is in the range of 900-1200 ℃, and the thickness of the gate oxide layer is in the range of 0.01-0.20 um.
In one embodiment, the step of removing the silicon nitride layer and the initial oxide layer comprises: and stripping the silicon nitride layer and the initial oxide layer by adopting wet etching.
In one embodiment, the polysilicon is N-type doped polysilicon, the growth temperature of the polysilicon is in the range of 500-700 degrees celsius, and the thickness is in the range of 0.1-2 um.
In one embodiment, the temperature of the heat treatment is in the range of 900-1300 degrees celsius, and the thickness of the silicon dioxide oxidized by the polysilicon outside the trench is in the range of 0.1-2 um.
In one embodiment, the material of the front metal comprises an aluminum alloy, a silicon alloy, or a copper alloy, and the back metal comprises a composite layer of titanium, nickel, and silver.
A groove type vertical double-diffusion metal oxide transistor comprises an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type body area formed on the surface of the N-type epitaxial layer, an N-type source area formed on the surface of the P-type body area, a first groove and a second groove which penetrate through the N-type source area and the P-type body area and extend into the N-type epitaxial layer, a gate oxide layer formed on the inner wall of the first groove and the second groove, polycrystalline silicon positioned on the gate oxide layers in the first groove and the second groove, silicon dioxide formed on the gate oxide layers of the N-type source area and the first groove and the second groove and the polycrystalline silicon, a contact hole which penetrates through the silicon dioxide, the N-type source area and extends to the P-type body area, and a front metal oxide transistor which is arranged on the silicon dioxide and is connected with the P-type body area through the contact hole, And the back metal is arranged on the surface of the N-type substrate far away from the N-type epitaxial layer.
Compared with the prior art, the groove type vertical double-diffusion metal oxide transistor and the manufacturing method thereof have the following advantages: the method saves the step of dry etching of the polycrystalline silicon, reduces the cost and avoids various defects caused by the etching process of the polycrystalline silicon; the polycrystalline silicon which grows once is utilized, a polycrystalline silicon grid electrode and an N-type source region are formed simultaneously, and the process flow is greatly simplified; the thermal treatment of the polysilicon is adopted to form silicon dioxide which can be used as a dielectric layer before a metal layer is grown subsequently, so that the growth step of the dielectric layer is omitted, the cost is saved, and the process flow is simplified; and <4> the heat treatment of the polysilicon is adopted to form the N-type source region, so that the photoetching and injection of the N-type source region are omitted, the cost of the existing injection is very high, and the operation efficiency is lower.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without inventive efforts.
FIG. 1 is a flow chart of a method of fabricating a trench-type vertical DMOS transistor according to the present invention.
Fig. 2-10 are schematic structural diagrams of steps of a method for manufacturing the trench-type vertical double diffused metal oxide transistor shown in fig. 1.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-10, fig. 1 is a flow chart illustrating a method for fabricating a trench-type vertical double-diffused metal oxide transistor according to the present invention, and fig. 2-10 are schematic structural diagrams illustrating steps of the method for fabricating the trench-type vertical double-diffused metal oxide transistor shown in fig. 1. The manufacturing method of the groove type vertical double-diffusion metal oxide transistor comprises the following steps.
In step S1, referring to fig. 2, an N-type substrate is provided, and an N-type epitaxial layer, an initial oxide layer and a silicon nitride layer are sequentially formed on the N-type substrate. The initial oxide layer grows on the N-type epitaxial layer, the growth temperature of the initial oxide layer is within the range of 900-1100 ℃, and the thickness is within the range of 0.01-0.10 um. The silicon nitride layer grows on the initial oxide layer, the growth temperature of the silicon nitride layer is within the range of 600-1100 ℃, and the thickness of the silicon nitride layer is within the range of 0.02-0.20 um.
In step S2, referring to fig. 3, a P-type body region is implanted and driven, so as to form a P-type body region on a side of the N-type epitaxial layer adjacent to the initial oxide layer. Wherein the implanted ions of the P-type body region comprise boron, the dose of the implantation is in a range from 13 powers per square centimeter 1 to 14 powers per square centimeter 1, and the energy of the implantation is in a range from 100KEV to 400 KEV; the step of performing the drive-in of the P-type body region is performed at a temperature in a range of 1100 degrees celsius to 1200 degrees celsius for a time in a range of 50 minutes to 200 minutes.
In step S3, referring to fig. 4, a first trench and a second trench penetrating through the silicon nitride layer, the initial oxide layer and the P-type body region and extending into the N-type epitaxial layer are formed. The step may be to perform photolithography and etching (e.g., dry etching) to form the first and second trenches.
In step S4, referring to fig. 5, a gate oxide layer is formed on the inner walls of the first trench and the second trench in the P-type body region and the N-type epitaxial layer. The gate oxide layer grows on the inner walls of the first groove and the second groove, the growth temperature of the gate oxide layer is in the range of 900-1200 ℃, and the thickness of the gate oxide layer is in the range of 0.01-0.20 um.
In step S5, referring to fig. 6, the silicon nitride layer and the initial oxide layer are removed. Specifically, the silicon nitride layer and the initial oxide layer may be stripped using a wet etch.
In step S6, referring to fig. 7, polysilicon is formed on the gate oxide layers in the first and second trenches and on the P-type body regions. The polycrystalline silicon is N-type doped polycrystalline silicon, the growth temperature of the polycrystalline silicon is in the range of 500-700 ℃, and the thickness of the polycrystalline silicon is in the range of 0.1-2 um.
In step S7, referring to fig. 8, the polysilicon is heat-treated, so that N-type impurities in the polysilicon enter the P-type body region adjacent to the surface of the polysilicon, thereby forming an N-type source region on the surface of the P-type body region adjacent to the polysilicon, and the polysilicon outside the trench is oxidized to silicon dioxide on the N-type source region. Wherein, the temperature of thermal treatment is in the range of 900-1300 ℃, and the thickness of the silicon dioxide oxidized by the polysilicon outside the groove is in the range of 0.1-2 um.
Step S8, please refer to fig. 9, in which the silicon dioxide, the N-type source region and the P-type body region are etched, so as to form a contact hole penetrating through the silicon dioxide and the N-type source region at two sides of the first and second trenches and extending into the P-type body region.
In step S9, please refer to fig. 10, a front metal layer is formed on the silicon dioxide, and the front metal layer is connected to the P-type body region through the contact hole. The material of the front metal comprises aluminum alloy, silicon alloy or copper alloy.
In step S10, referring to fig. 10, a back metal is formed on the surface of the N-type substrate away from the N-type epitaxial layer. The back metal comprises a composite layer of titanium, nickel and silver.
Further, as shown in fig. 10, the trench-type vertical double diffused metal oxide transistor obtained by the manufacturing method includes an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type body region formed on the surface of the N-type epitaxial layer, an N-type source region formed on the surface of the P-type body region, a first trench and a second trench penetrating through the N-type source region and the P-type body region and extending into the N-type epitaxial layer, a gate oxide layer formed on the inner walls of the first trench and the second trench, polysilicon located on the gate oxide layers in the first trench and the second trench, silicon dioxide formed on the gate oxide layers of the N-type source region and the first trench and the second trench and the polysilicon, a contact hole penetrating through the silicon dioxide, the N-type source region and extending into the P-type body region, and a front metal oxide layer disposed on the silicon dioxide and connected to the P-type body region through the contact hole, And the back metal is arranged on the surface of the N-type substrate far away from the N-type epitaxial layer.
Compared with the prior art, the groove type vertical double-diffusion metal oxide transistor and the manufacturing method thereof have the following advantages: the method saves the step of dry etching of the polycrystalline silicon, reduces the cost and avoids various defects caused by the etching process of the polycrystalline silicon; the polycrystalline silicon which grows once is utilized, a polycrystalline silicon grid electrode and an N-type source region are formed simultaneously, and the process flow is greatly simplified; the thermal treatment of the polysilicon is adopted to form silicon dioxide which can be used as a dielectric layer before a metal layer is grown subsequently, so that the growth step of the dielectric layer is omitted, the cost is saved, and the process flow is simplified; and <4> the heat treatment of the polysilicon is adopted to form the N-type source region, so that the photoetching and injection of the N-type source region are omitted, the cost of the existing injection is very high, and the operation efficiency is lower.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A manufacturing method of a groove type vertical double-diffused metal oxide transistor is characterized by comprising the following steps: the manufacturing method comprises the following steps:
providing an N-type substrate, and sequentially forming an N-type epitaxial layer, an initial oxide layer and a silicon nitride layer on the N-type substrate;
injecting and driving a P-type body region, so that a P-type body region is formed on one side, adjacent to the initial oxide layer, of the N-type epitaxial layer;
forming a first groove and a second groove which penetrate through the silicon nitride layer, the initial oxide layer and the P-type body region and extend into the N-type epitaxial layer;
forming gate oxide layers on the inner walls of the first groove and the second groove in the P-type body region and the N-type epitaxial layer;
removing the silicon nitride layer and the initial oxide layer;
forming polysilicon on the gate oxide layers in the first and second trenches and on the P-type body region;
carrying out heat treatment on the polysilicon, so that N-type impurities in the polysilicon enter the P-type body region and are adjacent to the surface of the polysilicon, an N-type source region is formed on the surface of the P-type body region and is adjacent to the surface of the polysilicon, and the polysilicon outside the first and second trenches is oxidized into silicon dioxide located on the N-type source region;
etching the silicon dioxide, the N-type source region and the P-type body region to form a contact hole which penetrates through the silicon dioxide and the N-type source region on two sides of the first and second grooves and extends to the P-type body region;
forming front metal on the silicon dioxide, wherein the front metal is connected with the P-type body region through the contact hole;
and forming back metal on the surface of the N-type substrate far away from the N-type epitaxial layer.
2. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the initial oxide layer is formed by growing on the N-type epitaxial layer, the growth temperature of the initial oxide layer is in the range of 900-1100 ℃, and the thickness is in the range of 0.01-0.10 um.
3. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the silicon nitride layer grows on the initial oxide layer, the growth temperature of the silicon nitride layer is within the range of 600-1100 ℃, and the thickness of the silicon nitride layer is within the range of 0.02-0.20 um.
4. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the implanted ions of the P-type body region comprise boron, and the implanted dosage is 1 x 1013/cm2To 1X 1014/cm2In the range of 100 to 400 KEV; the step of performing the drive-in of the P-type body region is performed at a temperature in a range of 1100 degrees celsius to 1200 degrees celsius for a time in a range of 50 minutes to 200 minutes.
5. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the gate oxide layer grows on the inner walls of the first groove and the second groove, the growth temperature of the gate oxide layer is in the range of 900-1200 ℃, and the thickness of the gate oxide layer is in the range of 0.01-0.20 um.
6. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the step of removing the silicon nitride layer and the initial oxide layer comprises the following steps: and stripping the silicon nitride layer and the initial oxide layer by adopting wet etching.
7. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the polycrystalline silicon is N-type doped polycrystalline silicon, the growth temperature of the polycrystalline silicon is in the range of 500-700 ℃, and the thickness of the polycrystalline silicon is in the range of 0.1-2 um.
8. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the temperature of the heat treatment is within the range of 900-1300 ℃, and the thickness of the silicon dioxide oxidized by the polysilicon outside the first and second grooves is within the range of 0.1-2 um.
9. The method of claim 1, wherein the trench-type vertical double diffused metal oxide transistor comprises: the front metal comprises aluminum alloy, silicon alloy or copper alloy, and the back metal comprises a composite layer of titanium, nickel and silver.
10. A trench-type vertical double diffused metal oxide transistor made by the method of making a trench-type vertical double diffused metal oxide transistor according to any one of claims 1 to 9, wherein: the groove type vertical double-diffused metal oxide transistor comprises an N-type substrate, an N-type epitaxial layer formed on the N-type substrate, a P-type body region formed on the surface of the N-type epitaxial layer, an N-type source region formed on the surface of the P-type body region, a first groove and a second groove which penetrate through the N-type source region and the P-type body region and extend into the N-type epitaxial layer, a gate oxide layer formed on the inner wall of the first groove and the inner wall of the second groove, polycrystalline silicon positioned on the gate oxide layers in the first groove and the second groove, silicon dioxide formed on the gate oxide layers of the N-type source region and the first groove and the second groove and polycrystalline silicon, a contact hole penetrating through the silicon dioxide, the N-type source region and extending into the P-type body region, and a front metal oxide arranged on the silicon dioxide and connected with the P-type body region through the contact hole, And the back metal is arranged on the surface of the N-type substrate far away from the N-type epitaxial layer.
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| CN201711397391.5A CN108054210B (en) | 2017-12-21 | 2017-12-21 | Groove type vertical double-diffusion metal oxide transistor and manufacturing method thereof |
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| US6211018B1 (en) * | 1999-08-14 | 2001-04-03 | Electronics And Telecommunications Research Institute | Method for fabricating high density trench gate type power device |
| CN101719495A (en) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | Semiconductor device and manufacturing method thereof |
| CN104282572A (en) * | 2013-07-11 | 2015-01-14 | 北大方正集团有限公司 | VDMOS device manufacturing method |
| CN104835739A (en) * | 2014-02-10 | 2015-08-12 | 北大方正集团有限公司 | Manufacturing method of power transistor and power transistor |
| CN106298920A (en) * | 2015-05-29 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of the field effect transistor in contactless hole and the field effect transistor in contactless hole |
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| US6211018B1 (en) * | 1999-08-14 | 2001-04-03 | Electronics And Telecommunications Research Institute | Method for fabricating high density trench gate type power device |
| CN101719495A (en) * | 2008-09-30 | 2010-06-02 | 英飞凌科技奥地利有限公司 | Semiconductor device and manufacturing method thereof |
| CN104282572A (en) * | 2013-07-11 | 2015-01-14 | 北大方正集团有限公司 | VDMOS device manufacturing method |
| CN104835739A (en) * | 2014-02-10 | 2015-08-12 | 北大方正集团有限公司 | Manufacturing method of power transistor and power transistor |
| CN106298920A (en) * | 2015-05-29 | 2017-01-04 | 北大方正集团有限公司 | The manufacture method of the field effect transistor in contactless hole and the field effect transistor in contactless hole |
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