JPH09129868A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable integration with a fine CMOS, by using structure wherein the thermal treatment at a high temperature can be concentrated in the first half of a processes, in the case of forming a double diffusion MOS transistor. SOLUTION: In this semiconductor device, an output element 1 using a double diffusion MOS transistor wherein a body region 5 is formed on the surface of a semiconductor substrate by using a trench 8 before formation of a gate electrode 11, and a control circuit 2 using an MOS transistor wherein the profile of the impurity concentration of a channel 9 is defined after the formation of the body region 5 and before the formation of the gate electrode 11 are integrated.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device in which an output element controls a relatively high voltage and a large current.

[0002]

2. Description of the Related Art Conventionally, a MOSFET semiconductor device of this type has, as an output element, a MOS transistor (DMOS transistor) by double diffusion as shown in FIG.
And is used, the output element 1, n on n ⁺ -type substrate 3 ^- comprises a drain drift region 4, the n ^- and p-type body region 5 on the surface of the drain drift region 4, p ⁺ back gate region 6 and an n ⁺ source region 7, and a gate insulating film 10 extending over the n ⁻ drain drift region 4 with the p-type body region 5 as a channel, and a gate electrode via the gate insulating film 10. 11 is provided. In the p-type body region 5 described above, after the gate electrode 11 is formed, ion implantation using the gate electrode 11 as a mask,
It was formed by heat treatment at a high temperature of about 1140 ° C. On the other hand, MOS transistor in the control circuit 2, n on the n ⁺ -type substrate 3, as shown in FIG. 2 ^- comprises a drain drift region 4, its the n ^- gate insulating film 10 on the surface of the drain drift region 4 Through the gate electrode 11
From the surface of the n ⁻ drain drift region 4 to the gate electrode 11
Source / drain region 1 with ion implantation as a mask
5 is provided. The silicon surface immediately below the gate insulating film 10 is the channel region 9. The MOS transistor in the control circuit 2 controls the impurity concentration in the channel region 9 by ion implantation of impurities such as boron before forming the gate electrode 11 to control the threshold voltage of the MOS transistor. It was

[0003]

In this prior art, the impurity concentration in the channel region 9 is controlled by ion implantation of impurities such as boron before forming the gate electrode 11.
As shown in FIGS. 4A to 4C, DM is used as an output element.
When an OS transistor is used, in order to form the p-type body region 5, it is necessary to perform ion implantation using the gate electrode 11 as a mask and heat treatment at a high temperature of about 1140 ° C. after forming the gate electrode 11. Therefore, in the process of high-temperature heat treatment when forming the p-type body region 5, the impurities implanted into the channel region 9 of the MOS transistor in the control circuit 2 diffuse, and the impurity concentration profile in the channel region 9 changes. Will end up. Therefore, there is a drawback that the threshold value of the MOS transistor in the control circuit is not stable. A DMOS transistor, especially a VDMOS (Ve
A method of manufacturing a self-alignment process using a gate electrode is widely known as a vertical DMOS (transistor DMOS) transistor. In recent years, however, as shown in JP-A-4-229662 and JP-A-5-335582, different silicon substrates are used. The one using a trench formed by isotropic etching is drawing attention. As an advantage of the VDMOS using the trench, the on-state resistance (RJFET) generated when the current path is narrowed by the depletion layer spreading from the adjacent p-type body region to the n ⁻ drain drift region is logically 0, and accordingly, Cell miniaturization is possible.

An object of the present invention is to provide a MOS transistor (DMOS transistor) by double diffusion as an output element.
A semiconductor device using the above is to provide a semiconductor device in which the threshold value of the MOS type transistor in the control circuit is stable.

[0005]

According to a first aspect of the present invention, a semiconductor device in which a power element for output and a control circuit are monolithically integrated is provided with an n ^- drain drift region on an n-type substrate. n ^- drain drift region p-type body region in a surface of the from the surface of the p-type body region n ^- a groove reaching the drain drift region, along the side walls of the groove, the the surface of the p-type body region n ^- and n ⁺ source region formed in a depth not reaching the drain drift region, and the p ⁺ back gate region formed on the surface of the n ⁺ p-type body region other than the source region, the inner surface of the groove A vertical MOS transistor having a gate electrode provided via an insulating film is used as the power element, and a gate electrode provided on the surface of the n ⁻ drain drift region via the gate insulating film. A lateral MOS transistor having a pole and a source / drain diffusion region, and further having a diffusion region for controlling a threshold value of the MOS transistor in a channel region immediately below the gate insulating film is provided in the control circuit. A semiconductor device having a transistor is obtained.

According to a second aspect of the invention, there is provided a semiconductor device according to the first aspect, wherein the conductivity types of the respective regions are reversed.

According to the invention described in claim 3, in the method of manufacturing the semiconductor device according to claim 1 or 2,
After forming the p-type body region of the power element,
A method of manufacturing a semiconductor device, characterized in that ion implantation of impurities for controlling the threshold voltage of the lateral MOS transistor of the control circuit is performed is obtained.

[0008]

In the semiconductor device of the present invention, the output power element is n
⁺ N on the mold substrate ^- comprises a drain drift region, n ^- after the formation of the p-type body region in a surface of the drain drift region from the surface of the p-type body region n ^- a groove reaching the drain drift region, of the groove Along the side wall, an n ⁺ source region on the surface of the p type body region to a depth not reaching the n ⁻ drain drift region, ap ⁺ back gate region on the surface of the p type body region other than the n ⁺ source region, and the groove With a gate electrode having a gate insulating film interposed on the inner surface of the V
A DMOS and a control circuit using a MOS type transistor having a diffusion region such as boron by ion implantation or the like before forming a gate electrode are integrated. Therefore, it is possible to form the gate insulating film and the gate electrode after forming the p-type body region, and ion implantation of impurities such as boron is performed in the p-type power element to control the threshold voltage of the MOS type transistor in the control circuit. After forming the mold body region,
And it can be performed before the formation of the gate electrode. In order to control the threshold voltage of the MOS transistor in the control circuit, high temperature heat treatment for forming a deep diffusion layer is not required in the step after ion implantation of impurities such as boron, so that diffusion of impurities by heat treatment is not necessary. Is eliminated, and the threshold voltage of the MOS transistor in the control circuit is stabilized.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention and is a sectional view of a power IC using an n-type double diffused vertical MOSFET as an output element. Referring to FIG. 1, this power IC is a semiconductor device in which an output element 1 (output power element) and a control circuit 2 are monolithically integrated.

A vertical MOS transistor is used as the output element 1. This output element 1 is an n ⁺ type substrate 3
An n ⁻ drain drift region 4 is provided on the upper surface of the n ⁻ drain drift region 4, a p-type body region 5 is formed on the surface of the n ⁻ drain drift region 4, and a trench (groove) 8 reaching the n ⁻ drain drift region 4 from the surface of the p-type body region 5. And an n ⁺ source region 7 formed along the sidewall of the trench 8 on the surface of the p-type body region 5 to a depth not reaching the n ⁻ drain drift region 4.
A p ⁺ back gate region 6 formed on the surface of the p type body region 5 other than the n ⁺ source region 7, and a gate electrode 11 provided on the inner side surface of the trench 8 via a gate insulating film 10. It is equipped with.

On the other hand, as a transistor of the control circuit 2,
A lateral MOS transistor is used. This MOS
Type transistor has a gate electrode 11 provided on the surface of the n ⁻ drain drift region 4 via a gate insulating film 10.
And a source / drain diffusion region 15, and a diffusion region for controlling the threshold value of the MOS transistor in the channel region 9 immediately below the gate insulating film 10.

FIG. 2 is a manufacturing process diagram of the power IC shown in FIG. Referring to FIG. 2, this power IC is manufactured as follows. First, resistivity 0.001 to 0.006 Ωcm
An n ⁻ drain drift region 4 having a peak concentration of 1.0E16 cm ⁻³ and a depth of 7.5 μm is formed on the n ⁺ type substrate 3 by epitaxial growth (FIG. 2A). Next, a photoresist is applied, and the surface of the control circuit portion is selectively opened by a photolithography technique. Boron is ion-implanted at a dose of 1.3E13 and an energy of 100 keV, and the p-well region 12 is subjected to heat treatment at 1200 ° C. for 10 hours.
Is formed (FIG. 3B). Next, a nitride film is grown by CVD to a thickness of 1200 A, a photoresist is applied, and a photolithography technique is used to selectively open it. Boron is dosed with a nitride film mask at a dose of 2.5E13 and an energy of 1
Ion implantation at 00 keV and 98 in H2-02 atmosphere
By thermal oxidation at 0 ° C. for 400 minutes, the element isolation diffusion layer region 13 having a higher concentration than the p well region 12 and the locos oxide film 14 are formed.
Is formed (FIG. 3B). Next, boron is ion-implanted at a dose amount of 2.5E13 and energy of 70 keV on the entire surface of the output element, and is heat-treated at 1140 ° C. for 10 minutes to diffuse to a depth of about 1.5 μm from the surface to form the p-type body region 5. Formed (FIG. 3B). Next, a photoresist is applied and boron is selectively dosed from the surface of the p-type body region 5 by photolithography to a dose amount of 4.0E15,
Ion implantation with energy of 50 keV and 1000 ° C. 15
The p ⁺ back gate region 6 having a depth of about 1.5 μm is formed by heat treatment for 0 minutes (FIG. 3C). Next, a photoresist is applied and a dose amount of 1.0E1 of arsenic is selectively applied from the surface of the p-type body region 5 by the photolithography technique.
6. Ion implantation with energy of 70 keV and 1000 ° C
The n ⁺ source region 7 having a depth of about 0.3 μm is formed by heat treatment for 30 minutes (FIG. 3C). Next, a photoresist is applied, and M of the control circuit is formed by photolithography technology.
Boron for controlling the threshold value of the OS transistor is ion-implanted into the region forming the channel (FIG. 3C). Then allowed to CVD growth of the oxide film to a thickness of 3000A, by anisotropic etching using the selectively oxidized film as a mask from the surface of the p-type body region 5 by photolithography a photoresist, n ⁺ source Area 7
Is separated from the silicon surface by a depth of 2.0μ
m trenches 8 are formed (FIG. 3D). Next, the gate insulating film 10 is formed on the side surface and the bottom surface of the trench 8 by H2-.
Thermal oxidation is performed at 900 ° C. for 15 minutes in a 02 atmosphere to form a thickness of about 500 A, and a gate electrode 11 is formed in the trench 8 with polysilicon or the like (FIG. 3D). Then the normal M
A lateral n-type MOS transistor and a lateral p-type MOS transistor of the control circuit 2 are formed by using the OS process, and the control circuit is constituted by aluminum wiring (FIG. 3E).

[0013]

As described above, according to the present invention, by using the trench in the double diffused MOS transistor of the output element of the semiconductor device, the high temperature heat treatment is concentrated in the first half of the process, and the lateral MOS transistor of the control circuit is formed. There is an effect that unnecessary thermal history of the profile of the diffusion layer forming the layer can be eliminated and the threshold voltage can be stabilized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a power IC using an n-type double diffused vertical MOSFET as an output element according to an embodiment of the present invention.

2A to 2E are manufacturing process diagrams of the power IC shown in FIG.

FIG. 3 is a cross-sectional view of a power IC using a conventional planar type DMOS as an output element.

4A to 4C are manufacturing process diagrams of the power IC shown in FIG.

[Explanation of symbols]

1 Output Element 2 Control Circuit 3 n ⁺ Type Substrate 4 n ⁻ Drain Drift Region 5 p Type Body Region 6 p ⁺ Back Gate Region 7 n ⁺ Source Region 8 Trench 9 Channel Region 10 Gate Insulating Film 11 Gate Electrode 12 p Well Region 13 Element isolation diffusion layer area 14 Locos oxide film 15 Source / drain area

Claims (3)

[Claims] 1. A semiconductor device in which a power element for output and a control circuit are monolithically integrated, wherein an n ⁻ drain drift region is provided on an n type substrate, and the n ⁻ drain drift region is provided.
A p-type body region is formed on the surface of the drain drift region,
Wherein the surface of the mold body region n ^- drain and drift region to reach the groove, along the side walls of the groove, the n on the surface of the p-type body region ^- n ⁺ source formed in a depth not reaching the drain drift region Region, ap ⁺ back gate region formed on the surface of the p type body region other than the n ⁺ source region, and a gate electrode provided on the inner side surface of the groove with an insulating film interposed therebetween. The MOS transistor as the power element, the gate electrode provided on the surface of the n ⁻ drain drift region via the gate insulating film, and the source / drain diffusion region, and the channel directly below the gate insulating film. A lateral MOS transistor having a diffusion region for controlling the threshold value of the MOS transistor in the region is used as the transistor of the control circuit. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the conductivity types of the respective regions are reversed. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the threshold voltage of a lateral MOS transistor of the control circuit is controlled after forming the p-type body region of the power element. A method for manufacturing a semiconductor device, which comprises ion-implanting impurities to achieve the above.