USRE32800E - Method of making mosfet by multiple implantations followed by a diffusion step - Google Patents
Method of making mosfet by multiple implantations followed by a diffusion step Download PDFInfo
- Publication number
- USRE32800E USRE32800E US07/053,269 US5326987A USRE32800E US RE32800 E USRE32800 E US RE32800E US 5326987 A US5326987 A US 5326987A US RE32800 E USRE32800 E US RE32800E
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- 238000002513 implantation Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000009792 diffusion process Methods 0.000 title description 13
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 7
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 41
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 37
- 230000008569 process Effects 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims description 22
- 229910052796 boron Inorganic materials 0.000 claims description 18
- 229910052785 arsenic Inorganic materials 0.000 claims description 14
- -1 boron ions Chemical class 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 48
- 150000002500 ions Chemical class 0.000 claims 24
- 238000005530 etching Methods 0.000 claims 7
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000002344 surface layer Substances 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 32
- 230000000694 effects Effects 0.000 abstract description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 13
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 239000007943 implant Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000013459 approach Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present invention relates to a metal oxide semiconductor device and a process for fabricating such a device, more particularly to field effect transistors used in large scale integrated circuits and a process for fabricating such devices.
- Nonplanar-type devices have been proposed for such high performance LSI circuits, including a nonplanar diffusion self-aligned (DSA) MOS transistor and a VMOS transistor. These two nonplanar devices have three dimensional configurations, which increase the packing density of the LSI.
- the process for fabricating such devices include an epitaxial and a V-groove process which require a larger number of fabrication steps than that of the planar-type devices.
- Planar-type devices utilized for high performance LSI circuits have generally involved scaling down the physical dimensions of the transistor.
- the short channel lengths involved in such scaled down transistors have involved limitations from the electrical characteristics present in such scaled down devices.
- the limitations on such short channel device have been the following: limited drain voltage, threshold voltage (V T ) falloff, and impact ionization in the drain pinchoff region.
- the drain voltage is limited by punch-through voltage decrease, snap back and gate field plated P-N junction avalanche breakdown.
- the threshold voltage falloff is limited by the drain field induced barrier lowering and the drain and source junction doping profile and substrate doping concentration.
- the impact ionization in the drain pinchoff region leads to hot-electron injection into the gate oxide and the substrate electron current due to secondary impact ionization.
- One fabrication technology uses a high resistivity substrate and double channel implants, where a deep implant is used to increase the punch-through voltage and a shallow implant is used to control V T .
- a second approach has been a diffusion self-aligned MOS transistor or a double-diffused MOS transistor. This device causes double diffusion of P-type impurities from the same diffusion window, the process yields good short channel V T falloff and a source-drain breakdown control.
- a third approach has been a lightly doped drain-source (LDD) process and a quadruply self-aligned (QSA) process.
- LDD lightly doped drain-source
- QSA quadruply self-aligned
- the LDD structure introduces narrow, self-aligned N-regions between the channel and the N+ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity.
- the QSA MOS device includes four mutually self-aligned areas: a narrow polysilicon gate, shallow-source/drain to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal innerconnection.
- the present invention is an improved process for fabricating a high performance LSI device without the undesirable electrical characteristics of short channel MOS transistors in such circuits.
- the process reduces the characteristic problems associated with short channel devices having a channel length of one to two microns.
- the process includes diffusing a very light concentration of P type material, such as boron, to create a very lightly doped P-- substrate region.
- the source and drain regions are formed from the diffusion of a high concentration of N-type material, such as arsenic, to create an N+ region for the source and drain.
- a lighter concentration of N-type material is diffused in the region between the N+ material and the gate to create an N- region to reduce punch-through.
- a high concentration of P-type material, such as boron is implanted at the gate and drain area to form a P region to control the drain field and drain bias, such that the fields can be limited to the drains lightly doped area.
- a lighter concentration of P-type material is implanted beneath the gate to form a P- region to control the V T falloff for short channel devices.
- the concentration of boron at the source-gate area is similar to that in the double diffused (D 2 ) process of the applicant, but the triple diffused (D 3 ) process of the present invention does not require the high temperature drive because of the shallow and lightly doped N-source-drain implant.
- the triple diffusion process of the present invention is a highly localized process in which the special features are in effect independently adjustable.
- the N+ junction depth (X j ) can be driven independently.
- the N- junction depth (X j ) and length are adjustable according to device specifications through the undercutting of the polysilicon gate.
- FIG. 1 is a cross sectional view of a transistor device structure of the present invention
- FIG. 2 is a profile of the device structure of FIG. 1 taken along the lines 2--2 in FIG. 1;
- FIG. 3 illustrates the shallow boron implant step in the process
- FIG. 4 illustrates the device structure after the process steps of polygate photo resist patterning, plasma etching of the oxide and polysilicon, and undercutting of the polysilicon;
- FIG. 5 illustrates the diffusion of arsenic impurity material to the device structure
- FIG. 6 illustrates a light diffusion of arsenic material and boron implant
- FIG. 7 illustrates the process of driving the arsenic and boron impurities into the substrate and oxidizing the surface.
- FIG. 1 illustrates one FET of a large scale integrated circuit fabricated in accordance with the process of the present invention, the FET device being generally identified by the reference numeral 10.
- the substrate region 12 of the device is a silicon material lightly doped with a P-type material, such as boron, and designated as a P-- region.
- a gate 14 is separated from the silicon substrate 12 by a layer of silicon dioxide 15.
- a channel region 16 above the P-- region 12 and below the gate 14 is slightly heavier doped with a P-type material than substrate 12 and is designated as a P- region.
- a source 18 and drain 20 are formed by heavily doping a region of the substrate 12 on opposite sides of the gate 14 with an N-type material and designated as an N+ region.
- Two first regions 22 and 24 are doped with P-type material in a greater concentration than channel region 16, and designated as a P region, extending from beneath the edges of the gate 14 downwardly to the boundary of the N+ source 18 and drain 20.
- the P-type material implanted in regions 22 and 24 supports the shallow punchthrough and V T falloff.
- Two second regions 26 and 28 are lightly doped with an N-type material, such as arsenic, to create shallow N- regions between the gate 14 and the N+ source 18 and drain 20.
- the N- regions 26 and 28 reduce the depletion at the gate 14-drain 20 region and also reduce the overlap of the gate and drain, enhancing the effect of the double diffused P-type material in regions 22 and 24.
- FIG. 2 illustrates a profile of the concentration of N and P-type impurities implanted into the device 10, taken along the line 2--2 of FIG. 1.
- the heaviest implantation of N-type material is found in the source and drain regions 18 and 20.
- the regions 26 and 28 are lightly doped with an N-type material to form N- regions between the N+ regions 18 and 20 and the edges of the gate region 14.
- the profile of the impurity concentration in the channel region, located directly beneath the gate 14 includes the P-channel region 16 beneath the center of the gate 14 and extending to regions 22 and 24 on either side, which regions contain a greater concentration of P-type material.
- the process of manufacturing the field effect transistor 10 begins with oxidizing the upper surface of the silicon substrate 12. As illustrated in FIG. 3, a layer of silicon dioxide 40, approximately 300 angstroms thick, is grown atop the substrate 12. A first implantation 42 of a P-type material, such as boron, occurs after the formation of the silicon dioxide layer 40. The boron implantation occurs at an intensity of about 2 ⁇ 10 4 boron ions/cm 2 at an energy level of 40 Kev in accordance with known ion implantation techniques. The first diffusion 42 of P-type material supports the shallow punchthrough and adjustment of the V T falloff.
- a P-type material such as boron
- the next process steps for manufacturing the FET 10 is the beginning of the formation of the polysilicon gate .[.14.]. with the deposition of a layer .Iadd.14 .Iaddend.of polysilicon material with a depth of about 5,000 angstroms, using known deposition techniques.
- the layer of polysilicon material is next implanted with phosphorous, an N-type material.
- the layer of polysilicon material implanted with phosphorous is then oxidized .[.with.]. .Iadd.to form .Iaddend.a layer .Iadd.46 .Iaddend.of silicon dioxide .Iadd.hereinafter to be termed a polyoxide layer .Iaddend.approximately 1,500 angstroms in thickness.
- FIG. 4 illustrates the next three steps in the process of manufacturing the FET device 10.
- the first step is the covering of the polysilicon .[.gate.]. .Iadd.layer .Iaddend.14 with a layer of photoresist 44, .Iadd.patterning the resist in the usual fashion to essentially define the gate electrode portion .Iaddend.followed by a wet etching of the polysilicon oxide layer 46 and the plasma etching of the layer of polysilicon .[.of gate.]. 14 beneath it.
- the next step is the undercutting of the polysilicon layer of gate 14 beneath the polyoxide layer 46 .Iadd.to achieve the stage shown in FIG. 4.Iaddend.. The distance the polysilicon layer is undercut allows for the adjustment of the N- regions 26 and 28 (FIG. 1).
- the photoresist layer 44 is then stripped, using conventional techniques.
- FIG. 5 illustrates the implantation step 50 of an N-type material, such as arsenic, for forming the heavily doped N+ regions 18 and 20 for the source and drain of the FET 10.
- the energy of the arsenic ion is selected so as to penetrate only through the portions not covered by the .[.polysilicon oxide.]. .Iadd.polyoxide .Iaddend.layer 46.
- An intensity of about 2 ⁇ 10 16 arsenic ions/cm 2 with an energy level of 60 Kev is selected, using known ion implantation techniques.
- the .[.silicon dioxide.]. .Iadd.polyoxide .Iaddend.layer 46 is etched away.
- FIG. 6 illustrates an implantation step 52 of N-type material, such as arsenic, as indicated by the solid arrows, for forming regions 26 and 28.
- the intensity of the arsenic ions is 1 ⁇ 10 13 arsenic ions/cm 2 with an energy level of 60 Kev.
- the implantation step 52 provides a lightly doped area forming the N- region 26 and 28, which are between gate region 14, and a heavier N+ region 18 and 20 for the source and drain.
- a second implantation 54 of P-type material, such as boron is indicated by the dashed arrow in FIG. 6.
- An intensity of about 5 ⁇ 10 12 boron ions/cm 2 with an energy level of 35 Kev is used in accordance with known ion implantation techniques.
- the triple diffusion process is the implantation step 50 to form N+ regions 18 and 20, the implantation step 52 to form N- regions 26 and 28, and the implantation step 54 to form the P regions 22 and 24.
- FIG. 7 illustrates the next process step of thermally oxidizing the upper layer of the .[.FET 10, and the.]. .Iadd.silicon wafer to form layer 32.
- the .Iaddend.oxidation process drives the boron .[.D 2 .]. implantation to greater depths within the substrate 12.
- .Iaddend.a metalization process to form the contacts, .Iadd.and thus .Iaddend.the metal oxide semiconductor FET transistor structure 10 has been constructed.
- the process described above for manufacturing the metal oxide semiconductor FET 10 has a number of advantages over previous device processes.
- the principle advantage is the individual adjustment of special features of the device 10.
- the substrate 12 with it lightly doped P-- region has high resistivity.
- the N+ regions of the source 18 and drain 20 can be driven independently to adjust the penetration of the N+ region into the substrate.
- the double diffusion of the boron does not need as long a drive time as in previous processes, since the N- region is a lightly doped region of N-type material, and the double diffused boron can be driven at the same time the N- material is driven.
- the N- regions at the edge of gate 14 are adjustable according to manufacturer's specifications. As indicated above, the N- region can be controlled by the undercutting of the polysilicon gate 14. Finally, there is a small overlap capacitance between the polysilicon gate 14 and the source/drain in the semiconductor device 10 made in accordance with the present invention.
- the gate 14 had a length of approximately 1.5 microns
- the source and drain N+ region had a X j dimension of 0.7 microns
- the N- regions have a X j dimension of approximately 1.5 microns
- the P-type regions 22 and 24 had a thickness of approximately 0.3 microns.
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Abstract
Description
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US07/053,269 USRE32800E (en) | 1981-12-30 | 1987-05-21 | Method of making mosfet by multiple implantations followed by a diffusion step |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US33560881A | 1981-12-30 | 1981-12-30 | |
US07/053,269 USRE32800E (en) | 1981-12-30 | 1987-05-21 | Method of making mosfet by multiple implantations followed by a diffusion step |
Related Parent Applications (2)
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US33560881A Division | 1981-12-30 | 1981-12-30 | |
US06/654,281 Reissue US4599118A (en) | 1981-12-30 | 1984-09-24 | Method of making MOSFET by multiple implantations followed by a diffusion step |
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USRE32800E true USRE32800E (en) | 1988-12-13 |
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US07/053,269 Expired - Lifetime USRE32800E (en) | 1981-12-30 | 1987-05-21 | Method of making mosfet by multiple implantations followed by a diffusion step |
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Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4902636A (en) * | 1988-01-18 | 1990-02-20 | Matsushita Electric Works, Ltd. | Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device |
US4943537A (en) * | 1988-06-23 | 1990-07-24 | Dallas Semiconductor Corporation | CMOS integrated circuit with reduced susceptibility to PMOS punchthrough |
US4990974A (en) * | 1989-03-02 | 1991-02-05 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor |
US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
EP0513923A2 (en) * | 1991-05-15 | 1992-11-19 | Koninklijke Philips Electronics N.V. | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
US5187117A (en) * | 1991-03-04 | 1993-02-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
US5227321A (en) * | 1990-07-05 | 1993-07-13 | Micron Technology, Inc. | Method for forming MOS transistors |
US5367186A (en) * | 1992-01-28 | 1994-11-22 | Thunderbird Technologies, Inc. | Bounded tub fermi threshold field effect transistor |
US5369295A (en) * | 1992-01-28 | 1994-11-29 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor with reduced gate and diffusion capacitance |
US5426063A (en) * | 1993-03-24 | 1995-06-20 | Sharp Kabushiki Kaisha | Method of making a field effect transistor with submicron channel length and threshold implant using oblique implantation |
US5440160A (en) * | 1992-01-28 | 1995-08-08 | Thunderbird Technologies, Inc. | High saturation current, low leakage current fermi threshold field effect transistor |
US5525822A (en) * | 1991-01-28 | 1996-06-11 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor including doping gradient regions |
US5543654A (en) * | 1992-01-28 | 1996-08-06 | Thunderbird Technologies, Inc. | Contoured-tub fermi-threshold field effect transistor and method of forming same |
US5606191A (en) * | 1994-12-16 | 1997-02-25 | Mosel Vitelic, Inc. | Semiconductor device with lightly doped drain regions |
US5686324A (en) * | 1996-03-28 | 1997-11-11 | Mosel Vitelic, Inc. | Process for forming LDD CMOS using large-tilt-angle ion implantation |
US5780902A (en) * | 1995-12-25 | 1998-07-14 | Nec Corporation | Semiconductor device having LDD structure with pocket on drain side |
US5786620A (en) * | 1992-01-28 | 1998-07-28 | Thunderbird Technologies, Inc. | Fermi-threshold field effect transistors including source/drain pocket implants and methods of fabricating same |
US5796145A (en) * | 1993-12-13 | 1998-08-18 | Nec Corporation | Semiconductor device composed of MOSFET having threshold voltage control section |
US5814869A (en) * | 1992-01-28 | 1998-09-29 | Thunderbird Technologies, Inc. | Short channel fermi-threshold field effect transistors |
US5827747A (en) * | 1996-03-28 | 1998-10-27 | Mosel Vitelic, Inc. | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation |
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US4902636A (en) * | 1988-01-18 | 1990-02-20 | Matsushita Electric Works, Ltd. | Method for manufacturing a depletion type double-diffused metal-oxide semiconductor field effect transistor device |
US5122474A (en) * | 1988-06-23 | 1992-06-16 | Dallas Semiconductor Corporation | Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough |
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US5151759A (en) * | 1989-03-02 | 1992-09-29 | Thunderbird Technologies, Inc. | Fermi threshold silicon-on-insulator field effect transistor |
US4990974A (en) * | 1989-03-02 | 1991-02-05 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor |
US5100820A (en) * | 1990-06-14 | 1992-03-31 | Oki Electric Industry Co., Ltd. | MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode |
US5227321A (en) * | 1990-07-05 | 1993-07-13 | Micron Technology, Inc. | Method for forming MOS transistors |
US5525822A (en) * | 1991-01-28 | 1996-06-11 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor including doping gradient regions |
US5187117A (en) * | 1991-03-04 | 1993-02-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
EP0513923A2 (en) * | 1991-05-15 | 1992-11-19 | Koninklijke Philips Electronics N.V. | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
EP0513923A3 (en) * | 1991-05-15 | 1993-06-02 | N.V. Philips' Gloeilampenfabrieken | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
US5440160A (en) * | 1992-01-28 | 1995-08-08 | Thunderbird Technologies, Inc. | High saturation current, low leakage current fermi threshold field effect transistor |
US5374836A (en) * | 1992-01-28 | 1994-12-20 | Thunderbird Technologies, Inc. | High current fermi threshold field effect transistor |
US5814869A (en) * | 1992-01-28 | 1998-09-29 | Thunderbird Technologies, Inc. | Short channel fermi-threshold field effect transistors |
US5369295A (en) * | 1992-01-28 | 1994-11-29 | Thunderbird Technologies, Inc. | Fermi threshold field effect transistor with reduced gate and diffusion capacitance |
US5367186A (en) * | 1992-01-28 | 1994-11-22 | Thunderbird Technologies, Inc. | Bounded tub fermi threshold field effect transistor |
US5786620A (en) * | 1992-01-28 | 1998-07-28 | Thunderbird Technologies, Inc. | Fermi-threshold field effect transistors including source/drain pocket implants and methods of fabricating same |
US5543654A (en) * | 1992-01-28 | 1996-08-06 | Thunderbird Technologies, Inc. | Contoured-tub fermi-threshold field effect transistor and method of forming same |
WO1994011900A1 (en) * | 1992-02-11 | 1994-05-26 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
US5532508A (en) * | 1993-03-24 | 1996-07-02 | Sharp Kabushiki Kaisha | Semiconductor device with LDD structure |
US5426063A (en) * | 1993-03-24 | 1995-06-20 | Sharp Kabushiki Kaisha | Method of making a field effect transistor with submicron channel length and threshold implant using oblique implantation |
US5796145A (en) * | 1993-12-13 | 1998-08-18 | Nec Corporation | Semiconductor device composed of MOSFET having threshold voltage control section |
US5606191A (en) * | 1994-12-16 | 1997-02-25 | Mosel Vitelic, Inc. | Semiconductor device with lightly doped drain regions |
US5780902A (en) * | 1995-12-25 | 1998-07-14 | Nec Corporation | Semiconductor device having LDD structure with pocket on drain side |
US5686324A (en) * | 1996-03-28 | 1997-11-11 | Mosel Vitelic, Inc. | Process for forming LDD CMOS using large-tilt-angle ion implantation |
US5827747A (en) * | 1996-03-28 | 1998-10-27 | Mosel Vitelic, Inc. | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation |
US6261886B1 (en) * | 1998-08-04 | 2001-07-17 | Texas Instruments Incorporated | Increased gate to body coupling and application to DRAM and dynamic circuits |
US20100315070A1 (en) * | 2009-06-12 | 2010-12-16 | Wen-Jan Hong | Inclinometer |
US20110221000A1 (en) * | 2009-09-15 | 2011-09-15 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing semiconductor device |
US8841725B2 (en) * | 2009-09-15 | 2014-09-23 | Fujitsu Semiconductor Limited | Semiconductor device having channel dose region and method for manufacturing semiconductor device |
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