JP2003249650A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture in a process simpler than that for a conventional horizontal trench power MOSFET breakdown voltage of up to 80 V, while a device pitch is smaller and on resistance per unit area is smaller compared with the conventional horizontal trench power MOSFET having the breakdown voltage lower than 80 V. <P>SOLUTION: A thickness of a gate oxide film 59 along a side surface of a trench 51 is made thin and uniform. By selective oxidizing, a gate oxide film 83 along a bottom surface of the trench 51 is so formed as to be thicker than the gate oxide film 59 on the side surface of the trench, and further to get thicker as it approaches from an end of the bottom surface of the trench to a drain polysilicon 63. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an integrated circuit for controlling a large current with a high withstand voltage, such as a switching power supply IC, an automobile power system drive IC, a flat panel display drive IC, The present invention relates to a technology suitable for application to a low on-resistance power MOSFET (insulated gate field effect transistor) suitable for, for example, a trench lateral power MOSFET in which a gate electrode is provided in a trench formed by digging the surface of a semiconductor substrate.

[0002]

2. Description of the Related Art With the rapid spread of mobile devices and the sophistication of communication technology, power I incorporating a power MOSFET has been incorporated.
The importance of C is increasing. In the power IC in which the lateral power MOSFET is integrated in the control circuit, the power MOSFE
Compared to the conventional configuration in which the simple substance T is combined with the control drive circuit, it is expected that the size, the power consumption, the reliability, and the cost will be reduced. Therefore, high-performance lateral power MOSFETs based on the CMOS process have been actively developed. By the way, a MOSFET having a trench structure is known as a technique for reducing the device pitch and increasing the degree of integration. The present inventor has proposed a lateral power MOSFET to which a trench structure is applied (hereinafter referred to as a trench lateral power MOSFET) (for example, refer to Non-Patent Document 1). 31 to 33 are views showing the structure of this trench lateral power MOSFET, and FIG. 31 is a plan view. 32 is a cross-sectional view taken along the line AA in FIG. 31, showing the structure of a region that drives a current as an MOSFET (herein referred to as an active region). FIG. 33 is a cross-sectional view taken along the line BB of FIG. 31, showing a structure of a region (herein referred to as a gate region) for drawing out the gate polysilicon on the surface of the substrate.

This MOSFET 202 is a p ^- substrate 20.
A gate oxide film 22 is formed along the inner peripheral surface of the trench 21 formed in
And the bottom of the trench 21 and the trench 2 are formed.
N ⁺ diffusion region 2 serving as a drain region on the periphery of 1
9 and an n ⁺ diffusion region 27 serving as a source region are formed. The n ⁺ diffusion region 29 (drain region) is surrounded by an n ⁻ diffusion region 28 (n − drain region) that surrounds the lower half of the trench 21, and the n ⁻ diffusion region 28 serves as a p body. ^- diffusion region 31
It is surrounded by. n ⁺ diffusion region 27 (source region)
A p ⁺ diffusion region 32 is provided on the outer side of, and a p base region 33 is formed on the lower side. In addition, a thick oxide film 34 for ensuring the breakdown voltage is provided in the lower half of the trench 21. 31 to 33, reference numeral 24
Is a source electrode, reference numeral 25 is a drain electrode,
Reference numeral 26 is an interlayer oxide film, reference numeral 35 is a gate electrode, reference numerals 36 and 37 are both contact portions, reference numeral 38 is an n ⁺ diffusion region, and reference numerals 39 and 40 are both interlayer oxide films. is there. According to the trench lateral power MOSFET 202, the on-resistance per unit area is 80 mΩ · mm ² at a withstand voltage of 80V. The device pitch is 4 μm, which is about half the device pitch of the conventional lateral power MOSFET for a withstand voltage of 80V.

[0004]

[Non-Patent Document] IEDM '97 Digest, P.M.
359-362)

[0005]

Even in a lateral power MOSFET having a withstand voltage lower than 80V, for example, 30V, it is desirable to apply a trench structure in order to reduce the device pitch. However, FIGS.
The trench lateral power MOSFET 202 shown in FIG.
Since it has a structure suitable for a withstand voltage of V, if it is directly applied to a withstand voltage lower than 80V, the following problems occur. That is, when the breakdown voltage is lower than 80V, the thickness of the oxide film 34 for securing the breakdown voltage may be thinner than that for the breakdown voltage 80V. In other words, if the thickness of the oxide film 34 is set to a necessary and sufficient thickness for a breakdown voltage lower than 80V, the entire size can be further reduced. Nevertheless, when the structure for the withstand voltage of 80 V is applied, the size of the entire element becomes larger than that in the case where the thickness of the oxide film 34 for ensuring the withstand voltage is optimized, so that the wiring resistance around the element is large. There is a problem with the characteristics such as

The gate area is also the oxide film 3 for ensuring the breakdown voltage.
Since the thickness becomes too large as compared with the case where the thickness of 4 is optimized, the parasitic gate capacitance becomes large and the driving loss increases. In addition, the trench lateral power MOSFET described above
When manufacturing 202, a shallow trench is once dug, the side surface of the trench is protected by a nitride film, and then the trench is deepened to perform thermal oxidation to form a thick oxide film 34 for ensuring a withstand voltage. The manufacturing process is complicated,
There is a risk of lowering the yield. The present invention has been made in view of the above problems, and can be manufactured by simpler process steps than a conventional trench lateral power MOSFET for a withstand voltage of 80V, and a lateral type for a withstand voltage lower than the conventional 80V. Trench lateral power MOS optimized for withstand voltage lower than 80V, which has a smaller device pitch and smaller on-resistance per unit area than a power MOSFET
An object of the present invention is to provide a semiconductor device including an FET and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention provides a thick gate insulating film by forming a trench and a drift region in a semiconductor substrate and selectively oxidizing the bottom of the trench in a region corresponding to an active region. To form. In addition, a thin and uniform gate insulating film is formed along the side surface of the trench, and a first conductor to be gate polysilicon is formed inside the gate insulating film. Then, a base region and a source region are formed, a drain region is formed at the bottom of the trench, and a second conductor serving as drain polysilicon is provided inside the first conductor via an interlayer insulating film. In the present invention, the gate insulating film at the bottom of the trench is continuously thickened below the gate polysilicon toward the drain polysilicon. Also, trench MOSFE on the same substrate
In the case of a semiconductor device in which T and a planar MOSFET are integrated, the selective oxidation step at the bottom of the trench and the selective oxidation step for element isolation are shared.

According to the present invention, the MO is formed on the side of the trench.
Since the SFET is formed in a self-aligned manner, the mask alignment accuracy becomes unnecessary except for the selective oxidation step on the bottom surface of the trench, and the device pitch becomes small. Further, unlike the conventional trench lateral power MOSFET for a withstand voltage of 80 V, a thick oxide film for ensuring a high withstand voltage is not required, so that the gate area and the element size are reduced. Further, the number of times of trench etching is one in the manufacturing process.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In the following description, the first conductor is p-type and the second conductor is n-type. However, the present invention can be applied to the opposite case. Embodiment 1. FIG. 1 is a plan view showing an essential part of a trench lateral power MOSFET according to a first embodiment of the present invention. This trench lateral power MOSFET 1 is shown in FIG.
, A plurality of trenches 51 are formed in a stripe shape on the p-type substrate 50, a gate polysilicon 52 is formed so as to cross the trenches 51, a gate electrode 53 and a comb-shaped source electrode are formed on the substrate surface. 54 and the comb-teeth-shaped drain electrode 55 are formed.

The gate polysilicon 52 has a contact portion 5.
It is electrically connected to the gate electrode 53 via 6.
Although not shown in FIG. 1, the drain electrode 55 is electrically connected to the polysilicon in the trench 51 via the contact portion. The polysilicon is trench 5
It is electrically connected to the n ⁺ diffusion region 58 which will be the drain region at the bottom of 1. The source electrode 54 is electrically connected to the n ⁺ diffusion region 61 serving as the source region via the contact portion 57. In FIG. 1, a region other than the trench 51 on the substrate surface portion is a p base region. In addition, the p ⁺ diffusion region 41 and the trench 51 in the substrate surface portion
The region other than is the n ⁺ diffusion region 62.

Next, the cross-sectional structure of the active region that drives the current as the MOSFET will be described. Figure 2
FIG. 3 is a vertical cross-sectional view taken along the line C-C in FIG. 1, showing the configuration in the active region. The gate oxide film 59 serving as a gate insulating film is formed along the side surface of the trench 51 with a substantially uniform thickness. This gate oxide film 59 is formed in the trench 5
The bottom surface of the trench 51 is also covered, and the bottom surface of the trench 51 is thicker than the side surface of the trench 51. In FIG. 2, reference numeral 83 is a thick gate oxide film on the bottom surface. The gate polysilicon 52, which is the first conductor, is formed along the inside of the gate oxide film 59 and substantially above and below the trench 51. This gate polysilicon 5
2 extends to the gate region described below in connection with FIG.

The outer region of the lower half of the trench 51 is an n diffusion region 60 which becomes an n type drift region. In the n diffusion region 60, an n ⁺ diffusion region 58 serving as a drain region is provided at the center of the bottom of the trench 51.
The n ⁺ diffusion region 58 (drain region) is electrically connected to the drain electrode 55 via the drain polysilicon 63 which is the second conductor provided in the trench 51. The drain polysilicon 63 is insulated from the gate polysilicon 52 in the trench 51 by an interlayer oxide film 65 which is an interlayer insulating film. The outer region of the upper half of the trench 51 is the p base region 62, and the n ⁺ diffusion region 61 serving as the source region is formed in the substrate surface region on the p base region 62. n ⁺ diffusion region 61
The (source region) is the source electrode 5 formed on the substrate surface.
4 is electrically connected. The p base region 62 is electrically connected to the source electrode 54 via the p ⁺ diffusion region 41 at a portion where the n ⁺ diffusion region 61 is not provided at another place in plan view. In FIG. 2, reference numeral 66 is an interlayer oxide film (interlayer insulating film).

Next, the gate polysilicon 5 is formed on the surface of the substrate.
The cross-sectional structure in the gate region for drawing out 2 will be described. FIG. 3 is a vertical cross-sectional view taken along the line DD of FIG.
The structure in the gate region is shown. The outer region of the trench 51 is the n diffusion region 60. The gate oxide film 59 is formed along the side surface and the bottom surface of the trench 51. The gate oxide film 59 also covers the surface of the substrate. In FIG. 3, the gate oxide film 59 is the trench 51.
Is formed with a uniform thickness along the side surface and the bottom surface of the gate oxide film 59. However, similarly to the structure of the active region shown in FIG. It may be formed thick. Gate polysilicon 52 is formed on the surface of gate oxide film 59 along the substrate surface and the inner surface of trench 51.

An interlayer oxide film 67 is laminated on the surface of the gate polysilicon 52 along the gate polysilicon 52. The drain polysilicon 63 is provided in a portion of the trench 51 sandwiched by the interlayer oxide film 67 via the interlayer oxide film 65. An interlayer oxide film 66 is formed on the drain polysilicon 63 between the drain electrode 55 and the gate electrode 53. The gate region and the active region having the above structure are present in the same element.
Here, although not particularly limited, the dimensions of each part and the surface concentration of impurities are as follows. For example trench 51
, Its depth is 2 μm and its width is 3 μm. The pitch of the trenches 51 is, for example, 3 μm,
In the substrate surface area between the trenches 51 having a width of 3 μm, the p
The base region 62 and the n ⁺ diffusion region 61 to be the source region are formed. The diffusion depth of p base region 62 is, for example, 1 μm, and the surface concentration is, for example, 1 × 10 ¹⁸ c.
m ^-3 . Each of the n ⁺ diffusion region 58 (drain region) and the n ⁺ diffusion region 61 (source region) has, for example, a diffusion depth of 0.2 μm and a surface concentration of 1 × 10 ²⁰ cm ⁻³ . Further, for example, the n-diffusion region 60 (drift region) has a diffusion depth of 2 μm and a surface concentration of 2 × 10 ¹⁶ cm ⁻³ .

The thickness of gate oxide film 59 is, for example, 0.02 μm on the side surface of trench 51. The thickness of the gate oxide film 83 at the bottom surface of the trench 51 is continuously increased toward the drain polysilicon 63 which serves as a drain electrode below the gate polysilicon 52. The drain polysilicon 6 is formed below the gate polysilicon 52.
The thickness of the gate oxide film 83 at the position closest to 3 is t1.
(See FIG. 2), t1 is, for example, 0.22 μm. If the thickness of the gate polysilicon 52 is tp (see FIG. 2), tp is 0.3 μm, for example.
Next, the trench lateral power MO according to the first embodiment
The manufacturing process of the SFET 1 will be described. 4 to 14 are vertical cross-sectional views showing the main part of the lateral trench power MOSFET 1 in the manufacturing stage, but in these figures, only one trench 51 is shown. First, for example, a mask oxide film 71 having a thickness of 1 μm is grown on the surface of the p-type substrate 50 having a specific resistance of 12 Ωcm. Part of the mask oxide film 71 is selectively removed to open the trench formation portion. The patterned mask oxide film 7
A plurality of trenches 51 having an opening width of 3 μm are formed at intervals of 3 μm, for example, by RIE (reactive ion etching) using 1 as a mask. Then, by oblique ion implantation, an n diffusion region 60 to be a drift region is formed on the side surface and the bottom surface of the trench 51 of the substrate 50 (FIG. 4).

After removing the mask oxide film 71, a buffer oxide film 81 is formed to a thickness of 0.03 μm, for example.
A nitride film 82 having a thickness of 0.15 μm, for example, is deposited thereon. After that, a photoresist is applied, and by exposure and development, a part of the bottom surface portion of the trench 51 in the active region of the photoresist is selectively removed to form a resist mask. Using this resist mask, a part of the bottom surface portion of the trench 51 in the active region of the nitride film 82 is selectively removed. At that time, the nitride film on the bottom surface of the trench 51 in the gate region may be simultaneously removed. Then, the remaining resist mask is removed. By this step, the buffer oxide film 81 is exposed at a part of the bottom surface portion of the trench 51 in the active region. The distance between the exposed region of the buffer oxide film 81, that is, the region where the nitride film 82 is removed in the bottom surface portion of the trench 51 in the active region, and the end portion of the bottom surface of the trench is t2.
Then, t2 is, for example, 0.5 μm or more (FIG. 5).

Next, using the remaining nitride film 82 as a mask, thermal oxidation is performed at, for example, 1000 ° C. to obtain the nitride film 82.
A selective oxide film having a thickness of 0.6 μm, for example, is formed in the opening. This selective oxide film becomes the thick gate oxide film 83 at the bottom of the trench. Subsequently, the nitride film 82 and the buffer oxide film 81 are removed (FIG. 6). Next, after cleaning the side surface of the trench 51 by sacrificial oxidation, a gate oxide film 59 having a thickness of 0.02 μm, for example, is formed on the side surface and the bottom surface of the trench 51. Gate oxide film 59 extends over the surface of the substrate. Then, polysilicon 72 having a thickness of 0.3 μm, for example, is deposited on the gate oxide film 59. Further, an interlayer oxide film 67 having a thickness of 0.4 μm is deposited on polysilicon 72. After that, apply photoresist,
A resist mask 73 is selectively formed only in the gate region by exposure and development. The resist in the active area is removed. The interlayer oxide film 67 is selectively removed using this resist mask 73. By this step, the interlayer oxide film 67 is removed in the active region to expose the polysilicon 72 (FIG. 7). On the other hand, the interlayer oxide film 67 and the resist mask 73 remain as they are in the gate region (FIG. 8).

Subsequently, the remaining resist mask 73 is removed, and the polysilicon 72 is etched back by anisotropic etching. By this step, the polysilicon 72 is removed except the side surface of the trench 51 in the active region, and the polysilicon 72 remains only on the side surface of the trench 51. The remaining polysilicon 72 becomes the gate polysilicon 52 in the active region. In this etch back step, overetching is performed so that the upper end of the polysilicon 72 remaining in the active region is lower than the surface of the trench 51, that is, the surface of the first substrate. As a result, the upper end of the polysilicon 72 becomes lower than the upper surface of the gate oxide film 59 on the substrate surface by tov (tov: overetch amount).

Subsequently, drive heat treatment is performed after ion implantation is performed on the substrate surface. Thereby, in the active region, for example, a diffusion depth of 1 μm and a surface concentration of 1
A p base region 62 of ^{x10 18} cm ^-3 , an n ⁺ diffusion region 61 (source region) having a diffusion depth of 0.2 μm and a surface concentration of 1 × 10 ²⁰ cm ^-3 , for example, a diffusion depth of 0.2 μm.
Thus, a p ⁺ diffusion region 41 having a surface concentration of 1 × 10 ²⁰ cm ⁻³ is formed. The n ⁺ diffusion region 61 and the p ⁺ diffusion region 41 are appropriately separated by using a resist mask at the time of ion implantation (FIG. 9). On the other hand, in the gate region, the etching of the polysilicon 72 is blocked by the interlayer oxide film 67, so that the polysilicon 72 remains as the gate polysilicon 52 (FIG. 10).

Next, LP in an atmosphere around 400 ° C.
The interlayer oxide film 65 is laminated by a film forming method such as CVD or P-TEOS. By using such a film forming method, the growth rate of the interlayer oxide film 65 inside the trench 51 becomes about 50% of the growth rate of the interlayer oxide film 65 outside the trench 51, that is, on the substrate surface. Therefore, the thickness of the portion of the interlayer oxide film 65 deposited on the bottom surface of the trench 51 is smaller than the thickness of the portion on the substrate surface (FIG. 11 (active region), FIG. 12 (gate region)).
Subsequently, a photoresist is applied, and by exposure and development, a part of the bottom surface of the trench 51 in the active region of the photoresist is removed to form a resist mask. Using this resist mask, a part of the bottom surface portion of the trench 51 in the active region of the interlayer oxide film 65 and the thick gate oxide film 83 on the bottom surface portion of the trench is selectively removed to remove the interlayer oxide film 65 and the gate oxide film. A contact hole penetrating the film 83 is formed. Then, the remaining resist mask is removed. Next, an n ⁺ diffusion region 58 to be a drain region is formed by ion implantation at the bottom of the trench 51 in the active region (FIG. 13 (active region), FIG. 14 (gate region)).

Instead of selectively removing the interlayer oxide film 65 by photolithography and etching, the thickness of the thick gate oxide film 83 at the bottom of the trench, the polysilicon 72 to be the gate polysilicon 52, and the interlayer oxide film 65. Depending on the combination, it is possible to remove the interlayer oxide film 65 and the thick gate oxide film 83 in a self-aligned manner to open the contact hole.
Then, polysilicon is deposited, the trench 51 is etched back to fill the trench 51 with polysilicon 63, and an interlayer insulating film 66 is formed on the entire surface. The interlayer insulating film 66
A contact hole is opened in and a metal is deposited to form a gate electrode 53, a source electrode 54 and a drain electrode 55. As described above, the trench lateral power MOSFET having the sectional structure shown in FIG. 2 in the active region and the sectional structure shown in FIG. 3 in the gate region.
1 is completed.

Here, the above-mentioned three parameters t1,
Three examples in which the combinations of t2 and tp are changed are given, and the vertical cross-sectional structures along CC in FIG. 1 are shown in FIGS. In the first example shown in FIG. 15, t1 = 0.1
μm, t2 ≧ 0.7 μm and tp = 0.3 μm. In this first example, similar to the sectional structure shown in FIG.
The gate oxide film 83 on the bottom surface of the trench 51 is formed on the lower side of the gate polysilicon 52 by the drain polysilicon 6
It becomes thicker toward 3 continuously. In the second example shown in FIG. 16, t1 = 0.04 μm, t2 ≧ 0.9 μm and t
p = 0.3 μm. In this second example, the trench 5
The gate oxide film 83 on the bottom surface of No. 1 continuously becomes thicker toward the drain polysilicon 63 in a part of the lower side of the gate polysilicon 52.

In the third example shown in FIG. 17, t1 = 0.0.
2 μm, t2 ≧ 1.0 μm and tp = 0.3 μm. In the third example, the thickness of the gate oxide film 83 on the bottom surface of the trench 51 is uniform below the gate polysilicon 52. That is, the third example is an example in which the gate oxide film 83 does not become thicker toward the drain polysilicon 63 below the gate polysilicon 52. Next, the above three parameters t1, t2 and tp
The results of consideration of the preferable range or mutual relationship will be described. FIG. 18 shows 0.2 μm ≦ tp ≦ 0.7.
in the range of μm and 0.18 μm ≦ t2 ≦ 1.4 μm
It is a characteristic view which shows the result of having investigated the value of 1. Where t2
Is 0.18 μm or more because the total thickness of the buffer oxide film 81 and the nitride film 82 is 0.18 μm.
This is because m.

As is apparent from FIG. 18, t2 = tp +
The value of t1 is 0.02 μm under the condition of 0.7 μm. That is, the gate oxide film 83 at the position below the gate polysilicon 52 and closest to the drain polysilicon 63.
Has a thickness t1 of 0.02 μm. On the other hand, as described above, the thickness of the portion of the gate oxide film 59 along the side surface of the trench 51 is 0.02 μm. Therefore, under this condition (t2 = tp + 0.7 μm), the gate oxide film 83
The thickness of the portion of the gate polysilicon 52 below the gate polysilicon 52 closest to the drain polysilicon 63 is the same as the thickness of the gate oxide film 59 along the side surface of the trench 51.

Under the condition that t2 = tp + 0.6 μm, t
The value of 1 is 0.03 μm or more. Also, t2 = tp +
Under the condition of 0.4 μm, the value of t1 is 0.07 μm or more. Further, under the condition that t2 = tp + 0.2 μm, the value of t1 is 0.18 μm or more. That is, if the value of t2 satisfies 0.18 μm ≦ t2 ≦ tp + 0.6 μm,
The thickness of the gate oxide film 83 below the gate polysilicon 52 and closest to the drain polysilicon 63 is larger than the thickness of the portion of the gate oxide film 59 along the side surface of the trench 51. Also, a trench lateral power MOSF
When the withstand voltage of ET was examined, the value of t2 was 0.18 μm.
The breakdown voltage is highest when ≦ t2 ≦ tp + 0.2 μm, followed by the breakdown voltage when tp + 0.2 μm ≦ t2 ≦ tp + 0.4 μm, and then tp + 0.4 μm ≦ t2 ≦ t
This is when p + 0.6 μm. The reason why the breakdown voltage is improved is that the thickness of the gate oxide film 83 adjacent to the drain polysilicon 63 is increased and that the gate oxide film 83 is increased.
When performing the selective oxidation for manufacturing the trench 51
This is because the trench corners on the bottom surface of the are rounded.
The reason why the breakdown voltage becomes higher in the above-described order is that the gate oxide film 83 adjacent to the drain polysilicon 63 becomes thicker in this order.

FIG. 19 is a characteristic diagram showing the relationship between the on-resistance RonA and the breakdown voltage BV of the trench lateral power MOSFET of the first embodiment and the parameter t1. Here, the film thickness tp of the gate polysilicon 52 is set to 0.3 μm. The on-resistance was almost constant regardless of the value of t1, and was about 13 mΩ · mm ² . The on-resistance is almost constant because the resistance of the p-base region 62 in the channel region facing the gate oxide film 59 on the trench sidewall is dominant in the on-resistance. The withstand voltage is 15 V when the value of t1 is the same (0.02 μm) as the film thickness of the gate oxide film 59 on the side wall of the trench, and the withstand voltage is increased with the increase of t1, and the value of t1 is 0.3.
It exceeded 30 V at 7 μm or more.

According to the first embodiment described above, MOSFETs are formed on the sides of the trench 51 in a self-aligned manner. Therefore, except for the selective oxidation step for forming the thick gate oxide film 83 on the bottom surface of the trench. The mask alignment accuracy becomes unnecessary, and the device pitch can be reduced. Further, according to the first embodiment, it is necessary to form a thick oxide film on the trench side portion for ensuring a high breakdown voltage, as in the conventional trench lateral power MOSFET for breakdown voltage 80V (see FIGS. 31 to 33). Therefore, the gate area and the element size are smaller than those of the trench lateral power MOSFET for the withstand voltage 80V. Therefore, it is possible to avoid characteristic deterioration such as an increase in wiring resistance and an increase in drive loss that may occur when the conventional trench lateral power MOSFET for a withstand voltage of 80V is applied for a withstand voltage of 30V.

Further, according to the first embodiment, the parasitic capacitance generated between the substrate and the element is reduced, and the wiring length of the gate, the source and the drain is shortened, so that the parasitic wiring resistance is reduced. Therefore, high speed can be realized as a switching element, and switching loss is reduced. In addition, it is possible to reduce the influence of noise on adjacent elements. Further, according to the first embodiment, since the trench etching only needs to be performed once in the manufacturing process,
It can be manufactured by simpler process steps than the conventional trench lateral power MOSFET for a breakdown voltage of 80 V in which trench etching is performed twice, and it is possible to prevent a decrease in yield. Embodiment 2. Next, the trench lateral power MOSFET according to the first embodiment is replaced with a P-type planar MOSF.
A semiconductor device integrated on the same substrate together with ET (hereinafter referred to as PMOS) and N-type planar MOSFET (hereinafter referred to as NMOS) will be described. Figure 20
FIG. 4 is a vertical cross-sectional view of an active region of the semiconductor device that drives current as a MOSFET. As shown in FIG. 20, this semiconductor device is provided on the same p-type substrate 150.
Trench lateral power MOSFET 101 and PMOS 10
2 and one each of the NMOS 103 are manufactured. However, one is shown in each of FIG. Trench lateral power MOSFET 10
1, the PMOS 102 and the NMOS 103 are isolated from each other by a selective oxide film 193 for element isolation.

First, the trench lateral power MOSFET 1
The configuration of 01 will be described. A p-type well region 110 is formed in the p-type substrate 150, and the trench lateral power MOSFET 101 is formed in the p-type well region 110. Gate oxide film 15 serving as a gate insulating film
9 is formed with a uniform thickness along the side surface of the trench 151. The gate oxide film 159 is connected to the gate oxide film 183 on the bottom surface of the trench 151. The gate oxide film 183 on the bottom surface of the trench is formed thicker than the gate oxide film 159 on the side surface of the trench. The gate polysilicon 152, which is the first conductor, is formed along the inside of the gate oxide film 159 on the side surface of the trench and substantially above and below the trench 151.

The outer region of the lower half of the trench 151 is n
The n diffusion region 160 serves as a drift region of the mold. The outside of the n diffusion region 160 is the p-type well region 110. The lateral trench power MOSFET 101 may be formed not in the p-type well region 110 but in a p-type portion outside the n-type well region 120 of the PMOS 102 described later. In the n diffusion region 160, an n ⁺ diffusion region 158 serving as a drain region is provided at the center of the bottom of the trench 151. The n ⁺ diffusion region 158 (drain region) is the gate polysilicon 15
Drain polysilicon 1 that is a second conductor provided inside 2 via an interlayer oxide film 165 that is an interlayer insulating film
It is connected to 63. The drain polysilicon 163 is connected to the drain electrode 155. Interlayer oxide film 16
Reference numeral 5 covers the surface of the substrate, and an interlayer oxide film 166 is further laminated thereon.

An outer region of the upper half of the trench 151 is a p base region 162, and an n ⁺ diffusion region 161 serving as a source region is formed in a substrate surface region on the p base region 162. The n ⁺ diffusion region 161 (source region) is
It is electrically connected to the source electrode 154 formed on the surface of the substrate. The p base region 162 is electrically connected to the source electrode 154 at a portion where there is no n ⁺ diffusion region 161 at another place in plan view. Trench lateral power MOSF
The vertical sectional structure of the gate region of the ET101 is the same as in the first embodiment.
The configuration is the same as that shown in FIG. Therefore, the description of the structure of the gate region is omitted. In the trench lateral power MOSFET 101, the active region and the gate region having the above-described structure exist in the same element.

Next, the structure of the PMOS 102 will be described. The PMOS 102 is formed in the n-type well region 120 provided on the p-type substrate 150. The gate oxide film 129 serving as a gate insulating film is formed on the p ⁺ diffusion regions 121 and 121 to be source regions or drain regions (hereinafter referred to as source / drain regions) and the channel region between the two p ⁺ diffusion regions. 121, 121 are formed to overlap with each other. Gate oxide film 1
A gate conductor 1 which is a first conductor is formed on 29.
25 are formed. The gate polysilicon 125 is electrically connected to the gate electrode 123.

A source / drain electrode 124 to be a source electrode or a drain electrode is formed on each p ⁺ diffusion region 121.
Are formed, and each is electrically connected to the p ⁺ diffusion region 121. The gate electrode 123 and each source / drain electrode 124 are electrically insulated by the interlayer oxide films 165 and 166. In the example shown in FIG. 20, n
The type well region 120 is in contact with the p-type well region 110 below the selective oxide film 193. However, when the p-type well region 110 is not provided, the n-type well region 120 is terminated below the selective oxide film 193. Next, NMO
The configuration of S103 will be described. The NMOS 103 is
It is formed in the p-type well region 110. The gate oxide film 119 serving as a gate insulating film is formed on the n ⁺ diffusion regions 111, 111 serving as source / drain regions and the channel region between them in a state of overlapping with the n ⁺ diffusion regions 111, 111. There is. In addition, NMOS
103 is not in the p-type well region 110 but in the PMOS1
02 may be formed in the p-type portion outside the n-type well region 120.

A gate polysilicon 115, which is a first conductor, is formed on the gate oxide film 119. The gate polysilicon 115 is electrically connected to the gate electrode 113. The source / drain electrode 114, which serves as a source electrode or a drain electrode, is electrically connected to the n ⁺ diffusion region 111. Gate electrode 113 and each source /
The drain electrode 114 is electrically insulated by the interlayer oxide films 165 and 166. Here, although not particularly limited, the dimensions of each part of the trench lateral power MOSFET 101 and the surface concentration of impurities are as follows. For example, for the trench 151, its depth is 2 μm and its width is 3 μm. The pitch of the trenches 151 is, for example, 3 μm, and the trenches 151 each having a width of 3 μm.
The p base region 162 and the n ⁺ diffusion region 161 serving as a source region are formed in the substrate surface region therebetween. p
The diffusion depth of the base region 162 is, for example, 1 μm,
The surface concentration is, for example, 1 × 10 ¹⁸ cm ⁻³ . The n ⁺ diffusion region 158 (drain region) and the n ⁺ diffusion region 161 (source region) each have, for example, a diffusion depth of 0.2 μm and a surface concentration of 1 × 10 ^20.
cm ^-3 . Further, for example, the n diffusion region 160
The diffusion depth of the (drift region) is 2 μm, and the surface concentration is 2 × 10 ¹⁶ cm ⁻³ .

The p-type well region 110 has, for example, a diffusion depth of 6 μm and a surface concentration of 1 × 10 ¹⁷ cm.
^-3 . The thickness of the gate oxide film 159 is the trench 151.
Is 0.02 μm, for example. Trench 15
The thickness of the gate oxide film 183 at the bottom surface of the drain polysilicon 1 is below the gate polysilicon 152.
The thickness gradually increases toward 63. The thickness of the gate oxide film 183 at the position below the gate polysilicon 152 and closest to the drain polysilicon 163 is 0.22 μm, for example. Also, the gate polysilicon 152
Has a thickness of 0.3 μm, for example.

The PMOS 102 is not particularly limited.
The dimensions of each part and the surface concentration of impurities are as follows. For example, the diffusion depth of the n-type well region 120 is 6
μm, and the surface concentration is 1 × 10 ¹⁷ cm ⁻³ . p +
For the diffusion region 121, for example, the diffusion depth is 0.3.
μm, and the surface concentration is 1 × 10 ²⁰ cm ⁻³ . Gate oxide film 129 has a thickness of 0.02 μm, for example.
The thickness of the gate polysilicon 125 is 0.3 μm, for example.
Is. Although not particularly limited, the dimensions of each part of the NMOS 103 and the surface concentration of impurities are as follows. The diffusion depth and surface concentration of the p-type well region 110 are as described above. For n ⁺ diffusion region 111, for example, the diffusion depth is 0.3 μm and the surface concentration is 1 × 10 ²⁰ cm ⁻³ . Gate oxide film 119 has a thickness of 0.02 μm, for example. Gate polysilicon 11
The thickness of 5 is 0.3 μm, for example. The film thickness of the selective oxide film 193 for element isolation is, for example, 0.6 μm.

Next, a manufacturing process of the semiconductor device according to the second embodiment will be described. 21 to 30 are vertical cross-sectional views showing the main part in the manufacturing stage of the semiconductor device according to the second embodiment. In these drawings, one trench lateral power MOSFET 101, one PMOS 102 and one NMOS 103 are shown. First, a buffer oxide film having a thickness of 0.03 μm, for example, is formed on the surface of p type substrate 150 having a specific resistance of 12 Ωcm, and a nitride film having a thickness of 0.15 μm is deposited thereon by, for example, the CVD method. Further thereon, a photoresist is applied, exposed and developed to form a resist mask for forming the n-type well region 120. Using this resist mask, the portion of the nitride film on the formation region of the n-type well region 120 is selectively removed. After removing the resist mask, phosphorus is introduced into the p-type substrate 150 by ion implantation, for example, using the remaining nitride film as a mask.

After that, in a diffusion furnace, for example, 900 ° C.
Then, the region where the n-type well region 120 is formed is covered with an oxide film having a thickness of 0.4 μm, and the remaining nitride film is removed. Thereby, the p-type well region 1 is formed on the substrate surface.
A mask for forming 10 is formed. Using this oxide film as a mask, boron is introduced into p type substrate 150 by, for example, an ion implantation method. Subsequently, heat treatment is performed at 1100 ° C. in a diffusion furnace. by this,
The p-type well region 110 and the n-type well region 120 are completed on the p-type substrate 150. Then, the oxide film used as the ion implantation mask is removed (FIG. 21).

Subsequently, a thickness of 0.4 is formed on the surface of the substrate.
A μm mask oxide film 171 is grown by a CVD method or the like, and a part thereof is selectively removed to remove the p-type well region 110.
A trench forming portion is opened therein. RIE using the patterned mask oxide film 171 as a mask,
For example, a trench 151 having an opening width of 3 μm is formed with
A plurality is formed at m intervals. Then, by oblique ion implantation, an n diffusion region 160 serving as a drift region is formed in the side surface and the bottom surface of the trench 151 of the substrate 150 (FIG. 22). After removing the mask oxide film 171, a buffer oxide film 181 is formed to a thickness of 0.03 μm, for example, and a nitride film 182 having a thickness of 0.15 μm is formed thereon.
Deposit. After that, apply photoresist, expose,
By development, a trench 1 in the active area of the photoresist
A part of the bottom surface portion of 51 and the boundary portion between the p-type well region 110 and the n-type well region 120 are selectively removed to form a resist mask. Using this resist mask, a part of the bottom surface portion of the trench 151 in the active region and the boundary portion between the p-type well region 110 and the n-type well region 120 of the nitride film 182 are selectively removed. At that time, the nitride film on the bottom surface of the trench 151 in the gate region may be removed at the same time.

Then, the remaining resist mask is removed. By this step, the buffer oxide film 181 is exposed at a part of the bottom surface portion of the trench 151 in the active region and the boundary portion between the p-type well region 110 and the n-type well region 120. Here, in the bottom surface portion of trench 151 in the active region, the distance t2 between the region where nitride film 182 is removed and buffer oxide film 181 is exposed and the end portion of the bottom surface of the trench is 0.5 μm or more, for example. In the region including the boundary between p-type well region 110 and n-type well region 120, nitride film 182 is removed with a width of, for example, 5 μm to expose buffer oxide film 181 (FIG. 23).

Next, using the remaining nitride film 182 as a mask, thermal oxidation is performed at, for example, 1000 ° C. to obtain the nitride film 1.
The opening of 82 is selectively oxidized. As a result, a gate oxide film 183 having a thickness of 0.6 μm is formed on the bottom surface of trench 151. In addition, the p-type well region 110
A selective oxide film 193 for element isolation is formed at the boundary between the n-type well region 120 and the n-type well region 120. Subsequently, the nitride film 182 and the buffer oxide film 181 are removed (FIG. 24). Next, after cleaning the side surface of the trench 151 and the substrate surface by sacrificial oxidation, a gate oxide film 159 having a thickness of 0.02 μm, for example, is formed on the substrate surface and the side surface and the bottom surface of the trench 151. Then, the gate oxide film 159 and the selective oxide film 193 for element isolation are formed on the gate oxide film 159 and the element isolation film 193 with a thickness of, for example, 0.
Deposit 3 μm of polysilicon 172. Furthermore, a photoresist is coated on it, and the PMOS is exposed and developed.
The resist mask 168 is selectively formed only in the gate electrode formation portions of the NMOS transistor 102 and the NMOS 103 and the formation region of the trench lateral power MOSFET 101. (FIG. 25) Polysilicon 172 is formed using this resist mask 168.
Is etched back by anisotropic etching. By this step, the polysilicon 172 is removed in each formation region of the PMOS 102 and the NMOS 103 except the portion to be the gate electrode, and the polysilicon 172 remains only on the gate electrode. This remaining polysilicon 172 is PMO
S102 gate polysilicon 125 and NMOS1
03 gate polysilicon 115 (FIG. 26).

Then, the resist mask 168 is removed. At this time, the trench lateral power MOSFET 101
In the formation region of, the polysilicon 172 is exposed on the surface. A photoresist is applied again, and a resist mask 173 is selectively formed by exposing and developing except the active region of the trench lateral power MOSFET 101. Using this resist mask 173, the polysilicon 172 is etched back by anisotropic etching. By this step, in the active region of the trench lateral power MOSFET 101, the polysilicon 17 is removed except for the side surface of the trench 151.
2 is removed, and the polysilicon 172 remains only on the side surface of the trench 151. The remaining polysilicon 172 becomes the gate polysilicon 152 in the active region. In this etch back step, overetching is performed so that the upper end of the polysilicon 172 remaining in the active region is lower than the surface of the trench 151, that is, the surface of the first substrate. As a result, the upper end of the polysilicon 172 becomes lower than the upper surface of the gate oxide film 159 on the substrate surface (FIG. 27).

Subsequently, in order to form the p base region 162, for example, boron is ion-implanted into the surface of the substrate. After removing the resist mask 173, a resist mask is selectively formed only in the formation region of the PMOS 102 by applying, exposing, and developing a photoresist again, and, for example, arsenic is ion-implanted. After that, the resist mask is removed, and the PMOS 10 is coated again with photoresist, exposed, and developed.
A resist mask in which only the formation region of 2 is selectively opened is formed. Then, for example, by ion-implanting BF ₂ ,
The resist mask is removed. Subsequently, for example, a drive heat treatment at 800 ° C. is performed in a diffusion furnace. As a result, in the active region of the trench lateral power MOSFET 101, the surface concentration is 1 × 10 5 at a diffusion depth of 1 μm, for example.
A p base region 162 of ¹⁸ cm ^-3 and an n + diffusion region 161 (source region) having a diffusion depth of 0.2 μm and a surface concentration of 1 × 10 ²⁰ cm ^-3 are formed. Also, PMOS1
No. 02, the surface concentration is 1 × at a diffusion depth of 0.2 μm.
A p ⁺ diffusion region 121 of 10 ²⁰ cm ^-3 is formed. On the other hand, in the NMOS 103, for example, the diffusion depth is 0.2 μm.
Then, an n ⁺ diffusion region 111 having a surface concentration of 1 × 10 ²⁰ cm ⁻³ is formed (FIG. 28).

Next, LP in an atmosphere around 400 ° C.
The interlayer insulating film 165 is stacked by a film forming method such as CVD or P-TEOS. By using such a film forming method, the growth rate of the interlayer insulating film 165 inside the trench 151 is about 50% of the growth rate of the interlayer insulating film 165 outside the trench 151, that is, on the substrate surface.
Therefore, the thickness of the portion of the interlayer oxide film 165 deposited on the bottom surface of the trench 151 is thinner than the thickness of the portion on the substrate surface (FIG. 29). Subsequently, a photoresist is applied, and by exposure and development, a part of the bottom surface of the trench 151 in the active region of the photoresist is removed to form a resist mask. Using this resist mask, a part of the bottom surface portion of the trench 151 in the active region of the interlayer oxide film 165 and the thick gate oxide film 183 at the bottom surface portion of the trench is selectively removed, and the interlayer oxide film 16 is removed.
5 and a contact hole penetrating the gate oxide film 183 is formed. Then, the remaining resist mask is removed (FIG. 30).

Next, at the bottom of the active region trench 151, an n ⁺ diffusion region 158 to be a drain region is formed by ion implantation. Instead of selectively removing the interlayer oxide film 165 by photolithography and etching, a combination of the thicknesses of the thick gate oxide film 183 at the bottom of the trench, the polysilicon 172 to be the gate polysilicon 152, and the interlayer oxide film 165 is used. Is an interlayer oxide film 165 and a thick gate oxide film 18
It is also possible to remove 3 in a self-aligned manner and open a contact hole. Subsequently, polysilicon is deposited, the trench 151 is etched back to fill the trench 151 with polysilicon 163, and an interlayer insulating film 166 is formed on the entire surface. A contact hole is opened in the interlayer insulating film 166 and metal is deposited to form a trench lateral power MOS.
Source electrode 154 and drain electrode 1 of FET 101
55, the gate electrode 123 and the source / drain electrode 124 of the PMOS 102, and the gate electrode 113 and the source / drain electrode 114 of the NMOS 103 are formed. As described above, in the active region, the trench lateral power MOSFET 1 having the sectional structure shown in FIG.
A semiconductor device having 01, PMOS 102 and NMOS 103 is completed.

Next, a trench lateral power MOSFET
101, the parameter t2, the thickness tp of the gate polysilicon 152, and the gate polysilicon 15
The result of consideration of the preferable range of the thickness t1 of the gate oxide film 183 or the mutual relationship at a portion below the drain polysilicon 163 closest to the drain polysilicon 163 will be described.
0.2 μm ≦ tp ≦ 0.7 μm and 0.18 μm ≦ t
As a result of examining the value of t1 in the range of 2 ≦ 1.4 μm, the same result as that of the first embodiment was obtained. That is, 0.18μ
If m ≦ t2 ≦ tp + 0.6 μm, the thickness of the gate oxide film 183 at the position below the gate polysilicon 152 and closest to the drain polysilicon 163 is along the side surface of the trench 151 of the gate oxide film 159. Thicker than the thickness of the part.

Further, the trench lateral power MOSFET 1
As a result of investigating the breakdown voltage of No. 01, as in the first embodiment, 0.
The breakdown voltage is highest when 18 μm ≦ t2 ≦ tp + 0.2 μm, and then tp + 0.2 μm ≦ t2 ≦ tp + 0.4 μ
Withstand voltage is high when m, followed by tp + 0.4 μm ≦
This is when t2 ≦ tp + 0.6 μm. The reason why the breakdown voltage is improved in this way is that the thickness of the gate oxide film 183 adjacent to the drain polysilicon 163 is increased and that the bottom surface of the trench 151 is formed when the selective oxidation for forming the gate oxide film 183 is performed. This is because the trench corners are rounded. The reason why the breakdown voltage becomes higher in the order as described above is that the film thickness of the gate oxide film 183 adjacent to the drain polysilicon 163 becomes thicker in this order.

Next, a trench lateral power MOSFET
The results of examining the relationship between the on-resistance and breakdown voltage of 101 and the parameter t1 will be described. However, the film thickness tp of the gate polysilicon 152 was set to 0.3 μm. Similar to the first embodiment, the on-resistance was almost constant regardless of the value of t1 and was about 13 mΩ · mm ² . The reason why the on-resistance is almost constant is that the p base region 162 is
This is because the resistance in the channel region facing the gate oxide film 159 on the side wall of the trench is dominant in the on-resistance. The withstand voltage is 15 V when the value of t1 is the same (0.02 μm) as the film thickness of the gate oxide film 159 on the side wall of the trench, and the withstand voltage is increased as t1 is increased.
When the value of t1 was 0.37 μm or more, it exceeded 30V.

According to the second embodiment described above, the trench lateral power MOSFET 101 and the PMO are formed on the same substrate.
A semiconductor device in which S102 and NMOS 103 are integrated can be manufactured, whereby a semiconductor device in which trench lateral power MOSFET 101 and PMOS 102 and NMOS 103 are integrated on the same substrate can be obtained. Further, according to the second embodiment, the selective oxide film 193 for element isolation and the trench lateral power MOSFET 1 are formed.
Since the thick gate oxide film 183 on the bottom surface of the trench 01 can be formed in the same selective oxidation step, the manufacturing process can be simplified by doing so.

Further, according to the second embodiment, a power IC in which a conventional lateral power MOSFET and a control circuit are integrated.
More compactness, lower power consumption, higher reliability, and lower cost can be achieved. In the above, the present invention can be variously modified. For example, in the first or second embodiment, the dimensions, surface density, etc. of each part are variously set according to the required use.

[0051]

According to the present invention, MO is formed on the side of the trench.
Since the SFET is formed in a self-aligned manner, the mask alignment accuracy becomes unnecessary except for the selective oxidation step on the bottom surface of the trench, and the device pitch can be reduced. In addition, a conventional trench lateral power MOSF for a withstand voltage of 80 V is used.
Since a thick oxide film for ensuring a high withstand voltage unlike ET is not required, this trench lateral power M for a withstand voltage 80V is used.
The gate area and element size are smaller than those of the OSFET. Therefore, it is possible to avoid deterioration in characteristics that may occur when the conventional trench lateral power MOSFET for a breakdown voltage of 80V is applied for a breakdown voltage of 30V. In addition, since the trench etching only needs to be performed once in the manufacturing process, it can be manufactured by simpler process steps than the conventional trench lateral power MOSFET for a withstand voltage of 80 V, which performs the trench etching twice, thereby improving the productivity. In addition, it is possible to prevent a decrease in yield.

According to another invention, a semiconductor device in which a trench lateral power MOSFET, PMOS and NMOS are integrated on the same substrate can be manufactured, whereby a trench lateral power MOSFET, P can be formed on the same substrate.
A semiconductor device in which MOS and NMOS are integrated can be obtained. Further, the manufacturing process of the selective oxide film for element isolation and the manufacturing process of the thick gate oxide film on the bottom surface of the trench of the trench lateral power MOSFET can be made common, so that the manufacturing process can be simplified.
Further, it is possible to obtain a power IC that is smaller in size, consumes less power, has higher reliability, and is lower in cost than a conventional power IC in which a lateral power MOSFET and a control circuit are integrated.

[Brief description of drawings]

FIG. 1 is a plan view showing a main part of a trench lateral power MOSFET according to a first embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view taken along the line CC of FIG.

FIG. 3 is a vertical sectional view taken along the line DD of FIG.

FIG. 4 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 5 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 9 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 10 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 12 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 13 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 14 is a vertical cross-sectional view showing a main part in a manufacturing step of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 15 is a vertical cross-sectional view showing an example of another cross-sectional structure in FIG. 1C-C of the trench lateral power MOSFET according to the first exemplary embodiment of the present invention.

FIG. 16 is a vertical sectional view showing an example of another sectional structure of the trench lateral power MOSFET according to the first exemplary embodiment of the present invention in FIGS. 1C-C.

FIG. 17 is a vertical sectional view showing an example of another sectional structure of the trench lateral power MOSFET according to the first exemplary embodiment of the present invention in FIG. 1C-C.

FIG. 18 is a characteristic diagram showing a relationship between three parameters t1, t2 and tp of the trench lateral power MOSFET according to the first embodiment of the present invention.

FIG. 19 is a characteristic diagram showing the relationship between the on-resistance and breakdown voltage of the trench lateral power MOSFET according to the first embodiment of the present invention and t1.

FIG. 20 is a vertical sectional view showing a structure in an active region of a semiconductor device according to a second exemplary embodiment of the present invention.

FIG. 21 is a vertical cross-sectional view showing the main parts of the semiconductor device according to the second embodiment of the present invention at the manufacturing stage.

FIG. 22 is a vertical cross-sectional view showing the main parts in the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 23 is a vertical cross-sectional view showing a main part in a manufacturing step of the semiconductor device according to the second exemplary embodiment of the present invention.

FIG. 24 is a vertical cross-sectional view showing the main parts in the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 25 is a vertical cross-sectional view showing the main parts of the semiconductor device according to the second embodiment of the present invention at the manufacturing stage.

FIG. 26 is a vertical cross-sectional view showing the main parts at the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 27 is a vertical cross-sectional view showing the main parts in the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 28 is a vertical cross-sectional view showing the main parts at the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 29 is a vertical cross-sectional view showing the main parts at the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 30 is a vertical cross-sectional view showing the main parts at the manufacturing stage of the semiconductor device according to the second embodiment of the present invention.

FIG. 31 is a plan view showing a configuration of a conventional trench lateral power MOSFET.

32 is a vertical cross-sectional view showing the structure of the active region indicated by AA in FIG.

FIG. 33 is a vertical cross-sectional view showing the structure of the gate region indicated by BB in FIG. 31.

[Explanation of symbols]

1 semiconductor device (trench lateral power MOSFET) 50, 150 semiconductor substrate 51, 151 trench 52, 115, 125, 152, 172 first conductor (gate polysilicon) 53, 113, 123 gate electrode 54, 154 source electrode 55 , 155 drain electrode 58, 158 drain region (n ⁺ diffusion region) 59, 83, 119, 129, 159, 183 gate insulating film (gate oxide film) 60, 160 drift region (n diffusion region) 61, 161 source region ( n ⁺ diffusion region) 62, 162 base regions 63, 163 second conductor (drain polysilicon) 65, 66 interlayer insulating film (interlayer oxide film) 82, 182 nitride film 101 trench lateral power MOSFET 102, 103 planar MOSFET ( PMO
S, NMOS) 111 source / drain region (n ⁺ diffusion region) 114,124 source / drain electrode 120 well region 121 source / drain region (p ⁺ diffusion region) 165,166 interlayer insulating film (interlayer oxide film) 193 element isolation Selective oxide film for

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/08 102B 102C (72) Inventor Mutsumi Kitamura No. 1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Inside the Electric Co., Ltd. (72) Inventor Yoshio Sugi 1-1, Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Fuji Electric Co., Ltd. F-term (reference) 5F048 AA05 AA09 AC03 AC06 BB01 BB05 BB16 BB19 BC03 BD01 BD04 BD05 BD07 BE03 BF11 BF15 BF16 5F140 AA01 AA25 AA39 AB03 AB04 AC21 AC23 BB04 BC06 BC17 BF04 BF43 BF44 BF45 BG27 BG38 BH05 BH09 BH10 BH14 BH25 BH30 BH47 BJ04 BJ11 BJ15 BJ25 BJ27 BK09 BK13 CB01 BK13 BK14 BK14

Claims (12)

[Claims] 1. A trench provided in a semiconductor substrate of a first conductivity type, a source region of a second conductivity type formed in a substrate surface region outside the trench, and below the source region outside the trench. A first conductivity type base region formed on a side of the trench, a second conductivity type drift region formed below the base region along the side of the trench and outside the trench, and a bottom of the trench. A drain region of the second conductivity type formed in the trench, a gate insulating film formed inside the trench along a side portion and a bottom portion of the trench, and having a thicker bottom portion than the side portion of the trench; A first conductor formed inside the gate insulating film, and a second conductor formed inside the first conductor via an interlayer insulating film and electrically connected to the drain region. , The first conductivity The semiconductor device according to claim a gate electrode electrically connected to a source electrode electrically connected to the source region, by comprising a drain electrode electrically connected to the second conductor on. 2. The semiconductor device according to claim 1, wherein the drift region extends along a side portion of the trench. 3. The gate insulating film has a portion below the first conductor that continuously increases in thickness toward the second conductor. The semiconductor device described. 4. The portion of the gate insulating film located below the first conductor is a selective oxide film formed by selectively oxidizing the portion. Item 5. The semiconductor device according to any one of Items 1 to 3. 5. A semiconductor device in which the semiconductor device according to any one of claims 1 to 4 and a planar MOSFET are formed on the same substrate. 6. A step of forming a trench in a surface region of a semiconductor substrate of a first conductivity type, a step of forming a drift region of a second conductivity type around the trench, and a step of nitriding inside the trench and the surface of the substrate. A step of forming a film, and at least in a region corresponding to the active region, of the nitride film,
A step of removing a part of a portion covering the bottom of the trench, a step of performing selective oxidation using the nitride film as a mask, and a gate insulating film is formed inside the trench along the side portion of the trench. A step of forming a first conductor along the surface of the gate insulating film, and a step of etching back the first conductor so that it remains only on the side surface of the trench in a region corresponding to an active region. And a step of forming a first conductivity type base region and a second conductivity type source region in the substrate surface region outside the trench,
An interlayer insulating film is formed inside the first conductor, and a bottom portion of the interlayer insulating film is selectively removed in a region corresponding to an active region to form a drain region of the second conductivity type at a bottom portion of the trench. And a step of providing a second conductor electrically connected to the drain region in the trench. 7. When performing selective oxidation using the nitride film as a mask, the nitride film reaches the bottom surface of the trench, the film thickness tp of the first conductor and the nitriding from the end of the bottom surface of the trench. Distance t2 to the area where the film is removed
The relationship with is 0.18 μm ≦ t2 ≦ tp + 0.6 μm,
The method of manufacturing a semiconductor device according to claim 6, wherein 0.18 μm ≦ t2 ≦ tp + 0.4 μm is preferable, and 0.18 μm ≦ t2 ≦ tp + 0.2 μm is more preferable. 8. An interlayer insulating film is further formed on the surface of the substrate,
A contact hole is opened in the interlayer insulating film to form a gate electrode electrically connected to the first conductor, a drain electrode electrically connected to the second conductor, and a source electrode electrically connected to the source region. 8. The method of manufacturing a semiconductor device according to claim 6, further comprising the step of forming a source electrode to be connected. 9. A trench MOSFET and a planar MO.
In manufacturing a semiconductor device in which SFETs are integrated on the same substrate, a step of forming a second conductivity type well region in a part of a surface region of a first conductivity type semiconductor substrate, and a step of forming a well region of the second conductivity type outside the well region. Forming a trench in the trench MOSFET formation region; forming a second conductivity type drift region around the trench in the trench MOSFET formation region; forming a nitride film on the substrate surface and inside the trench Then, a part of the bottom of the trench in at least a region corresponding to the active region of the nitride film and a boundary portion between each element of the trench MOSFET and the planar MOSFET on the substrate surface are removed, and the remaining nitride film is used as a mask to form a selective oxide film. A step of forming a gate insulating film on the surface of the substrate and inside the trench, and Forming a first conductor along the surface of the gate insulating film above and inside the trench; and in a region corresponding to an active region, the first conductor is selectively oxidized on the substrate surface. Etching back so as to remain in a part of the region where the film is not formed, while remaining in only the side surface of the trench in the region where the trench is formed,
Forming a first conductivity type base region and a second conductivity type source region in a substrate surface region outside the trench in the trench MOSFET formation region;
Forming a source / drain region serving as a source or drain of the first conductivity type in the well region in the FET formation region, and a second conductivity type source or drain outside the well region in the planar MOSFET formation region Forming a source / drain region to be a source / drain region, and forming an interlayer insulating film on the first conductor in the planar MOSFET formation region and inside the first conductor in the trench, A step of selectively removing a bottom portion of the interlayer insulating film in the trench in a region corresponding to an active region to form a drain region of the second conductivity type in the trench bottom portion; and electrically connecting the drain region to the drain region in the trench. And a step of providing a second conductor to be connected to the semiconductor device. 10. When performing selective oxidation using the nitride film as a mask, the nitride film reaches the bottom surface of the trench, the film thickness tp of the first conductor and the nitriding from the end of the bottom surface of the trench. Distance t to the area where the film is removed
The relationship with 2 is 0.18 μm ≦ t2 ≦ tp + 0.6 μ
m, preferably 0.18 μm ≦ t2 ≦ tp + 0.4 μm
m, more preferably 0.18 μm ≦ t2 ≦ tp + 0.2
The manufacturing method of a semiconductor device according to claim 9, wherein the thickness is μm. 11. A step of forming the source region of the second conductivity type in the trench MOSFET formation region, and a step of forming the source / drain region of the second conductivity type outside the well region in the planar MOSFET formation region. 11. The process is the same process as in claim 9,
A method of manufacturing a semiconductor device according to item 1. 12. An interlayer insulating film is further formed on a substrate surface, a contact hole is opened in the interlayer insulating film, and a gate electrode electrically connected to the first conductor and the second conductor are formed. A drain electrode electrically connected, a source electrode electrically connected to the source region, a source / drain electrode electrically connected to the source / drain region of the first conductivity type, and a source / drain of the second conductivity type. 12. A method of manufacturing a semiconductor device according to claim 9, further comprising the step of forming a source / drain electrode electrically connected to the drain region.