JPH06151842A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To suppress the short-channel effect and generation of hot carriers and at the same time the increase in gate capacity in an insulated-gate transistor. CONSTITUTION:An element isolation region 2 is formed on a silicon substrate 1 and a recessed part is formed at a gate formation region. A gate oxide film 6 and a polysilicon gate electrode 7 are formed at the recessed part for forming a buried gate. A low-concentration impurity semiconductor region 11 is formed at both edges of the buried gate by ion implantation and a high-concentration impurity semiconductor region 12 is formed inside, thus forming source/drain. Short-channel effect is suppressed since the depth of the buried gate is the same as that of the source/drain and also the generation of hot carriers is suppressed by the low-concentration impurity semiconductor region 11. Also, the high-concentration impurity semiconductor region 12 is not in contact with the gate oxide film 6, thus suppressing the increase in gate capacity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device used in a MOS integrated circuit having an insulating gate arranged in a recess formed in a semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in an insulated gate transistor such as MOS or MIS, a short channel effect in which a threshold value decreases with a channel length or a hot electron effect in which hot electrons are generated by a strong electric field near a drain occurs. There was a problem. Therefore, in order to suppress the short channel effect and the hot electron effect, the junction between the source and the drain is substantially the same as or above the gate junction, as in the insulated gate transistor disclosed in JP-A-60-22372. Position, the short channel effect is suppressed, and the impurity concentration distribution in the drain junction is configured as n ⁺ −n ⁻ −P so that the depletion layer near the drain can more easily extend to the drain region and a strong electric field is generated. A technique has been proposed for preventing the hot electron effect and suppressing the hot electron effect.

FIG. 7 shows the structure of this conventional insulated gate transistor. On the P-type silicon substrate 20, a low concentration impurity region n ^- 23 and a high concentration impurity region n ⁺ 2
Source consisting of 4, the low concentration impurity region n ^- 25, drain composed of a high concentration impurity region n ⁺ 26 is formed, further the source, drain insulated gate buried consisting gate insulating film 21 and the polysilicon gate electrode 22 between Has been done. Since the insulated gate is buried, the junction between the source and the drain is substantially coincident with the interface between the gate insulating film 21 and the P-type silicon substrate 20, so that the threshold voltage has little dependence on the channel length and a short length. The channel effect can be suppressed. The drain junction n ⁺ -n ^-
Since it is -P, the electric field strength is weakened, and hot electron generation can be suppressed.

[0004]

As described above, in the buried gate type transistor, it is possible to suppress the deterioration of the basic characteristics of the transistor such as the short channel effect and the generation of hot carriers which become a problem when the element is miniaturized. However, there is a problem in that parasitic resistance and parasitic capacitance are increased.

That is, in the conventional buried gate type transistor shown in FIG. 7, since the low concentration impurity layer and the high concentration impurity layer overlap to form the source and the drain, the gate insulating film 21 and the high concentration impurity layer are formed. Since it is in direct contact with the impurity layer, the gate capacitance increases. Further, as miniaturization progresses, the contact hole also becomes smaller, so the contact resistance also increases.

The present invention has been made in view of the above problems of the prior art, and its purpose is to suppress the short channel effect and hot carrier generation at the time of miniaturization, and also suppress the increase of parasitic resistance and parasitic capacitance. It is an object of the present invention to provide a semiconductor device capable of achieving high integration of elements and a manufacturing method thereof.

[0007]

In order to achieve the above object, a semiconductor device according to claim 1 is provided with an insulated gate embedded in a semiconductor substrate and both ends of the insulated gate.
A source and a drain each having a low-concentration impurity semiconductor region and a high-concentration impurity semiconductor region inside the source and drain, and a wiring member directly connected to the high-concentration impurity semiconductor region of the source and the drain. The impurity semiconductor region and the insulated gate are not in contact with each other.

In order to achieve the above object, a method of manufacturing a semiconductor device according to a second aspect of the present invention includes a step of etching a gate formation region of a semiconductor substrate to form a recess.
Covering the inside of the recess with an insulating oxide film; depositing a gate member in the recess covered with the insulating oxide film to form a buried gate; forming an oxide film on the buried gate; A step of introducing impurities into the semiconductor surface by using the film as a mask to form low-concentration impurity semiconductor regions at both ends of the buried gate, and forming an oxide film on the surface of the semiconductor substrate and etching back to form an oxide film on the side of the buried gate. Forming a high-concentration impurity semiconductor region in the low-concentration impurity semiconductor region by introducing impurities into the semiconductor surface using the oxide film formed on the upper and side portions of the buried gate as a mask; A step of depositing a wiring member on the surface and creating a wiring pattern.

[0009]

In the semiconductor device of the present invention, since the high-concentration impurity semiconductor regions of the source / drain are present inside the low-concentration impurity semiconductor region, the gate capacitance can be kept small without directly contacting the insulated gate. it can. Further, in the semiconductor device of the present invention, since the wiring member is directly connected to almost the entire surface of the source / drain without providing a contact hole, it is possible to form a low resistance contact having a large contact area and to reduce the resistance of the diffusion layer. Can be very small.

Further, in the method of manufacturing a semiconductor device of the present invention, since the gate and the source / drain are formed in self-alignment, high integration of the element can be achieved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the main part of the structure of a semiconductor device according to this embodiment. A device isolation region (LOCOS) 2 is formed in the silicon substrate 1, and a recess is formed in the device isolation region 2. Then, a polysilicon gate electrode 7 covered with an insulating oxide film 6 is formed in this recess to form a buried type insulated gate. An oxide film 8 having a film thickness of 200 angstrom is formed on the polysilicon gate electrode 7. Then, a source / drain is formed at both ends of the insulated gate. The source / drain is composed of a low-concentration impurity semiconductor region 11 in which phosphorus is introduced into the silicon substrate 1 and a high-concentration impurity semiconductor region 12 inside thereof, and an oxide film 9 covering the side of the insulated gate is formed. The wiring material 13 is directly connected to the high concentration impurity semiconductor region 12 which is not present. In addition,
Below the element region in the silicon substrate 1, a threshold adjusting impurity layer 14 in which boron is introduced as an impurity is formed.

Here, what is characteristic of the semiconductor device of this embodiment is that the source / drain high-concentration impurity semiconductor regions 1 are formed.
2 is formed in the low concentration impurity semiconductor region 11 and is not in direct contact with the insulating oxide film 6 of the insulated gate.
As a result, it is possible to prevent an increase in gate capacitance and suppress deterioration of basic transistor characteristics. Also, wiring material 1
Since 3 is directly connected to the high-concentration impurity semiconductor region 12 not covered by the oxide film (sidewall) 9 formed on the buried insulating gate side without a contact hole, the contact area is large. The contact resistance can be kept small.

2 to 6 show a method of manufacturing the semiconductor device of this embodiment shown in FIG. First, as shown in FIG. 2, a P well and an element isolation region (LOCOS) 2 are formed on a silicon substrate 1 by a known method, and then SiO ₂ (pad oxide film) 3 is formed to 500 angstroms by thermal oxidation. Then, as impurities, 1 × 10
Boron of about ¹² / cm ² is ion-implanted to form the threshold adjusting impurity layer 14. Further, the SiN film 4 is deposited to 2000 angstrom by CVD (Chemical Vapor Deposition). Then, a region other than the gate formation region is covered with a resist, and the SiN film 4 and SiO ₂ in the gate formation region are covered.
The film 3 is removed by RIE (reactive ion etching), and the resist is peeled off.

Next, as shown in FIG. 3, the silicon substrate 1 is RI with the SiO ₂ film 3 and the SiN film 4 as a mask.
Etching is performed with E to form a recess 5 having a width of 0.35 μm and a depth of 0.15 μm, and a gate oxide film (insulating oxide film) 6 having a film thickness of 90 angstrom is formed by thermal oxidation.

After that, as shown in FIG. 4, about 3 polysilicon is filled on the entire surface so as to fill the formed recess 5.
After depositing 000 angstroms and introducing phosphorus to the gate as an impurity for reducing the resistance, the gate is etched back to form a polysilicon gate 7. Then, an oxide film 8 having a film thickness of 200 angstrom is formed on the polysilicon gate electrode 7 by thermal oxidation.

After that, as shown in FIG. 5, after removing the SiN film 4 by wet etching, about 1 × 10 ¹³ / cm ² of phosphorus is ion-implanted as an impurity into the source / drain, and both ends of the buried gate are implanted. Low-concentration impurity semiconductor layer n
^-Form 11 Then, a film thickness of 150 is formed by the CVD method.
A 0 Å oxide film is deposited and etched back to form a 1500 Å gate side oxide film (sidewall) 9. After forming the side wall 9, thermal oxidation is performed to form an oxide film 10 having a thickness of 40 Å, and then the source / drain, that is, the low-concentration impurity semiconductor region n ^- 11 has a high concentration of 1 × 10 ¹⁵ /
cm of arsenic As is ion-implanted and annealed to form a high-concentration impurity semiconductor region (n ⁺ ) 12. Therefore, this time the low concentration impurity semiconductor region n ^- source / drain 11 and a depth 0.15μm consisting internal high concentration impurity semiconductor region n ⁺ 12 that is formed. In addition,
Ion implantation conditions and annealing conditions for forming the source / drain regions are that the high-concentration impurity semiconductor regions 12 do not contact the gate oxide film 6 and that the low-concentration impurity semiconductor regions 1 are formed.
It is necessary to satisfy the following two conditions: 1. The lower part of the high-concentration impurity semiconductor region 12 is formed to the same depth as the gate oxide film 6.

Finally, as shown in FIG. 6, a wiring member 13 of Al alloy or the like is deposited by sputtering and patterned to complete the semiconductor device of this embodiment shown in FIG. Therefore, in FIG. 6, the wiring member 13 and the source / drain are connected without providing a contact hole, so that the contact area can be expanded and the contact resistance can be suppressed. Further, since the source / drain are formed by self-alignment, miniaturization can be achieved.

As described above, according to the semiconductor device and the method of manufacturing the same in this embodiment, since the source / drain having the depth of the buried gate and the depth of identification is formed, the short channel effect can be suppressed. it can. In addition, since the impurity concentration distribution of the drain junction is n ⁺ −n ⁻ −P,
The electric field strength near the drain can be weakened to suppress the hot electron effect.

Further, in this embodiment, since the high-concentration impurity semiconductor region n ⁺ is not in direct contact with the gate oxide film of the insulated gate, the gate capacitance does not increase and the basic characteristics (high frequency characteristics, etc.) are deteriorated. Can be suppressed.

[0021]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the short channel effect and the generation of hot carriers can be suppressed, and the increase of the gate capacitance can also be suppressed. The basic characteristics of the transistor can be improved.

Further, since the wiring material is connected to almost the entire surface of the source / drain diffusion layer without passing through the contact hole, the contact area can be increased and the contact resistance can be suppressed small.

Furthermore, since the source / drain diffusion layer and the wiring material can form a contact in self-alignment with the gate, it is possible to achieve high integration of devices such as a gate array.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing method according to the embodiment.

FIG. 3 is a diagram showing a manufacturing method according to the embodiment.

FIG. 4 is a diagram showing a manufacturing method in the embodiment.

FIG. 5 is a diagram showing a manufacturing method in the example.

FIG. 6 is a diagram showing a manufacturing method according to the embodiment.

FIG. 7 is a configuration diagram of a conventional semiconductor device.

[Explanation of symbols]

 1 Silicon substrate 2 Element isolation region 6 Gate oxide film (insulating oxide film) 7 Polysilicon gate electrode 8 Oxide film 9 Gate side oxide film (sidewall) 11 Low concentration impurity semiconductor region 12 High concentration impurity semiconductor region 13 Wiring member

Claims (2)

[Claims] 1. An insulated gate buried in a semiconductor substrate, a source and a drain which are provided at both ends of the insulated gate and which are composed of a low-concentration impurity semiconductor region and a high-concentration impurity semiconductor region therein, and a source and a drain of the source and the drain. A wiring member that is directly connected to the high-concentration impurity semiconductor region, and the high-concentration impurity semiconductor region of the source and drain and the insulated gate are not in contact with each other. 2. A step of etching a gate formation region of a semiconductor substrate to form a recess, a step of covering the inside of the recess with an insulating oxide film, and a step of depositing a gate member in the recess covered with the insulating oxide film. Forming an embedded gate by forming an oxide film on the embedded gate, and introducing an impurity into the semiconductor surface using the oxide film as a mask to form low-concentration impurity semiconductor regions at both ends of the embedded gate, Forming an oxide film on the surface of the semiconductor substrate and performing etch back to form an oxide film on the side portions of the buried gate; and introducing impurities into the semiconductor surface using the oxide film formed on the upper and side portions of the buried gate as a mask. And forming a high-concentration impurity semiconductor region in the low-concentration impurity semiconductor region, and depositing a wiring member on the surface of the semiconductor substrate to form a wiring pattern. A method of manufacturing a semiconductor device, comprising: