JP3714396B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an improvement of a semiconductor device formed on an SOI substrate (Silicon On Insulating Substrate) and a manufacturing method thereof.
[0002]
[Prior art]
Since a transistor using an SOI substrate is excellent in high-speed operation, research and development have been advanced. An SOI substrate is obtained by forming a semiconductor layer such as a silicon single crystal thin film on an insulator. For example, oxygen ions are implanted into a predetermined depth of a semiconductor substrate, and this is converted into an oxide film by heat treatment, thereby providing embedded insulation. Form a layer. In addition, an SOI substrate can be obtained by forming a silicon single crystal thin film on a semiconductor substrate having an oxide film formed on the surface by a bonding technique and a polishing technique. A device such as a MOSFET is formed on the SOI substrate. In order to form a large amount of MOSFETs and the like on an SOI substrate, miniaturization (scaling) of each device is required.
[0003]
[Problems to be solved by the invention]
However, when the device is scaled, the film thickness of the silicon single crystal thin film is further reduced, so that the film thickness of the source / drain region of the MOSFET is also reduced. For this reason, as shown in FIG. 4, when the interlayer insulating film is etched in the contact hole forming step, the silicon single crystal layer under the interlayer insulating film is also slightly removed (overetching). The silicon single crystal thin film thus formed is shaved relatively large, resulting in problems such as loss of the silicon single crystal thin film, an increase in parasitic resistance, and a low on-current value.
[0004]
Accordingly, an object of the present invention is to provide a semiconductor device capable of avoiding overetching of a silicon single crystal thin film on an SOI substrate.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device in which a MOSFET is formed on a semiconductor thin film formed on a semiconductor substrate through a buried insulating film, and the impurity concentration distribution in the source / drain regions of the semiconductor thin film There are two peaks of the impurity concentration distribution, the first peak of the impurity concentration distribution is present at substantially the center of the film thickness of the semiconductor thin film, and the second peak of the impurity concentration distribution is the inner surface of the semiconductor thin film. It exists in the vicinity, and the second peak is higher than the first peak.
[0006]
With such a configuration, the etching rate of the semiconductor thin film layer in the region into which the impurity is implanted at a high concentration is lowered. Therefore, when forming a contact hole in the interlayer insulating film, the semiconductor thin film (for example, a single crystal silicon thin film) It is possible to prevent the source / drain regions of the silicon oxide from being eroded by overetching. Further, by using an impurity (dopant) in the high-concentration impurity implantation region having an atomic weight larger than that of the impurity implanted to form the source / drain regions, the etching rate of the semiconductor thin film can be further reduced. It becomes possible.
[0007]
According to another aspect of the present invention, there is provided a semiconductor device in which a MOSFET is formed on a semiconductor thin film (for example, a single crystal silicon thin film) formed on a semiconductor substrate via a buried insulating film. A concentration distribution peak exists near the surface of the source / drain region. Thereby, it is possible to suppress the surface of the source / drain regions of the semiconductor thin film from being eroded. Preferably, the MOSFET has a lightly doped drain (LDD) structure to suppress hot carriers and facilitate device miniaturization.
[0008]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: an element isolation step for forming an element isolation region for insulating and isolating an element region in which a transistor is to be formed; A gate forming step of forming a gate in the semiconductor thin film in a region through a gate insulating film; and a first impurity injection step of forming a source / drain region by implanting impurities into the semiconductor thin film using the gate as a mask; A second impurity implantation step for implanting impurities near the surface of the source / drain region; an interlayer insulation film forming step for forming an interlayer insulation film on the semiconductor thin film in the element region; and covering the source / drain region wherein the interlayer insulating film and a contact hole formation step of forming a contact hole, wherein in the first impurity implantation step, the semiconductor thin that In the ion implantation conditions as the first peak of the impurity concentration distribution is formed in a substantially central portion of the film thickness is set, the in the second impurity implantation process, the impurity concentration distribution in the vicinity of the surface of the semiconductor thin film The ion implantation conditions are set such that the second peak is formed, the second peak is higher than the first peak, and the impurity in the second impurity implantation step is the first impurity implantation. The atomic weight is larger than the impurity of the process .
[0009]
Through this process, a high concentration impurity diffusion layer can be formed on the surface of the source / drain region.
[0010]
Preferably, the impurity in the second impurity implantation step has a larger atomic weight than the impurity in the first impurity implantation step. Further, the impurity implantation in the second impurity implantation step is higher in concentration than the first impurity implantation. In the second impurity implantation step, the ion implantation conditions are set so that the concentration distribution peak of the second impurity is near the surface of the source / drain region. Further, the impurities in the second impurity implantation step are activated by heat treatment and / or laser annealing (heat treatment or laser annealing or a combination of both).
[0011]
Since the etching rate of the semiconductor thin film tends to be lower as the impurity concentration is higher or the atomic weight of the impurity is larger, over-etching of the source / drain regions due to the etching process for forming contact holes is suppressed.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0013]
In the embodiment of the present invention, a high concentration and / or larger atomic weight impurity is implanted into the surface of the semiconductor layer in the source / drain region. Thereby, the etching rate of the surface of the source / drain region is lowered, and erosion of the source / drain region due to the etching for forming the contact hole is prevented.
[0014]
FIG. 1A shows an embodiment of a semiconductor device of the present invention, and shows an example in which a MOSFET is formed as an electric element on an SOI substrate. In the figure, a buried insulating film (oxide film) 2 is formed on a silicon substrate 1 as a semiconductor substrate. A silicon single crystal thin film 3 is formed on the buried insulating film 2 to obtain an SOI structure. Part of the silicon single crystal thin film 3 is used as an element isolation region by the field oxide film 4, and the element formation regions are insulated and isolated from each other. In the element formation region, for example, a MOSFET is formed as an electric element. The MOSFET includes a channel region 3a in which ions for determining a threshold value of a transistor formed in the silicon single crystal thin film 3 are implanted at a low concentration, a gate 5 formed on the channel region 3a via a gate insulating film 4, and a gate. 5 is constituted by a source region 3b and a drain region 3c respectively formed on both sides. The MOSFET gate 5 has an LDD structure in which sidewall spacers 6 are formed, and a region having a low impurity concentration is provided in the channel 3 to alleviate the electric field and reduce the generation of hot carriers. Interlayer insulating film 9 is formed on gate 5, source region 3b, and drain region 3c. In the contact holes 10 and 10 opened in the interlayer insulating film 9 on the source region 3b and the drain region 3c, a metal, for example, aluminum is buried and becomes the source and drain terminals 11 respectively.
22 is an impurity in the source / drain region for etching prevention.
[0015]
FIG. 1B shows the impurity concentration distribution of the source / drain regions. As shown in the figure, the impurity concentration is the channel ion concentration below the gate 5, the low concentration n ⁻ (or p ⁻ ) below the side wall spacer, and the high concentration n ⁺ (or p ⁺ ) in the source / drain regions. In the vicinity of the surface (upper surface) of the source / drain region, the concentration profile is set so as to have a higher concentration n ⁺⁺ (or p ⁺⁺ ). An impurity concentration peak is set near the surface (upper surface) of the source / drain region.
[0016]
In the high concentration n ⁺ (or p ⁺ ) region, ions are deeply implanted into the source / drain regions. In the case of an n-channel MOSFET, for example, phosphorus is implanted at an acceleration voltage of 40 keV and a dose of 2 × 10 ¹⁵ / cm ² so as to be concentrated at the center of the film thickness of the silicon single crystal thin film 3. In the case of a p-channel MOSFET, for example, boron is implanted at an acceleration voltage of 20 keV and a dose amount of 2 × 10 ¹⁵ / cm ² .
[0017]
Also, in the region of high concentration n ⁺⁺ (or p ⁺⁺ ), in the case of an n-channel MOSFET, for example, arsenic is concentrated on the upper surface of the silicon single crystal thin film 3 at an acceleration voltage of 20 keV and a dose of 1 × 10 ¹⁶ / cm ^2. Inject. In the case of a p-channel MOSFET, for example, indium is implanted at an acceleration voltage of 30 keV and a dose of 1 × 10 ¹⁶ / cm ² .
[0018]
Etching in the vicinity of the surface by implanting impurities at a high concentration (n ⁺⁺ or p ⁺⁺ ) near the surface of the source / drain region and using an impurity having an atomic weight larger than that of the source / drain region. The rate is set low. As a result, the erosion of the thin film 3 is reduced as compared with the conventional case (see FIG. 4).
[0019]
Next, the manufacturing process of the semiconductor device described above will be described with reference to FIGS. For convenience of explanation, FIGS. 2D, 2F, and 3B are enlarged in the vertical direction.
[0020]
First, as shown in FIG. 2A, a silicon single crystal thin film 3 is formed on a silicon substrate 1 via a buried insulating film 2 to form an SOI substrate. As described above, for manufacturing an SOI substrate, an oxygen ion implantation method or a silicon single crystal thin film bonding method to a silicon substrate can be used.
[0021]
A field oxide film is formed on this SOI substrate by a LOCOS (Local Oxidation of Silicon) method to form an element isolation region as shown in FIG. That is, a pad oxide film (not shown) is thinly formed on the surface of the silicon single crystal thin film 3 by thermal oxidation, and a silicon nitride film (not shown) is formed thereon, for example, by a CVD method. The silicon nitride film is patterned corresponding to the element formation region / element isolation region, leaving the silicon nitride film on the element formation region. Using this silicon nitride film as a mask, the silicon single crystal thin film 3 is wet O ₂ oxidized to form a field oxide film 4.
[0022]
Next, the silicon nitride film and the pad oxide film used as the mask are removed, and a gate oxide film 4 is formed by thermal oxidation. Impurity ions such as boron are implanted into the p well portion and phosphorus is implanted into the n well portion as channel ions from the gate oxide film 4. Next, polysilicon 5 to be a gate electrode / wiring is deposited on the gate oxide film 4 by the CVD method, and the polysilicon film 5 is formed into a pattern corresponding to the gate electrode / wiring by using lithography and etching.
[0023]
Next, if necessary, the gate electrode portion 5 has an LDD (Lightly Doped Drain) structure. In the LDD structure, ion implantation is performed using the gate 5 as a mask to form the low-concentration impurity diffusion layer n ⁻ (or p ⁻ ) (see FIG. 1B). For example, in the case of a p-MOSFET, phosphorus is ion-implanted into the p-type silicon single crystal thin film 3 at a dose of 1 × 10 ¹³ / cm ² to form an n ⁻ layer. In the case of an n-MOSFET, boron is ion-implanted with a dose of 1 × 10 ¹³ / cm ² into the n-type silicon single crystal thin film 3 to form a p ⁻ layer. Thereafter, a silicon oxide film is deposited on the entire surface by a CVD method, and when this oxide film is uniformly etched by directional etching, a structure in which the side wall spacer 6 remains in the gate 5 is obtained as shown in FIG. It is done.
[0024]
Next, ion implantation is performed using the gate 5 as a mask. In this ion implantation, the implantation conditions are adjusted so that the implanted impurity ions 21 are concentrated at substantially the center of the thickness of the silicon single crystal thin film 3. For example, for the p-type silicon single crystal thin film 3, boron is performed at a dose of 2 × 10 ¹⁵ / cm ² and an implantation voltage of 20 KeV. Further, for the n-type silicon single crystal thin film 3, phosphorus is applied at a dose of 2 × 10 ¹⁵ / cm ² and an implantation voltage of 40 KeV.
[0025]
Next, as shown in FIG. 2E, for example, heat treatment is performed at 1000 ° C. for about 20 seconds to activate the implanted ions.
[0026]
Next, as shown in FIG. 2F, impurity ions 22 are implanted at a shallower position near the surface of the silicon single crystal layer 3 at a concentration higher than the impurity concentration of the source / drain regions. This ion implantation suppresses the etching for forming the contact hole from cutting the source / drain regions. For example, for the p-type silicon single crystal thin film 3, indium is dosed at a dose of 1 × 10 ¹⁶ / cm ² and an implantation voltage of 30 KeV. For the n-type silicon single crystal thin film 3, arsenic is applied at a dose of 1 × 10 ¹⁶ / cm ² and an implantation voltage of 20 KeV. The activation of the impurities is performed by heat treatment at 1000 ° C. or lower, laser annealing, or a combination of both. Impurity activation by laser annealing can be performed in a non-equilibrium state within the laser irradiation range, which is convenient for forming high-concentration impurities on the extreme surfaces of the silicon single crystal layer 3.
[0027]
Thereafter, as shown in FIG. 3A, silicon oxide is deposited on the entire surface by a CVD method to form an interlayer insulating film 9. A resist (not shown) is applied on the interlayer insulating film 9, and the pattern of the contact hole 10 is exposed and developed to form a mask. The interlayer insulating film 9 is opened by performing directional etching, for example, RIE, using the mask in which the contact hole portion is opened. Etching is terminated when the oxide film 11 is opened, but the source / drain regions 3b and 3c of the silicon single crystal thin film 3 immediately below the contact hole 10 are subjected to some etching. However, the silicon single crystal thin film 3 has an impurity diffused at a high concentration on the upper side of the film thickness, and an impurity having an atomic weight larger than that of the impurity implanted into the source / drain regions is used. The etching rate on the upper part of the silicon single crystal thin film 3 is low, and the erosion to the source / drain regions is suppressed (FIG. 3B).
[0028]
After opening the contact hole, a conductive film, for example, aluminum is deposited on the entire surface as a wiring film. A resist is applied to the wiring film, and a wiring / electrode pattern is exposed and developed to form a mask. Using this mask, directional etching, for example, RIE is performed to form wirings and electrodes. Thus, as shown in FIG. 3C, an SOI substrate MOSFET in which over-etching is prevented is formed. Thereafter, the semiconductor device is completed through conventional processes such as formation of a passivation film.
[0029]
As described above, the impurity implantation conditions and the thermal diffusion conditions have been optimized so that the impurities in the source / drain regions of the conventional MOSFET having the SOI structure are uniform. Impurity concentration is higher than that of the source / drain region, and the atomic weight is higher, and the etching rate of the part is reduced, so over-etching of the thin film semiconductor layer in the source / drain region is avoided as much as possible. It becomes possible.
[0030]
According to the configuration of the present embodiment, a complicated structure for preventing over-etching associated with the opening of the contact hole in the source / drain region is unnecessary. An additional process for preventing over-etching can be minimized. In addition, it is possible to reduce the parasitic resistance.
[0031]
In the embodiment, the LDD structure is used, but the present invention is not limited to this. Further, the present invention can be applied to prevent over-etching of a semiconductor thin film substrate even in etching other than contact hole formation. The present invention can be applied to portions other than the source / drain regions in order to suppress erosion.
[0032]
【The invention's effect】
As described above, the semiconductor device of the present invention makes it difficult for the semiconductor thin film substrate to be over-etched, so that a required film thickness of the source / drain regions is ensured and an increase in parasitic resistance can be suppressed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram showing a configuration example of a semiconductor device of the present invention.
FIG. 2 is an explanatory view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 3 is an explanatory view illustrating a manufacturing process of a semiconductor device of the present invention.
FIG. 4 is an explanatory diagram for explaining a problem (over-etching) of a conventional semiconductor device.
[Explanation of symbols]
1 Silicon substrate (semiconductor substrate)
2 Buried insulating film (oxide film)
3 Silicon single crystal thin film 4 Gate insulating film 5 Gate 6 Side wall spacer 7 Resist 21 Impurity for suppressing etching (high concentration, large atomic weight)
22 Impurities in source / drain regions

Claims (2)

An element isolation step for forming an element isolation region for insulatingly isolating an element region in which a transistor is to be formed in a semiconductor thin film formed through an insulating film embedded in a semiconductor substrate;
Forming a gate through a gate insulating film on the semiconductor thin film in the element region;
A first impurity implantation step of implanting impurities into the semiconductor thin film using the gate as a mask to form source / drain regions;
A second impurity implantation step for implanting impurities in the vicinity of the surface of the source / drain region;
An interlayer insulating film forming step of forming an interlayer insulating film on the semiconductor thin film in the element region;
A contact hole forming step of forming a contact hole in the interlayer insulating film covering the source / drain region,
In the first impurity implantation step, ion implantation conditions are set so that a first peak of the impurity concentration distribution is formed at a substantially central portion of the film thickness of the semiconductor thin film,
In the second impurity implantation step, ion implantation conditions are set so that a second peak of the impurity concentration distribution is formed near the surface of the semiconductor thin film,
The method of manufacturing a semiconductor device , wherein the second peak is higher than the first peak, and the impurity in the second impurity implantation step has a larger atomic weight than the impurity in the first impurity implantation step. . 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the impurity implanted in the second impurity implantation step is activated by heat treatment and / or laser annealing.

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