KR100665829B1 - Gate structure of semiconductor devices - Google Patents
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- KR100665829B1 KR100665829B1 KR1020000029188A KR20000029188A KR100665829B1 KR 100665829 B1 KR100665829 B1 KR 100665829B1 KR 1020000029188 A KR1020000029188 A KR 1020000029188A KR 20000029188 A KR20000029188 A KR 20000029188A KR 100665829 B1 KR100665829 B1 KR 100665829B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 23
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 abstract description 16
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BYFGZMCJNACEKR-UHFFFAOYSA-N aluminium(i) oxide Chemical group [Al]O[Al] BYFGZMCJNACEKR-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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Abstract
본 발명은 MOS 트랜지스터를 갖는 반도체장치 및 그 제조방법에 관한 것으로서, 트랜지스터의 신호(ON/OFF)를 빠르게 하고 신뢰성을 향상시키고, 제조과정에서 게이트의 패턴 불량을 방지하는 게이트를 제공하는 것을 목적으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor and a method of manufacturing the same. The object of the present invention is to provide a gate for speeding up a signal (ON / OFF) of a transistor, improving reliability, and preventing a pattern defect of a gate during a manufacturing process. do.
본 발명의 반도체장치의 트랜지스터는 엑티브층을 갖는 실리콘기판(11) 고농도의 불순물 이온 주입에 의하여 구성되는 소스전극(12) 및 드레인전극(13)이 형성된다. 특히, 상기 엑티브층 위에는 Al2O3막(15)과 SiGe막(16) 및 다결정 실리콘(17)이 적층되어 게이트(20)를 구성한다.In the transistor of the semiconductor device of the present invention, a source electrode 12 and a drain electrode 13 constituted by implanting a high concentration of impurity ions into a silicon substrate 11 having an active layer are formed. In particular, an Al 2 O 3 film 15, a SiGe film 16, and polycrystalline silicon 17 are stacked on the active layer to form the gate 20.
Description
도 1은 종래 MOS 트랜지스터의 한 예의 게이트 구조를 설명하기 위한 단면도이고,1 is a cross-sectional view for explaining a gate structure of an example of a conventional MOS transistor,
도 2는 종래 MOS 트랜지스터의 다른 예의 게이트 구조를 설명하기 위한 단면도이고,2 is a cross-sectional view illustrating a gate structure of another example of a conventional MOS transistor;
도 3, 도 4는 본 발명의 MOS 트랜지스터의 게이트 구조를 설명하기 위한 각각의 단면도이고,3 and 4 are respective cross-sectional views for explaining the gate structure of the MOS transistor of the present invention.
도 5는 본 발명의 MOS 트랜지스터의 게이트 구조를 설명하기 위한 플로우차트이다.
5 is a flowchart for explaining the gate structure of the MOS transistor of the present invention.
*도면의 주요부분에 대한 부호의 설명* * Explanation of symbols for main parts of drawings *
1, 11 - 실리콘기판 2, 12 - 소스전극1, 11-
3, 13 - 드레인전극 20 - 게이트
3, 13-drain electrode 20-gate
본 발명은 MOS(Metal Oxide Semiconductor) 트랜지스터 구조를 갖는 반도체장치 및 그 제조방법에 관한 것으로서, 특히, 트랜지스터의 신뢰성을 향상시킴과 아울러 저소비전력으로 신호지연을 방지하는 게이트 구조를 제공하는 것에 관련된 것이다.BACKGROUND OF THE
종래의 트랜지스터는 기판의 불순물 농도를 저하시키면 트랜지스터의 문턱전압도 함께 저하하기 때문에 트랜지스터가 충분히 OFF(오프)되지 않는 문제점이 발생한다. 이와 같은 문제점을 해결하기 위하여 종래의 트랜지스터의 게이트 즉, 게이트전극을 n형 다결정실리콘에서 p형 다결정실리콘으로 하면 OFF 특성은 개선되지만 반대로 문턱전압이 과도하게 상승하여 ON(온)이 되지않는 문제점이 발생한다.In the conventional transistor, when the impurity concentration of the substrate is lowered, the threshold voltage of the transistor is also lowered, which causes a problem that the transistor is not sufficiently turned off. In order to solve such a problem, when the gate of the conventional transistor, that is, the gate electrode is changed from n-type polycrystalline silicon to p-type polysilicon, the OFF characteristic is improved, but the problem that the threshold voltage is excessively increased and does not become ON (on) Occurs.
상기와 같은 문제점을 개선하기 위한 기술로써 도 1과 같이 게이트전극을 게이트절연막(5) 위에 다결정 실리콘(Poly Si)과 다결정 실리콘게르마늄(Poly SiGe)을 적층하여 구성한 기술이 공지되어 있다.As a technique for improving the above problems, a technique in which a gate electrode is formed by stacking polycrystalline silicon (Poly Si) and polycrystalline silicon germanium (Poly SiGe) on the
상기 도 1의 종래 트랜지스터의 구조는 실리콘기판(1) 상에 소정 두께의 SiO2막을 개재하여 2층 구조의 게이트전극(6)(7)을 구성한다.The structure of the conventional transistor of FIG. 1 constitutes a two-layered gate electrode 6 (7) via a SiO 2 film having a predetermined thickness on a
상기 게이트전극(6)(7)은 게이트절연막(5) 위에 적층된 다결정 실리콘막과 그 위에 다결정 실리콘게르마늄막이 적층되어 구성된다.
The
소스전극(2)과 드레인전극(3)은 통상의 MOS트랜지스터와 같이 게이트전극의 양측의 실리콘기판(1)의 표면 영역에 각각 배치되고, 도시되지 않은 금속막에 의하여 각 전극이 외부로 인출되어 있다.The
상기 종래의 MOS트랜지스터의 구조 외에 도 2와 같이 게이트를 게이트절연막(5)을 SiO2로 구성하고 그 위에 게이트전극(6)을 다결정 실리콘으로 구성하는 구조가 개시되어 있다.In addition to the structure of the conventional MOS transistor, a structure is disclosed in which a gate is formed of SiO 2 and a
상기와 같이 구성되는 종래의 게이트 구조는 게이트절연막을 SiO2로 사용하므로 트랜지스터의 신호지연을 방지하기 위하여 그 두께를 15Å정도 까지 얇게 할 경우 게이트의 에칭 마진의 확보가 어려워 게이트의 패턴시 다결정 실리콘(6)이 오버에치되어 트랜치(Trench)가 형성되거나 찌거기가 생겨 트랜지스터의 신뢰성이 떨어지는 문제점이 발생한다.In the conventional gate structure configured as described above, since the gate insulating film is used as SiO 2 , it is difficult to secure the etching margin of the gate when the thickness thereof is reduced to about 15 μs in order to prevent signal delay of the transistor. 6) is overetched, so trenches are formed or residues are generated, which causes the transistor to be unreliable.
또한, 게이트전극(6)을 다결정 실리콘(6)로 구성하는 경우는 폴리 디플랙션(Poly Depletion) 때문에 트랜지스터의 신호지연(스피드 지연)이 발생한다.
In addition, when the
본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로써, 게이트의 구조를 알루미늄산화막(Al2O3막)과, 실리콘게르마늄막(SiGe막)과 다결정 실리콘막(Poly Si막)의 적층구조로 형성한다. The present invention has been made to solve the above problems, the gate structure of the aluminum oxide film (Al 2 O 3 film), the silicon germanium film (SiGe film) and the laminated structure of a polycrystalline silicon film (Poly Si film) To form.
상기 Al2O3막은 유전율이 10으로 SiO2의 2.6배에 해당하므로 SiO2 의 게이트절연막과 비교하여 두께를 크게하여 다결정 실리콘의 에칭 마진을 충분히 확보한다.Since the Al 2 O 3 film has a dielectric constant of 10 and corresponds to 2.6 times SiO 2 , the Al 2 O 3 film has a larger thickness than that of the SiO 2 gate insulating film, thereby sufficiently securing the etching margin of the polycrystalline silicon.
또, Al2O3의 막 두께를 크게하여 다결정 실리콘의 드라이에칭 선택비를 증가시켜 다결정 실리콘의 에칭패턴의 컨트롤을 용이하게 하고 스텝커버리지(Step Coverage) 특성을 개선한다.In addition, the film thickness of Al 2 O 3 is increased to increase the dry etching selectivity of the polycrystalline silicon, thereby facilitating control of the etching pattern of the polycrystalline silicon, and improving the step coverage characteristics.
또, 상기 게이트를 구성하는 SiGe막은 pMOS 폴리 디플랙션일 경우 게르마늄(Ge) 몰 프랙션(mole fraction)이 증가함에 따라 트랜지스터의 신호가 빨라진다.In the SiGe film constituting the gate, the transistor signal increases as the germanium (Ge) mole fraction increases in the pMOS poly deflection.
따라서, 본 발명의 목적은 트랜지스터의 신호(ON/OFF)를 빠르게 하고 신뢰성을 향상시키는 것을 목적으로 한다.Accordingly, an object of the present invention is to speed up the signal (ON / OFF) of a transistor and to improve reliability.
본 발명의 또 다른 목적은 트랜지스터의 게이트 에칭 불량을 방지하여 수율을 향상하고 품질을 개선하는데 있다.
Still another object of the present invention is to prevent a poor gate etching of the transistor to improve the yield and improve the quality.
상기와 같은 특징을 갖는 본 발명은 반도체장치의 게이트 구조에 있어서, 상기 게이트는 적어도 Al2O3막과 SiGe막의 적층으로 이루어진는 것을 특징으로 한다. The present invention having the above characteristics is characterized in that in the gate structure of a semiconductor device, the gate is formed of a stack of at least an Al 2 O 3 film and a SiGe film.
상기 Al2O3막은 10Å∼30Å의 두께로 형성되고, 상기 SiGe막 위에 추가로 폴리실리콘이 적층되어 형성된다.The Al 2 O 3 film is formed to a thickness of 10 kPa to 30 kPa, and is further formed by stacking polysilicon on the SiGe film.
이하, 본 발명의 반도체장치의 게이트 구조 및 작용에 대하여 도 3 내지 도 5를 참고하여 상세히 설명한다.Hereinafter, the gate structure and operation of the semiconductor device of the present invention will be described in detail with reference to FIGS. 3 to 5.
p형 실리콘기판의 표면에 열산화막을 형성한 후 통상의 포토리소그래피공정을 통하여 pMOS 트랜지스터 영역의 열산화막을 선택적으로 박리하고 pMOS 트랜지스터 영역에 n형 불순물을 이온 주입한다. 그 후, 레지스트를 박리하고 소정의 온도에서 열확산을 행한다. After the thermal oxide film is formed on the surface of the p-type silicon substrate, the thermal oxide film in the pMOS transistor region is selectively peeled off through the usual photolithography process, and n-type impurities are implanted into the pMOS transistor region. Thereafter, the resist is peeled off and thermal diffusion is performed at a predetermined temperature.
이어서, 실리콘기판의 표면의 열산화막을 모두 박리하고 다시 소정 두께의 열산화막을 형성한 후, 다결정 실리콘막과 질화막을 적층한다. 그리고, nMOS, pMOS 트랜지스터의 활성영역 등을 포토리소그래피공정에 의하여 레지스트로 덮고, 프라즈마 에칭으로 질화막을 에칭한다. 상기 에칭은 다결정 실리콘막을 스토퍼로 하여 행해진다.Subsequently, all the thermal oxide films on the surface of the silicon substrate are peeled off, and a thermal oxide film having a predetermined thickness is again formed, and then the polycrystalline silicon film and the nitride film are laminated. The nMOS and pMOS transistors are then covered with a resist by a photolithography process, and the nitride film is etched by plasma etching. The etching is performed using the polycrystalline silicon film as a stopper.
이어서, 포토리소그래피 공정에 의하여 pMOS 트랜지스터 영역을 레지스트로 덮고 상기 레지스트와 실리콘 질화막을 마스크로 하여 nMOS 트랜지스터 영역에 p형 불순물의 채널스토퍼이온 주입을 행한다.Subsequently, the photolithography step covers the pMOS transistor region with a resist and implants p-type impurity channel stopper ions into the nMOS transistor region using the resist and the silicon nitride film as a mask.
이어서, 포토리소그래피 공정에 의하여 nMOS 트랜지스터 영역을 레지스트로 덮고 상기 레지스트와 실리콘 질화막을 마스크로 하여 pMOS 트랜지스터 영역에 n형 불순물의 채널스토퍼이온 주입을 행한다.Subsequently, a n-type impurity channel stopper ion is implanted into the pMOS transistor region by covering the nMOS transistor region with a resist by a photolithography process and using the resist and the silicon nitride film as a mask.
이어서, 열산화를 실시하고 nMOS,pMOS 트랜지스터의 각각의 활성영역에 필요한 불순물을 이온 주입하여 p또는 n층을 각각 형성한다.Subsequently, thermal oxidation is performed and impurities necessary for each active region of the nMOS and pMOS transistors are ion implanted to form a p or n layer, respectively.
이어서, 게이트절연막으로 Al2O3막을 10∼30Å의 두께로 형성하고, 그 Al2O 3 막 위에 SiGe막과 절연막을 적층한다.Subsequently, an Al 2 O 3 film is formed to have a thickness of 10 to 30 GPa as the gate insulating film, and a SiGe film and an insulating film are laminated on the Al 2 O 3 film.
이어서, 절연막 및 SiGe막을 에칭하여 게이트전극의 제1층 즉, SiGe막을 형성한다.Subsequently, the insulating film and the SiGe film are etched to form a first layer of the gate electrode, that is, a SiGe film.
상기 SiGe막의 에칭은 Al2O3막을 에치스토퍼로 하여 행해지고 게이트전극 이외의 영역에서는 Al2O3막 및 필드 절연막의 표면이 노출된다.The etching of the SiGe film is Al2O 3 is performed to etch stopper film as a gate electrode in a region other than the surface of the Al 2 O 3 film and the field insulating film is exposed.
이어서, SiGe막 등을 마스크로 하여 nMOS 트랜지스터 영역에 저농도 n이온을 을 주입한다.Subsequently, low concentration n ions are implanted into the nMOS transistor region using a SiGe film or the like as a mask.
상기 이온 주입에 의하여 불순물이 실리콘기판(11) 내의 채널 영역에 도달하는 것을 방지하기 위해 SiGe막 만으로는 두께가 얇기 때문에 절연막을 별도로 적층하여 형성하는 것이 바람직하다.In order to prevent impurities from reaching the channel region in the
이어서, 상기 별도로 적층된 절연막을 제거한 후 표면이 노출된 SiGe막 위에 다결정 실리콘막을 적층하여 형성한다.Subsequently, the separately stacked insulating film is removed, and then a polycrystalline silicon film is laminated on the exposed SiGe film.
상기 다결정 실리콘막을 마스크로 하여 소스전극 및 드레인전극 영역에 불순물 이온을 주입하고 열확산하여 고농도의 n 또는 p 확산층을 형성한다.Using the polycrystalline silicon film as a mask, impurity ions are implanted into the source and drain electrode regions and thermally diffused to form a high concentration n or p diffusion layer.
상기와 같은 과정에 의하여 제조되는 MOS 트랜지스터는 도 3과 같이 채널층(활성층)을 갖는 실리콘기판(11), 고농도의 불순물 이온 주입에 의하여 구성되는 소스전극(12) 및 드레인전극(13)이 형성된다. 상기 채널층 위에는 Al2O3막(15)과 SiGe막(16) 및 다결정 실리콘(17)이 적층되어 게이트(20)를 구성한다.In the MOS transistor manufactured by the above process, as shown in FIG. 3, the
즉, 실리콘 기판에 활성층을 형성하는 단계, 상기 활설층 위에 Al2O3막을 형 성하는 단계, Al2O3막 위에 SiGe막을 형성하는 단계, SiGe막 위에 다결정 실리콘막을 형성하는 단계를 거쳐 MOS 트랜지스터가 제조된다.That is, the MOS transistor is formed by forming an active layer on a silicon substrate, forming an Al 2 O 3 film on the active layer, forming a SiGe film on an Al 2 O 3 film, and forming a polycrystalline silicon film on the SiGe film. Is prepared.
본 발명은 상기와 같이 게이트(20)를 Al2O3막,SiGe막,다결정 실리콘막의 적층 구조로 형성함으로써, 붕소(B)를 포함하는 에천트 등의 침투에 의한 게이트 패턴의 트랜치 또는 패턴 주위에 패턴막의 찌꺼기가 남는 문제점을 해소하고, 트랜지스터의 ON/OFF 특성을 개선한다.
According to the present invention, the gate 20 is formed in a stacked structure of an Al 2 O 3 film, a SiGe film, and a polycrystalline silicon film as described above, so that the trench or the periphery of the gate pattern due to the penetration of an etchant containing boron (B). This eliminates the problem that the residue of the pattern film remains, and improves the ON / OFF characteristics of the transistor.
본 발명은 실리콘기판 위에 활성층을 형성하고, 그 활성층 위에 게이트로서 Al2O3막, SiGe막, 다결정 실리콘막을 연속 적층하여 구성함으로써, 트랜지스터의 신호(ON/OFF)를 빠르게 하고 신뢰성을 향상시키는 효과를 얻을 수 있다.According to the present invention, an active layer is formed on a silicon substrate, and an Al 2 O 3 film, a SiGe film, and a polycrystalline silicon film are successively stacked as a gate on the active layer, thereby speeding up the signal (ON / OFF) of the transistor and improving reliability. Can be obtained.
또, 트랜지스터의 게이트 형성에 있어서 SiO2에 비하여 Al2O3막의 두께를 크게 할 수 있으므로 게이트 패턴의 에칭 불량을 방지하여 수율을 향상하고 품질을 개선하는 효과를 얻을 수 있다.
In addition, since the thickness of the Al 2 O 3 film can be made larger than that of SiO 2 in the gate formation of the transistor, it is possible to prevent the etching defect of the gate pattern, thereby improving the yield and improving the quality.
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| KR20010063265A (en) * | 1999-12-22 | 2001-07-09 | 박종섭 | Method of manufacturing semiconductor device |
| KR20010106716A (en) * | 2000-05-23 | 2001-12-07 | 박종섭 | Method for fabrication semiconductor device |
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| KR20010063265A (en) * | 1999-12-22 | 2001-07-09 | 박종섭 | Method of manufacturing semiconductor device |
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