JP3166911B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device such as a field effect transistor.

[0002]

2. Description of the Related Art In order to improve the performance of a transistor, miniaturization is required. As a result, a gate oxide film thickness is becoming thinner with a decrease in power supply voltage.

Due to the reduction in the thickness of the oxide film, the gate electrode using conventional polysilicon cannot be sufficiently depleted of impurities at the gate / oxide film interface.
This is a major cause of hindering performance improvement by miniaturization. This means that the gate oxide film thickness of a MOS transistor at the 0.1 micron level is about 1.5 nm. For such a thin oxide film, while suppressing the boron penetration phenomenon which is a problem on the pMOS side, In addition, in order to suppress the gate depletion by sufficiently doping impurities into the gate polysilicon, the problem of narrowing the process margin, etc. There was a limit.

On the other hand, a metal gate structure in which a gate electrode is formed of metal has no problem of gate depletion and is a promising structure for miniaturization, but is a structure in which a thin gate oxide film comes into contact with metal. Therefore, there is a restriction that a high-temperature heat treatment process cannot be applied after the gate structure is formed. Therefore, a method of forming a dummy gate, forming a source / drain, and then forming a gate again has been adopted. .

[0005]

However, the problem here is that it is difficult to form a source / drain structure corresponding to a 0.1 micron level transistor by the conventional method of forming a source / drain structure. There is a point.

This is because the current source / drain structure for a fine device is formed by a shallow junction and a pocket structure by a source / drain-extension structure, and this region is generated at the time of ion implantation for forming the source / drain. Due to point defects, the impurity forming these regions is indispensable in a transistor having a deep junction or a miniaturized transistor due to a phenomenon called accelerated diffusion when activation annealing is performed after ion implantation. The impurity in the region where the channel impurity concentration is locally increased to become a pocket structure is diffused, and the impurity concentration is reduced. As a result, the phenomenon of gate depletion can be suppressed, but the short channel characteristics of the fine device cannot be maintained. The problem had arisen. Moreover, in a device having a metal gate structure, the gate oxidation step is performed after the formation of the source / drain, so that this problem becomes more remarkable. The solution was desired. The problems associated with this miniaturization will be described below with reference to the manufacturing steps shown in FIGS.

FIG. 5A shows a device having a metal gate electrode. First, ion implantation for a source / drain-extension region and ions for a pocket structure are performed on a dummy gate electrode (40). FIG. FIG. 5B is a view showing a state after forming a sidewall (6) made of silicon nitride and then performing ion implantation for forming a source / drain region. FIG. 5C is a diagram when a heat treatment for activating the source / drain regions is performed.

[0008] Since ion implantation for forming the source / drain regions is performed at a high dose, there are many point defects (silicon atoms shifted from the lattice position due to the implanted ions) during the ion implantation. . These point defects combine with impurity atoms that have been doped in advance and cause so-called enhanced diffusion that increases the diffusion coefficient of the impurities. That is, despite the relatively low temperature heat treatment
For example, the impurities in the channel region that determines the threshold voltage and the impurities that form the pocket structure introduced earlier are significantly diffused (region (53) in FIG. 5C). In particular, if the distribution of the impurities forming the pocket structure close to the source / drain regions changes due to the enhanced diffusion, it will greatly affect the short channel characteristics. Further, since the enhanced diffusion involving the point defect is sensitively affected by a change in the manufacturing process, it also has a disadvantage that the variation in the electrical characteristics of the transistor itself increases. Even if a gate with a very low depletion suitable for a micro device is brought into consideration, the performance of the device itself will not improve unless the design of the source / drain regions is suitable for the micro device. Further, in a transistor having such a metal gate structure, the dummy metal gate is removed after the formation of the source / drain regions, and then the gate oxide film is formed again.
The impurity distribution forming the pocket structure is further diffused.

As can be seen from the above, a process which is not affected by the redistribution of impurities due to enhanced diffusion and which is suitable for a metal gate device which is a prominent device as a fine device, and particularly a shallow (shallow) process which is sufficiently compatible with a fine device ) A process for realizing a pocket was desired.

A semiconductor device in which a source / drain region is formed using a dummy gate electrode and then the dummy gate electrode is removed to form a gate electrode is disclosed in, for example, Japanese Patent Application Laid-Open Nos. -12446
JP, JP-A-6-84952, JP-A-6-17
No. 7161 discloses this.

[0011]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a semiconductor device, using the dummy gate electrode, lightly doped source of
.Drain-extension regions and high-concentration sources
- a drain region after forming the semiconductor substrate, and removing the dummy gate electrode, in the method of manufacturing a semiconductor device for forming a gate electrode, after removing the dummy gate electrode, the ion implantation for forming a pocket structure area The semiconductor substrate with respect to the groove where the dummy gate electrode was located.
From the pocket structure area
Source / drain-channel side of extension region
The bottom and sides of the channel, and the channel of the source / drain region.
It is characterized in that it is provided in contact with the side on the side of the console . The present invention relates to a method of forming a semiconductor device such as a metal gate transistor in which a gate electrode is formed after forming a source / drain using a dummy gate electrode. Semiconductor base
By performing ion implantation at a fixed angle from the plate, it is possible to suppress the accelerated diffusion of impurities forming the ion-implanted pocket region, which has occurred at the time of source / drain activation, which has conventionally been a problem. And a shallow (shallow) and local impurity profile suitable for a fine device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

One embodiment of a method of manufacturing a semiconductor device according to the present invention is shown in FIGS. Here, the n-type MO
Although the method of manufacturing a semiconductor device according to the present invention will be described using an S transistor as an example, the present invention can be similarly applied to a p-type MOS transistor.

As shown in FIG. 1A, a gate oxide is formed on a silicon substrate (1) to form a dummy oxide film (30), a dummy gate electrode (40) is further formed, and a dummy gate structure is formed. To form The dummy gate oxide film (30) and the dummy gate electrode (40) are
After the drain is formed, it is removed.

In the embodiment shown here, a p-type MOS transistor is formed on the silicon substrate (1).
A type impurity, for example, boron is doped by an ion implantation method, and the concentration is set so as to have a separation characteristic and a threshold voltage necessary for transistor operation. For a 0.1 micron level transistor, the gate oxide film thickness should be 1.
In the case of 5 nm, for example, boron is set to 1 at 100 keV.
A dose of about 6 × 10 ¹² / cm ² is implanted at × 10 ¹³ / cm ² and 30 keV. The channel region (11) is formed by such impurity doping.

The dummy oxide film (30) is, for example, a silicon oxide film having a thickness of 1.5 nm or a silicon oxide film containing nitrogen by a steep oxidation treatment by a lamp annealing device or the like.

The dummy gate electrode (40) is obtained by depositing a 200-nm-thick polysilicon film on the material by using an excimer laser lithography or electron beam lithography technique, and further, using a high-selectivity etching technique with an oxide film. Can be formed.

Thereafter, as shown in FIG.
A region serving as a source / drain-extension region (51) in the OS transistor is formed by arsenic at 7 keV and about 4 × 10 ¹⁴ / cm ² by an ion implantation method. At this time, the junction depth of the drain-extension region is about 30 nm.

The important point here is that the short channel effect does not usually occur even if the transistor is miniaturized.
A pocket structure made of a substrate and a conductive type impurity, such as an n-type transistor, for example, boron, which is a p-type impurity, is also formed by ion implantation so as to cover the source / drain-extension region (51). Although it is formed, the present invention is not performed at this time.

Thereafter, a silicon nitride film is deposited to a thickness of about 80 nm to form a side wall. This silicon nitride is formed by, for example, a CVD (chemical vapor deposition) method. The substrate temperature in this deposition is about 700 ° C., and the reaction is performed in an atmosphere of silane (SiH ₄ ) and ammonia (NH ₃ ). Thereafter, etching is performed by an etch-back method so as to leave only the side wall of the dummy gate electrode, thereby forming a side wall (6) having a structure as shown in FIG. 1C.

Next, as shown in FIG. 2D, ion implantation for forming a source / drain region (7) of the transistor is performed. For example, in the case of an n-type MOS transistor, arsenic is used as an ion species at 50 keV and about 6 × 10 ¹⁵ / cm ^{2 in} a 0.1-micron level design.
Although not shown in the figure, in such a high dose ion implantation, in order to avoid the influence of contamination (related to the knock-on phenomenon) from the ion implantation atmosphere, C
After a silicon oxide film formed by the VD method or the like is deposited to a thickness of about 10 nm, ion implantation for forming the source / drain regions is performed.

Thereafter, as shown in FIG. 2E, a heat treatment for activating the previously implanted impurities is performed. This heat treatment is performed at 1000 ° C. for 10 seconds to 20 seconds in a nitrogen atmosphere at normal pressure. This heat treatment is performed by a device capable of performing a steep heat treatment by a lamp annealing device or the like. During this heat treatment, the source
Drain-extension region (51) and source
The drain region (7) becomes slightly deeper due to diffusion. Here, it should be noted that since the ion implantation for forming the pocket structure is not performed as described above, the impurity on the substrate locally forming the pocket structure which has been conspicuously generated during the heat treatment for activation in the past. The point is that the enhanced diffusion does not occur for the impurity in the region where the concentration is increased.

Thereafter, an insulating film (8) of silicon oxide is formed.
Is deposited to a thickness of about 300 nm as shown in FIG. This silicon oxide film is formed at 400 ° C. by a CVD method.
Deposited under moderate growth conditions. Regarding the thickness, the thickness of the dummy gate electrode (40) is 200 in this case.
Since it is nm, it is sufficient if the film thickness covers the entire substrate as shown in the figure.

Then, as shown in FIG. 3 (g), the substrate surface is subjected to a CMP method (chemical mechanical polishing).
Polishing is performed until the surface of the dummy gate (40) appears by the cal polishing method. At this time, the dummy gate (4
Since the side wall (6) made of a silicon nitride film deposited on the side wall portion of (0) is harder than the silicon oxide film (8) for this polishing, it serves as a stopper during polishing. ) Can be realized.

Thereafter, only the dummy gate (40) is etched (FIG. 3 (h)). The etching at this time may be anisotropic etching having a high selectivity to the oxide film when the dummy gate structure is formed, or wet etching using a mixed solution of hydrofluoric acid and nitric acid. .

In this state, as shown in FIG. 3 (i), ion implantation for forming a pocket structure is performed at an angle, thereby forming the source / drain formed earlier.
Impurities of the same conductivity type as the substrate are introduced into a region deeper than the extension region (51) and shallower than the source / drain region (7) (formation of the pocket region (52)). In this case, since an n-type transistor is used as an example, BF ₂ is ion-implanted so that the ion species becomes p-type. The conditions for ion implantation are the source / drain-extension region (5
Regarding the conditions for forming 1) and the source / drain region (7), BF ₂ is increased by 1 at an acceleration energy of 20 to 30 keV.
A dose amount of × 10 ¹³ to 3 × 10 ¹³ / cm ^{2 is set at} an angle of 25 ° to 4 ° from the substrate with respect to the groove where the dummy gate was located.
By performing at 0 degrees, the impurity distribution described above, that is, the shallowness is sufficient for realizing a fine device, and the ion implantation is performed on the groove of the dummy gate electrode, so that the pocket structure is sufficiently local. (See the pocket region (52) in FIG. 3 (i)).

Thereafter, the dummy gate oxide film (30) is etched. Although the silicon oxide film (8) is slightly etched by the wet etching at this time, since the dummy gate oxide film is about 1.5 nm, the reduction of the oxide film (8) itself in this etching is almost a problem. do not become.

Thereafter, the entire surface of the substrate is again oxidized to form a gate oxide film (32), and a gate electrode is formed. The gate oxidation may be an oxide film into which nitrogen is mixed. Since the thickness of the oxide film is about 1.5 nm for realizing a 0.1-micron level transistor, it is formed by a method such as the steep oxidation method described above. Here, the metal film (42) constituting the gate electrode is not directly deposited on the silicon oxide film so as not to react with the thin oxide film, but is used as a barrier metal having a thickness of, for example, about 10 nm. Titanium nitride (43) is deposited first, and then tungsten or aluminum is deposited to fill the trench itself.
Deposit about 00 nm (see FIG. 4 (j)). Generally, a titanium nitride film as a barrier metal is formed by a CVD method, and a metal film is formed by a sputtering method or a CVD method.

Thereafter, as shown in FIG.
Polishing is performed by the MP method so that the gate metal is left only inside the trench using the sidewall (6) as a stopper.
Thereafter, a contact hole for a diffusion layer such as a gate electrode, a source, and a drain is formed by a normal process, and further,
By performing the wiring step, a transistor device is formed.

Also, since it is formed by such a manufacturing method, it has a shallow pocket structure so as to sufficiently realize miniaturization.
In addition, it is possible to form a 0.1-micron level fine MOS transistor having a metal gate electrode.

In the above-described embodiment, various numerical values such as the polarity of the transistor, the thickness of the oxide film, and the ion implantation conditions are not limited to the above.

[0032]

As described above, according to the present invention,
Conventionally, the pocket structure corresponding to the micro device, which is not affected by the accelerated diffusion generated at the time of forming the source / drain diffusion layer, which has been difficult to form with the micro transistor,
This can be realized by a device having a metal gate electrode structure in which the necessity is important.

That is, in the present invention, a dummy gate structure is formed, a source / drain-extension region and a source / drain region are formed, and after removing the dummy gate electrode, ion implantation for a pocket structure is performed. After that, a buried gate electrode made of metal is formed. Therefore, the impurities forming the pocket structure are formed shallowly (shallowly) and formed in the trench where the dummy gate was formed by angle ion implantation, so that the impurities are formed sufficiently locally. By this method, a metal gate transistor having a source / drain-extension structure and a source / drain structure sufficiently suitable for miniaturization can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of an embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of an embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of an embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of an embodiment according to a method of manufacturing a semiconductor device of the present invention.

FIG. 5 is a cross-sectional view showing an example of a manufacturing process according to a conventional manufacturing method.

[Description of Signs] 1 p-type semiconductor substrate 6 sidewall 7 source / drain region 8 insulating film 11 channel region 30 dummy gate oxide film 32 gate oxide film 40 dummy gate electrode 42 gate electrode made of metal 43 barrier metal (titanium nitride) 51 source / drain-extension region 52 pocket region 53 pocket region significantly diffused by enhanced diffusion

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-189966 (JP, A) JP-A-5-152321 (JP, A) JP-A-5-121446 (JP, A) JP-A-4- 28236 (JP, A) JP-A-6-177161 (JP, A) JP-A-6-84852 (JP, A) JP-A-4-123439 (JP, A) JP-A-8-130193 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/338 H01L 21/265 604 H01L 29/812

Claims (3)

(57) [Claims] 1. A low-density source using a dummy gate electrode.
Source / drain-extension region and high-concentration source
After forming the over scan and drain regions in the semiconductor substrate, and removing the dummy gate electrode, in the method of manufacturing a semiconductor device for forming a gate electrode, after removing the dummy gate electrode, ion forming the pocket structure area The implantation is performed at a predetermined angle from the semiconductor substrate with respect to the groove where the dummy gate electrode was located.
The pocket structure region is
Lower and sides of the channel side of the extension area and in front
It is set in contact with the channel side of the source / drain region.
A method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said ion implantation is performed at an angle of 25 ° to 45 ° with respect to said groove from said semiconductor substrate. 3. The method according to claim 1, further comprising the steps of :
Source-drain-extension
A dummy region, and a sidewall is formed on the dummy gate electrode.
After the formation of the source / drain by ion implantation
Method of manufacturing semiconductor device characterized by forming region
Law.