JP3371600B2 - Method for manufacturing MIS transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a highly integrated LSI.
The present invention relates to a method for manufacturing a MIS transistor applicable to a logic circuit and an analog circuit in the inside.

[0002]

2. Description of the Related Art When manufacturing a Pch transistor having a design rule of 1 μm or less, the gate length is also 1 μm or less. In the case of such a fine structure, short channel effects such as punch through and lowering of threshold voltage become a problem. As a method of suppressing this, P ⁻ by the LDD structure
Layer formation is commonly used. This manufacturing method is shown in FIG.

First, in the step (a), a thin gate oxide film (for example, a thickness of 20 nm or less) 51 is formed on a semiconductor substrate 50 having an N-type property, and a gate length of 1 μm or less is formed thereon. A fine gate electrode 52 is formed. Further, a thin amorphous insulating film 53 such as an oxide film or a nitride film having a thickness of 0.01 to 0.03 μm is formed on the entire surface by a chemical vapor deposition method, a sputtering method or the like. After that, boron ions 54 are implanted at about 1 to 5 × 10 ¹³ / cm ² .

In the next step (b), an insulating film 55 similar to the insulating film 53 is formed on the surface of the substrate to a thickness of about 0.4 μm. Further, in order to activate the boron implanted in the step (a), heat treatment is carried out at an appropriate temperature so that the concentration on the surface of the substrate is about 1 × 10 ¹⁸ / cm ^2, which is a relatively low concentration of P.
^- forming a layer 56, 57. In the next step (c), the insulating film 55 is anisotropically etched back to form the gate electrode 53.
Side walls 58 and 59 are formed so as to be adjacent to both sides of the side wall.
At this time, the thickness d of the side wall is appropriately about 0.2 μm.

In the next step (d), BF ₂ (2
Boron fluoride ion or 60 boron ions
^{× 10 15 / cm 2 ~5 ×} 10 15 / cm 2 of about injected.
At this time, the region where the ions reach the substrate 50 is the side wall 58,
It is located outside the region where 59 is formed. And (e)
In the step of, the implanted ions 60 are activated to form high-concentration P ⁺ layers (source and drain) 62 and 63.

As described above, a Pch transistor having a fine structure is formed. In this structure, the presence of the P ⁻ layers 56 and 57 increases the effective channel length, and this P ⁻
Since the layers 56 and 57 act as a resistance component and cause a voltage drop here, the voltage applied between the channel regions 61 becomes smaller than the drain voltage, whereby punch-through can be suppressed. Therefore, the P ⁻ layers 56, 5
7 acts as a punch-through suppressing layer.

[0007]

However, when the manufacturing method as described above is used, the length a of the P ⁻ layers 56 and 57 largely depends on the side wall thickness d. The side wall thickness d has two major factors in manufacturing. One is the variation in film thickness when the insulating film 55 is formed, and the other is
One is the variation in etching rate during anisotropic etch back.

The variation in the formation of the insulating film 55 is about 10%, which is about ± 0.04 μm under the above manufacturing conditions. The variation due to anisotropic etch back is about 20%, and is ± 0.04 μm under the above manufacturing conditions.
There will be variations in the degree. Therefore, the variation of the side wall thickness d is {(0.04) ² +
(0.04) ² } ^1/2 = 0.056 μm. This is because the effective channel length is 0.056μ due to the sidewall process.
This indicates that a variation of m is generated. Currently, 10% in the LSI process where the miniaturization progresses and the gate length is about to reach a region smaller than 0.5 μm.
The above variations result. Therefore, such variations are of an unacceptable magnitude in the manufacture of microstructured transistors.

Further, the variation in the length a of the P ⁻ layers 56 and 57 also varies the effect of suppressing punch-through, which causes a problem that stable transistor characteristics cannot be obtained. The present invention has been made in view of the above problems, and an object of the present invention is to reduce the above-mentioned variations and obtain stable transistor characteristics.

[0010]

In order to achieve the above object, in the invention described in claim 1, the semiconductor substrate (1
1) via the gate insulating film (12) to the gate electrode (1
3), and an insulating film on the surface of the gate electrode on the surface of the gate electrode and the surface of the semiconductor substrate.
Is thicker than the insulating film on the surface of the semiconductor substrate.
Punch, the insulating film (14a, 14b) forming a, the ions (15) from an oblique direction with respect to the insulating film formed on the side surface (14a) of the gate electrode implanted to, in the semiconductor substrate A step of forming a through suppression layer (16a, 16b), and a step of forming a source and a drain from the vertical direction on the surface of the semiconductor substrate by using the gate electrode and the insulating film formed on the side surface of the gate electrode as a mask. implanting boron difluoride ions (18) as an ion source to activate the implanted ions by heat treatment, the drain (18a, 18b) and forming a said boron difluoride ions Before injection
In the gate electrode due to abnormal diffusion of boron during the heat treatment
Boron atoms implanted in the silicon penetrate through the gate insulating film.
It is characterized by a method of manufacturing a MIS transistor that is performed with an accelerating voltage so as not to reach the channel region .

[0011] In the invention described in claim 2, a method of manufacturing a MIS transistor according to claim 1, in the gate
The insulating film on the surface of the cathode electrode,
It is characterized in that it is set to a projected range Rp or more representing a range .

[0012] In the invention described in claim 3, also claim 1
In the method of manufacturing a MIS transistor described in 2 ,
The semiconductor substrate is a single crystal silicon substrate (11),
The gate electrode (13) is made of polycrystalline silicon, and in the step of forming the insulating film, an oxide film (14a) is simultaneously formed on each surface of the gate electrode and the single crystal silicon substrate by thermal oxidation. , 14b) are formed.

According to the invention described in claim 4 , claims 1 to
3. In the method of manufacturing a MIS transistor according to any one of 3 above, the ions for forming the punch-through suppressing layer are phosphorus ions or phosphorus-containing compound ions (15), or boron ions or boron-containing compound ions ( 20). The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0014]

[Effects of the invention] According to the invention described in claims 1 to 4, the punch-through suppression layer being performed ion implantation from an oblique direction with respect to the insulating film formed on the side surface of the gate insulating film is formed Ions for forming a source and a drain are vertically implanted using the gate electrode and the insulating film formed on the side surface of the gate electrode as a mask.

Therefore, since the punch-through suppressing layer, the source and the drain are both formed by the ions implanted with the insulating film formed on the side surface of the gate insulating film as a reference, the punch-through suppressing layer, the source and the drain are formed. It is possible to reduce the variation in the positional relationship of (1), and thus the variation in the short channel effect can also be reduced.

Further, because they form a source, a drain by implantation of boron difluoride ions, it is possible to manufacture a Pch transistor can be sufficiently suppressed short channel effect even with a small gate length. Further, according to the invention described in claim 3 , an oxide film is simultaneously formed on the respective surfaces of the gate electrode and the semiconductor substrate by thermal oxidation. In this case, since the semiconductor substrate is a single crystal silicon substrate and the gate electrode is composed of polycrystalline silicon, the oxide film on the surface of the gate electrode may be thicker than the oxide film on the surface of the single crystal silicon substrate. It is possible to form the side wall only by this thermal oxidation. Therefore, the conventionally required etch-back process shown in FIG. 5 can be eliminated, and variations due to the etch-back process can be eliminated.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view showing a first embodiment when applied to a MOS transistor in the method of manufacturing a MIS transistor according to the present invention. First, in the step (a), a gate oxide film 12 having a thickness of 20 nm or less (for example, 16 nm) is formed on an N-type single crystal silicon substrate 11, and a gate electrode 13 is formed thereon. The gate electrode 13 is made of, for example, polycrystalline silicon, is heavily N-doped with phosphorus or arsenic, and has a thickness of 300 to 350 nm.

In the next step (b), heat treatment is performed in a dry atmosphere in which only oxygen is supplied or in a wet atmosphere in which a mixed gas of oxygen and hydrogen is burned, and the substrate surface is thermally oxidized to form an oxide film. 14a and 14b are formed. This time,
The thickness of the surface oxide film 14a of the gate electrode 13 is t2,
If the thickness of the surface oxide film 14b of the silicon substrate 11 is t1, then t2> t1. For example, 1000 ° C, 90
In dry oxidation of min, the thickness of the oxide film 14a is 100 n
While the thickness of the oxide film 14b is 50 nm, the thickness is about half, which is 50 nm.

In the next step (c), phosphorus ions or compound ions containing phosphorus are obliquely ion-implanted. The incident angle is preferably about 10 to 60 degrees with respect to the normal to the substrate surface. The injection amount is 1 to 9 × 10 ¹³ / c
m ² is suitable, and the acceleration energy is 30 k
eV to 120 keV is suitable. At this time, the acceleration voltage is set so that most of the ions that reach the channel region under the gate oxide film 12 are the implanted ions that have passed through the side surface of the gate electrode 13. This is because if most of the ions that have entered from the upper surface of the gate electrode 13 reach the channel region directly below the gate electrode 13, the threshold voltage changes significantly and it becomes impossible to obtain the desired performance.

After that, appropriate heat treatment is performed to activate the implanted ions to form N-type punch-through suppressing layers 16a and 16b partially including the region directly below the gate electrode 13. The positions of the punch-through suppressing layers 16a and 16b formed in the silicon substrate 11 by using such an oblique ion implantation method are determined with reference to the oxide film surfaces 17a and 17b formed on the side surfaces of the gate electrode 13. Will be.

In the next step (d), BF ₂ ions 18
Are implanted perpendicularly to the surface of the silicon substrate 11. The acceleration voltage of the BF ₂ ion 18 at this time is 110 k.
eV or less. Then, in the step (e), heat treatment is applied to the P ⁺ layers 18a and 18b serving as the source and the drain.
To form. At this time, in the channel region 19 immediately below the gate electrode 13, the punch-through suppression layers 16a and 16b are left by the length b at the positions in contact with the P ⁺ layers 18a and 18b.

In the above embodiment, the gate electrodes 13 are formed because the insulating films 14a and 14b are formed by thermal oxidation.
An oxide film can be simultaneously formed on the upper surface and the silicon substrate 11, in which case a thick oxide film 14a is formed on the surface of the gate electrode 13 and a thin oxide film 14b is formed on the surface of the silicon substrate 11 than the gate electrode 13. Is formed. Therefore, since the thick oxide film 14a and the thin oxide film 14b can be formed at the same time, the conventional oxide film 53 shown in FIG.
And the side wall 58 can be formed in the same process. Further, since the thick oxide film 14a to be the side wall is formed by only one oxidation step, there is an effect that the conventional etch back step is unnecessary. In addition, the oxide film 14
Since b is a thin oxide film, there is no particular problem when the BF ₂ ions for forming the source and drain reach the silicon substrate 11. For example, the above-mentioned 1000 ° C,
When the heat treatment is performed for 90 minutes, the thickness of the insulating film 14b on the silicon substrate 11 becomes 50 nm. Therefore, if the acceleration voltage is 80 keV, the BF _{2 in the} silicon substrate 11 is sufficient.
Ions can reach.

Further, since the oxide film 14b having a thickness of 10 nm or more is formed on the silicon substrate 11, it is possible to obtain a boron concentration profile with little variation and good reproducibility without channeling at the time of ion implantation. it can. If a thicker insulating film is required on the gate electrode 13, the heat treatment temperature may be lowered. For example,
In the case of wet oxidation at 850 ° C, 1 is applied to the gate electrode 13.
Even if a 00 nm oxide film is formed, only 30 nm is formed on the silicon substrate 11. When considering the processing temperature, wet oxidation is usually lower than dry oxidation, and a thicker oxide film can be formed on the silicon substrate around the gate electrode. Further, in the case of dry oxidation, the processing temperature is as high as about 1000 ° C. as compared with wet oxidation, and the oxide film around the gate electrode becomes thin in the same processing time, but it has an effect of rounding the edge portion of the gate electrode.

BF ₂ ions are implanted using the gate electrode 13 and the sidewall oxide film 14a as a mask. in this case,
Ion implantation is performed with reference to the oxide film surfaces 17a and 17b on the side surfaces of the gate electrode 13. The oblique ion implantation for forming the punch-through suppressing layers 16a and 16b is also performed with the sidewall oxide film 14a as a reference. Therefore, the positional relationship between the P ⁺ layers 18a and 18b formed of BF ₂ and the punch-through suppressing layers 16a and 16b is independent of the variation in the thickness of the sidewall oxide film 14a. Therefore, the variation of the positional relationship becomes smaller than that of the conventional one, and the gate length L
Since the appearance of the short channel effect with respect to g is stable, the transistor characteristics are stable.

When the accelerating voltage for implanting BF ₂ ions for forming the P ⁺ layers 18a and 18b is made extremely high,
Due to the abnormal diffusion of boron, the boron atoms injected into the gate electrode 13 penetrate the gate oxide film 12 and reach the channel region 19, making it impossible to control the threshold voltage.
Therefore, as shown in FIG. 2, the acceleration voltage of BF ₂ is 110 k
It must be smaller than eV. FIG. 2 is a graph showing changes in the threshold voltage (Vth) with respect to the acceleration energy of BF ₂ when the film thickness of the gate oxide film 12 is 16 nm.

When the maximum accelerating voltage for BF ₂ ion implantation is 110 keV at maximum, the projected range Rp representing the range of boron ion implantation is 0.082 μm at maximum. Therefore, stable P ⁺ layer 1
In order to obtain the characteristics of 8a and 18b, the insulating film 14b on the surface of the silicon substrate 11 is not more than Rp at this time, that is, 0.0
The thickness is preferably 82 μm or less. On the other hand, in order to suppress the short channel effect, the side surface of the gate electrode 13 needs to have an insulating film having a greater thickness (for example, 0.1 μm).

On the other hand, when boron ions are used instead of BF ₂ ions, as shown in FIG.
Larger gate length Lg than in the case of ion implantation with F ₂
Therefore, the threshold voltage of the Pch transistor starts to decrease, that is, the short channel effect occurs, and stable transistor performance cannot be obtained. Therefore, it is necessary to use BF ₂ ions in order to sufficiently suppress the short channel effect even with a small gate length. Use Incidentally, as shown in FIG. 3, as BF ₂ ions and boron ions are the same implantation depth, a graph when the experiment set each of the accelerating voltages, the (a) is BF ₂ ions In the case where the boron ion is present, (b) shows the case where boron ions are used.

FIG. 4 shows a second embodiment of the present invention. The difference from the first embodiment is that, in the step (c), ion implantation is carried out by using boron or an ion 20 of a compound containing boron instead of the phosphorus ion or the compound ion 15 containing phosphorus. This allows the punch-through suppressing layers to be P ⁻ layers 20a and 20b.

In this case, similarly to the first embodiment, the P ⁺ layer 18
It is possible to reduce variations in the positional relationship between the a and 18b and the P ⁻ layers 20a and 20b, and to stabilize the transistor characteristics. Note that the punch-through suppressing layer has an electric field relaxing effect as compared with the case where the P ⁻ layer is the N ⁻ layer. The present invention is also applicable to the case where the side wall oxide films 58 and 59 formed by the conventional technique shown in FIG. 5 are used as the side wall oxide films, and oblique ion implantation and vertical ion implantation are performed after the formation of the side wall oxide films. You can However, the above-described embodiment is more effective than that in the following points.

That is, in the above embodiment, the sidewall oxide film 1
Since 4a is formed in one step, the film thickness variation is reduced as compared with the film thickness variation of the sidewall oxide film formed in the two steps of film formation and etch back as shown in FIG. can do. Therefore, as compared with the case where the ion implantation is performed using the sidewall oxide film shown in FIG. 5, the influence of the film thickness variation can be reduced, so that the variation of the effective channel length defined by the punch-through suppressing layer is suppressed. In addition, it is possible to suppress variations in the amount of overlap between the P ⁺ layers 18a and 18b and the gate electrode, and it is possible to further stabilize the transistor characteristics.

Although the method of manufacturing the Pch transistor has been described in the above embodiment, the Nch transistor can be manufactured in the same manner by implanting an appropriate ion species.

[Brief description of drawings]

FIG. 1 is a process drawing showing a first embodiment of the present invention.

FIG. 2 is a graph showing change characteristics of threshold voltage with respect to acceleration energy of BF ₂ ions.

FIG. 3 is a graph showing change characteristics of the threshold voltage with respect to the gate length Lg when BF ₂ ions and boron ions are used.

FIG. 4 is a process drawing showing a second embodiment of the present invention.

FIG. 5 is a process chart showing a conventional manufacturing process.

[Explanation of symbols]

11 ... Single crystal silicon substrate, 12 ... Gate insulating film, 13
... Gate electrodes, 14a, 14b ... Oxide film, 15 ... Phosphorus ions or compound ions containing phosphorus, 16a, 16b ...
Punch-through suppressing layer, 18 ... BF ₂ ions.

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-302433 (JP, A) JP-A-3-203243 (JP, A) JP-A-6-104277 (JP, A) JP-A-3- 209836 (JP, A) JP-A-56-161673 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (4)

(57) [Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a step of forming a gate electrode on a surface of the gate electrode and a surface of the semiconductor substrate .
The insulating film on the surface of the gate electrode is more
A step of forming an insulating film so as to be thicker than the surface insulating film ; and ion-implanting obliquely with reference to the insulating film formed on the side surface of the gate electrode to form a punch-through suppressing layer in the semiconductor substrate. forming a said as a mask the insulating film formed on the side surface of the gate electrode and the gate electrode, and a source, the ion for forming the drain from the vertical direction to the semiconductor substrate surface
Implanting boron difluoride ions Te, source by activating the implanted ions by heat treatment, and forming a drain, the injection of the boron difluoride ions, ball during the heat treatment
Of boron implanted in the gate electrode due to abnormal diffusion of boron.
Ron atoms penetrate through the gate insulating film and channel region
A method for manufacturing a MIS transistor, characterized in that the MIS transistor is performed at an accelerating voltage so as not to exceed 2. The insulating film on the surface of the gate electrode is
Project drain showing the range of boron ion implantation
Di Rp or more , M according to claim 1, characterized in that
Method of manufacturing IS transistor. 3. The semiconductor substrate is a single crystal silicon substrate, the gate electrode is made of polycrystalline silicon, and the step of forming the insulating film includes the step of forming the insulating film by thermal oxidation. 3. The method of manufacturing a MIS transistor according to claim 1, which is a step of simultaneously forming an oxide film on each surface of the crystalline silicon substrate. 4. ions for forming the punch-through suppression layer may be any of claims 1 to 3, characterized in that a compound ions or compound ions containing boron ions or boron, including phosphorus or phosphorus 1. A method of manufacturing a MIS transistor according to one.