JP3376305B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, with higher performance and higher speed of LSIs, MIS transistors have been gradually miniaturized, and the gate insulating film of MIS transistors has been rapidly thinned. Therefore, a technique for forming an extremely thin gate insulating film uniformly and with high reliability is required.

Further, as represented by an EEPROM,
In an element in which the gate insulating film is used as a tunnel insulating film, a high electric field is applied to the gate insulating film during writing and erasing. When a high electric field is applied to the gate insulating film, electrons having high energy from the electric field pass through the insulating film, so that the gate insulating film is required to have high dielectric breakdown resistance.

In response to such requirements, it is known that the film quality is improved by introducing a halogen element, particularly fluorine, into a gate insulating film typified by a silicon oxide film. Also, it has been reported from several groups that the introduction of fluorine atoms into the silicon / silicon oxide film interface suppresses the generation of interface states (for example, Y. Nishioka et al., IEEE).
Electron Device Lett. 10, p
p. 141-143 (1989)). Further, there is also a report that introduction of fluorine atoms into the silicon substrate can suppress the reverse leakage current of the pn junction.

As a method for introducing fluorine into the gate insulating film or the substrate, there is known a method in which fluorine is ion-implanted into the gate electrode and the fluorine is introduced into the gate insulating film or the substrate by thermal diffusion.

However, in the method of introducing fluorine from the gate electrode into the gate insulating film or the substrate, the concentration of fluorine in the gate insulating film or the substrate under the gate electrode, especially the fluorine concentration in the channel length direction of the transistor, becomes uniform. However, it is impossible to control the profile of the fluorine concentration of the gate insulating film or the substrate in the channel length direction. In general, the optimum fluorine concentration for suppressing the interface state and the optimum fluorine concentration for suppressing the reverse leakage current of the pn junction are not the same, that is, in the region corresponding to the center of the gate electrode and near the end of the gate electrode. The optimum fluorine concentration differs from the corresponding region (it is better to make the fluorine concentration near the edge higher than the fluorine concentration near the center). Therefore, if the fluorine concentration profile in the channel length direction cannot be controlled, there is a problem that it is difficult to manufacture a highly reliable element as a whole element.

When fluorine ions are introduced into the gate electrode by ion implantation, the source gas, for example, BF ₃ gas is electrically decomposed, the fluorine ions are extracted by mass separation, and the fluorine ions are ion-implanted. . However, the ion implantation apparatus used in a normal production line cannot sufficiently take out fluorine ions. Therefore, there is a problem in that the fluorine ion implantation process takes a long time and the productivity is reduced. Furthermore, mass separation of fluorine ions is also difficult because the mass difference between fluorine ions and OH ₃ ⁺ ions is small.

[0008]

As described above, in the method of introducing a halogen element such as fluorine into the gate insulating film or the substrate from the gate electrode, the concentration profile of the halogen element in the gate insulating film or the substrate is controlled. I can't
There is a problem that it is difficult to manufacture a highly reliable element as a whole element.

Further, when a halogen element such as fluorine is introduced into the gate electrode by ion implantation, there is a problem that the halogen element ions cannot be extracted sufficiently and a long time is spent in the ion implantation step.

The present invention has been made to solve the above-mentioned conventional problems, and it is an object of the present invention to provide a method for manufacturing a semiconductor layer device capable of optimizing the concentration profile of the halogen element in the gate insulating film or the substrate. The purpose of 1.

A second object of the present invention is to provide a method of manufacturing a semiconductor layer device, which can sufficiently extract halogen element ions during ion implantation and can shorten the time of the ion implantation step. .

[0012]

A method of manufacturing a semiconductor device according to the present invention corresponds to a gate electrode formed on a first conductivity type semiconductor substrate via a gate insulating film and both ends of the gate electrode. In a method of manufacturing a semiconductor device having a second conductivity type diffusion layer formed in a region and serving as a source / drain region, a step of forming an insulating film containing a halogen element on at least a side surface of a gate electrode; And a step of introducing the contained halogen element into the surface region of the gate insulating film and the semiconductor substrate by heat treatment (invention A).

A typical example of the halogen element is fluorine. Further, as the gate insulating film,
Typically, a silicon oxide film (SiO ₂ ) can be used, but a silicon nitride film (SiN), a silicon oxynitride film (SiON), or the like can also be used.

As a method of forming an insulating film containing a halogen element on at least a side surface of a gate electrode, a method of ion-implanting a halogen element into an insulating film formed on at least a side surface of a gate electrode, an insulating film on at least a side surface of a gate electrode There is a method of introducing a gas containing a halogen element into the film forming atmosphere when forming the film.

According to the present invention, the halogen element is introduced into the gate insulating film and the surface region of the semiconductor substrate below the gate insulating film from the insulating film formed on at least the side surface of the gate electrode (around the gate electrode). More halogen element can be introduced into the region corresponding to the end portion of the gate electrode than to the region corresponding to the center portion of the electrode.
That is, in the channel length direction of the transistor, a concentration profile in which the proportion of the halogen element is higher in the end portion than in the central portion can be obtained. Therefore, since the halogen element concentration in the region corresponding to the end portion of the gate electrode can be increased, the reverse leakage current of the pn junction can be suppressed and, compared with the region corresponding to the end portion of the gate electrode, Also, since the halogen element concentration in the region corresponding to the central portion can be lowered, the generation of interface states can also be effectively suppressed.

Further, the inventor of the present application has studied in detail the origin and mechanism of the dielectric breakdown and stress leak current of the gate oxide film. As a result, the dielectric breakdown mechanism of the gate oxide film and the stress leak current generation mechanism are
It became clear that it was governed by a common mechanism of kind. The first mechanism is caused by a dangling bond (≡Si ·) of silicon generated by the electron injected into the gate oxide film breaking the Si—H bond in the film. The mechanism of is a dangling bond (≡Si.) Generated by breaking the weakly strained Si-O bond in the film.
Is the cause.

Dielectric breakdown of the gate oxide film is caused when trivalent silicon atoms (≡Si ⁺ ) formed by trapping holes in dangling bonds (≡Si.) Are connected from the silicon substrate to the gate electrode. , This connection serves as a leak path for electrons and causes dielectric breakdown. On the other hand, the stress leak current is generated by the dangling bond (≡Si ·) located almost at the center of the gate oxide film acting as a “stepping stone” when the electrons tunnel. Therefore, it is important to prevent dangling bonds (≡Si ·) from occurring over the entire area of the gate oxide film thickness direction. In addition, the amount of Si-H bond and weakly strained Si
It was also found that the amount of —O bond was not independently determined but was present in the film in a proportional relationship with each other.

From the above, the dangling bond (≡
It is possible to obtain a highly reliable gate oxide film by terminating Si.) With a halogen element such as fluorine. However, if the amount of introduction of the halogen element is too large, the reliability of the gate oxide film is deteriorated. Therefore, there is an optimum value for the concentration of the halogen element for terminating the dangling bond. On the other hand, as already mentioned, p
From the viewpoint of suppressing the reverse leakage current of the n-junction, it is preferable to increase the halogen element concentration in the region corresponding to the vicinity of the end of the gate electrode.

According to the present invention, more halogen element can be introduced into the region corresponding to the vicinity of the end of the gate electrode, so that the reverse leak current of the pn junction can be suppressed and the dangling bond is terminated. It is also possible to achieve optimization of the concentration of the halogen element for this purpose, and it is also possible to improve the dielectric breakdown resistance of the gate insulating film and the stress-induced current generation resistance.

In the method of manufacturing a semiconductor device according to the present invention, a gate electrode is formed on a first conductivity type semiconductor substrate via a gate insulating film, and a source electrode formed in a region corresponding to both ends of the gate electrode. In a method of manufacturing a semiconductor device having a second-conductivity-type diffusion layer serving as a drain region, a step of introducing a halogen element compound into a gate electrode and a heat treatment of a halogen element contained in the halogen element compound introduced into the gate electrode And a step of introducing it into the gate insulating film at least (invention B).

The halogen element compound is preferably introduced into the gate electrode by ion implantation. Further, the halogen element compound is preferably a compound containing an impurity element which serves as a donor or an acceptor and a halogen element. Further, the halogen element compound is preferably a compound in which two or more halogen elements are contained in one molecule.

According to the present invention, the halogen element is introduced into the gate electrode in the form of a halogen element compound. Therefore, it is not necessary to perform a process of decomposing the halogen element compound or taking out only the fluorine ions by the mass separation during the ion implantation, and the ion implantation step can be performed in a shorter time than before. Further, the halogen element compound introduced into the gate electrode can be introduced into the gate insulating film as a halogen element simple substance by heat treatment. Therefore, the characteristics and reliability of the MIS type semiconductor element can be improved, as described above, such as the film quality of the gate insulating film being improved.

Further, by using a compound containing an impurity element serving as a donor or an acceptor and a halogen element as the halogen element compound, it is possible to introduce impurities into the source / drain regions and the polysilicon gate at the same time. Further, by using a compound containing two or more halogen elements in one molecule as the halogen element compound, the halogen element can be efficiently introduced into the gate electrode.

[0024]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a cross-sectional structure of a MIS transistor according to the first embodiment.

Reference numeral 51 is a p-type silicon substrate, 52 is an element isolation region, 53 is a gate insulating film containing fluorine, 54 is a gate electrode made of polysilicon, and 55 is a diffusion layer (source / drain) into which n-type impurities are introduced. Area). Reference numeral 56 is an insulating film (for example, a CVD silicon oxide film) containing fluorine formed around the side wall of the gate electrode 54, and fluorine atoms are introduced into the gate insulating film 53 by thermal diffusion from the insulating film 56. . Therefore, the gate insulating film 5
3 and the silicon substrate 5 near the interface with the gate insulating film 53
1, a larger amount of halogen element is introduced into the region corresponding to the vicinity of the end of the gate electrode 54 than in the region corresponding to the center of the gate electrode 54. Reference numeral 57 denotes an interlayer insulating film (CVD silicon oxide film or the like).
Through the contact hole provided in the gate electrode 54
The Al wiring 58 is connected to the source / drain region 55.

Next, referring to FIG. 2, in the first method of manufacturing the MOS transistor having the structure shown in FIG. 1, fluorine is mainly applied from the silicon oxide film 56 to the gate insulating film 53 and the silicon substrate 51. The process of introducing will be mainly described.

First, the plane orientation (100) and the specific resistance 4 to 6Ω.
A groove for element isolation is formed on the p-type silicon substrate 51 of cm by reactive ion etching. Subsequently, an element isolation region 52 is formed by embedding, for example, an LP-TEOS film in the groove (FIG. 2A).

Next, at 750 ° C. and 1 atm, for example,
The silicon substrate 51 is exposed to a mixed gas of oxygen gas and hydrogen gas to form a silicon oxide film. Furthermore, for example, 9
At 00 ° C., nitrogen atoms are introduced into the silicon oxide film by exposing the silicon oxide film to nitric oxide gas (NO) or nitrous oxide gas (N ₂ O) diluted to 10% with nitrogen gas. The gate insulating film 53 is formed (FIG. 2B).

Next, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and the polysilicon film is patterned to form a gate electrode 54. Then, for example, 45
At 0 ° C. and a pressure of 10 mTorr to 1 atm, using a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas, for example, a CVD silicon nitride film 5 of 50 to 2000 Å
6 is deposited. After that, fluorine ions are implanted over the entire surface at an acceleration voltage of 10 to 50 keV and a dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ^-2 . Further, the substrate is exposed to a nitrogen gas atmosphere at a temperature of, for example, 300 to 850 ° C. for 1 to 60 minutes to introduce the fluorine atoms injected into the CVD silicon nitride film 56 into the p-type silicon substrate 51 and the silicon insulating film 53. (FIG. 2 (c)).

The subsequent steps are the same as the steps for manufacturing a normal MOS transistor. That is, for example, the acceleration voltage 2
Ion implantation of arsenic is performed with 0 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to form a source region / drain region. Subsequently, C which becomes an interlayer insulating film is formed on the entire surface by chemical vapor deposition.
A VD silicon oxide film is deposited, and a contact hole is opened in this interlayer insulating film. Then, an Al film is deposited on the entire surface by a sputtering method, and the Al film is patterned by reactive ion etching, whereby a MOS transistor having a structure as shown in FIG. 1 is completed.

Next, with reference to FIG. 3, a second method of manufacturing a MOS transistor having the structure shown in FIG. 1 will be described.

First, the plane orientation (100) and the specific resistance 4 to 6 Ω
A groove for element isolation is formed on the p-type silicon substrate 51 of cm by reactive ion etching. Subsequently, an element isolation region 52 is formed by embedding, for example, an LP-TEOS film in the groove (FIG. 3A).

Next, for example, at 750 ° C. and 1 atm,
The silicon substrate 51 is exposed to a mixed gas of oxygen gas and hydrogen gas to form a silicon oxide film. Furthermore, for example, 9
At 00 ° C., nitrogen atoms are introduced into the silicon oxide film by exposing the silicon oxide film to nitric oxide gas (NO) or nitrous oxide gas (N ₂ O) diluted to 10% with nitrogen gas. The gate insulating film 53 is formed (FIG. 3B).

Next, a polysilicon film is deposited on the entire surface by a chemical vapor deposition method, and this polysilicon film is patterned to form a gate electrode 54. Then, for example, 60
The substrate is exposed to a mixed gas of oxygen gas and NF ₃ gas at a temperature of 0 to 1000 ° C. and a pressure of 10 mTorr to 1 atmosphere to form a silicon oxide film 56a containing fluorine having a film thickness of 10 to 200 Å around the gate electrode 54. To do. continue,
For example, at a temperature of 450 ° C. and a pressure of 10 mTorr to 1 atmosphere, a mixed gas of SiH ₄ gas and NH ₃ gas diluted with nitrogen gas is used to deposit a CVD silicon nitride film 56b of, for example, 50 to 2000 Å. Furthermore, for example, 300-
The substrate is exposed to a nitrogen gas atmosphere at a temperature of 850 ° C. for 1 to 60 minutes to remove fluorine atoms from the silicon oxide film 56a.
It is introduced into the mold silicon substrate 51 and the silicon insulating film 53 (FIG. 3C).

Thereafter, a MOS having a structure as shown in FIG. 1 is obtained by going through the same steps as described with reference to FIG.
The transistor is completed.

In the present embodiment, the method of forming the silicon insulating film containing fluorine around the gate electrode is not limited to the above example. For example, 7
The surface of the polysilicon film to be the gate electrode may be oxidized by exposing the gate electrode to a mixed gas atmosphere in which a halide such as NF ₃ is added to oxygen gas and hydrogen gas at 50 to 1050 ° C. In addition, around the gate electrode made of a polysilicon film, SiH ₄ gas diluted with nitrogen gas and NH
Mixed gas of ₃ gases, or oxygen gas, hydrogen gas and N
The fluorine-containing silicon film may be formed using a mixed gas of F ₃ gas. Further, a fluorine-containing silicon nitride film may be formed around the gate electrode made of a polysilicon film by using a mixed gas of SiH ₄ gas and NF ₃ gas.

As shown in FIG. 4, the gate electrode 54
Of the silicon insulating films 56c-5 having different fluorine concentrations on the side walls of the
6f may be laminated, and fluorine may be introduced into the gate insulating film 53 and the silicon substrate 51 from these laminated films. By increasing the fluorine concentration in the order of 56c to 56f, the fluorine profile near the end of the gate electrode can be changed as shown by the dotted line.

As described above, in the present embodiment, by introducing fluorine from the insulating film formed around the gate electrode into the gate insulating film and the silicon substrate in the vicinity of the interface with the gate insulating film, the gate electrode More halogen element can be introduced into the region corresponding to the end portion of the gate electrode than the region corresponding to the central portion. Therefore, by appropriately controlling the fluorine concentration in the insulating film or the heat treatment conditions when diffusing fluorine, it becomes possible to form the gate insulating film and the channel region having the desired fluorine concentration and fluorine profile.

(Embodiment 2) Next, a method of manufacturing a MIS transistor according to a second embodiment of the present invention will be described.

FIGS. 5A to 7L are process sectional views showing a first manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further heat-treating at high temperature (FIG. 5A).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is further formed as a gate electrode (FIG. 5B). ).

Next, the resist mask 8a is used to mask the entire surface of the region where the p-channel MOSFET is to be formed and the region where the n-channel MOSFET is to be formed. Then, the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrode 5a in the p-channel MOSFET region (FIG. 5).
(C)).

Next, after removing the resist mask, BF
₂ ions 6 are applied at an acceleration voltage of 30 keV, for example, 5 × 10 ¹⁴ c
M ⁻² ions are implanted to form a diffusion layer region 10a on the p-channel MOSFET side. At this time, p-channel MOSF
BF ₂ ions are also implanted into the ET polycrystal silicon film and the polycrystal silicon film in the n-channel MOSFET region (FIG. 5D).

Next, the resist mask 8b is used to mask the entire gate portion in the region where the n-channel MOSFET is to be formed and the entire region where the p-channel MOSFET is to be formed. Then, the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrode 5b in the n-channel MOSFET region (FIG. 6).
(E)).

Next, after removing the resist mask 8b,
Again, only the p-channel region is masked with the resist 8c. Then, arsenic ions or phosphorus ions 7 are implanted into the entire surface at an acceleration voltage of 30 keV at a dose of 1 × 10 ¹⁵ cm ^-2 , and n
A diffusion layer region 10b is formed on the channel MOSFET side. At this time, the ions are also implanted into the polycrystalline silicon film 5b in the n-channel MOSFET region (FIG. 6).
(F)).

Next, the sidewall insulating film 12 made of a silicon nitride film having a thickness of about 10 nm is formed on the sidewalls of the gate electrodes 5a and 5b by using the LP-CVD method. This sidewall insulating film is obtained, for example, by depositing a 10-nm-thick silicon nitride film on the entire surface by a CVD method and then performing anisotropic dry etching (FIG. 6G).

Next, the resist mask 8d is used to mask the n-channel MOSFET region, boron ions 9 are implanted at an acceleration voltage of 20 keV, for example, at 3 × 10 ¹⁵ cm ⁻² to form the p-type source / drain diffusion layer 11a. Form.
At this time, boron ions are also implanted into the polycrystalline silicon film 5a in the p-channel MOSFET region. In this ion implantation step, during the above-mentioned BF ₂ ion implantation step,
Since the polycrystalline silicon surface and the substrate surface are made amorphous, the range of boron ions can be reduced (Fig. 6).
(H)).

Next, the p-channel MOSFET region is masked with a resist 8e, and arsenic ions or phosphorus ions 7 are added.
For example, 3 × 10 ¹⁵ cm ^-2 ions are implanted at 50 keV, and n
The source / drain diffusion layer 11b of the mold is formed. At this time, the polycrystalline silicon film 5 in the n-channel MOSFET region
The above ions are also implanted in b. After removing the resist mask, the substrate is heat-treated in a nitrogen atmosphere at 950 ° C. for 1 minute to activate the dopant in each gate electrode and the dopant in the source / drain diffusion layer. At this time, the fluorine implanted as BF ₂ ions into each gate electrode 5a and 5b diffuses into each gate oxide film 4 by heat treatment (FIG. 7 (i)).

Then, a titanium thin film having a thickness of 25 nm is formed on the entire surface,
A titanium nitride thin film having a thickness of 50 nm is sequentially deposited by the sputtering method. Then, heat treatment is performed at 700 ° C. for 1 minute in a nitrogen atmosphere to react all the titanium thin film with the polycrystalline silicon (gate electrode) and the silicon substrate, and the titanium silicide film only on the gate electrode and the source / drain diffusion layer region. 13 is formed. Then, for example, with an aqueous solution of hydrofluoric acid, a mixed solution of sulfuric acid and hydrogen peroxide,
The titanium nitride film 13 and the unreacted titanium thin film on the insulating film are peeled off (FIG. 7 (j)).

Next, as an interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 having a thickness of nm by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 7 (k)).

Next, silicon and copper are each added, for example, to 0.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 7 (l)).

Although the ion species used to introduce fluorine into the gate electrode is BF ₂ in this example, the ion species are not limited to this, and, for example, fluoride ions of silicon, fluorine ions of arsenic and phosphorus are used. A compound ion or a compound ion of arsenic or phosphorus containing fluorine may be used (the same applies to other manufacturing process examples below).

FIGS. 8A to 11M are process sectional views showing a second manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further heat-treating at high temperature (FIG. 8A).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is further formed as a gate electrode (FIG. 8B). ).

Next, BF ₂ ions 6 are formed on the entire surface of the silicon substrate.
Is implanted at a dose amount of 5 × 10 ¹⁴ cm ⁻² at, for example, 30 keV. Then, in a nitrogen atmosphere, for example, at 850 ° C.,
Heat treatment is performed for 30 minutes. At this time, the fluorine implanted as BF ₂ ions into the polycrystalline silicon thermally diffuses into the gate oxide film 4 (FIG. 8C).

Next, the resist mask 8a is used to mask the entire gate portion in the region where the p-channel MOSFET is to be formed and the entire region where the n-channel MOSFET is to be formed. Then, the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrode 5a in the p-channel MOSFET region (FIG. 8).
(D)).

Next, BF ₂ ions 6 are applied, for example, to an acceleration voltage of 3
A diffusion layer region 10a is formed on the p-channel MOSFET side by implanting 5 × 10 ¹⁴ cm ⁻² ions at 0 keV (FIG. 9E).

Next, after removing the resist mask, the gate portion of the n-channel MOSFET and the p-channel MOSF are formed.
The entire surface of the ET region is covered with the resist mask 8b. continue,
The polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrode 5b in the n-channel MOSFET region (FIG. 9 (f)).

Next, after removing the resist mask, only the p-channel region is masked again with the resist 8c. Subsequently, arsenic ions or phosphorus ions 7 are implanted into the entire surface at an acceleration voltage of 30 keV, for example, at 1 × 10 ¹⁵ cm ⁻² to form a diffusion layer region 10b on the n-channel MOSFET side.
At this time, the ions are also implanted into the polycrystalline silicon film 5b in the n-channel MOSFET region (FIG. 9).
(G)).

Next, a thickness of 10 n is obtained by using the LP-CVD method.
A sidewall insulating film 12 made of a silicon nitride film having a thickness of about m is formed (FIG. 10H).

Next, the n-channel MOSFET region is masked using the resist mask 8d. Subsequently, boron ions 9 are applied at an acceleration voltage of 20 keV, for example, 3 × 10 ¹⁵ c
p − type source / drain diffusion layer 11 after m ⁻² ion implantation
a is formed. At this time, boron ions are also implanted into the polycrystalline silicon film 5a in the p-channel MOSFET region. In this ion implantation step, since the polycrystalline silicon surface and the substrate surface are made amorphous during the above-mentioned BF ₂ ion implantation step, the range of boron ions can be reduced (FIG. 10 (i)).

Next, the p-channel MOSFET region is masked with a resist 8e, and subsequently, arsenic ions or phosphorus ions 7 are implanted at, for example, 40 keV and 3 × 10 ¹⁵ cm ⁻² ions to form an n-type source / drain diffusion layer 11b. To form. At this time, the ions are also implanted into the polycrystalline silicon film 5b in the n-channel MOSFET region. Next, the substrate is heat-treated in a nitrogen atmosphere at 950 ° C. for 1 minute to activate the dopant in each gate electrode and the dopant in each source / drain diffusion layer. At this time, the fluorine implanted as BF ₂ ions into each gate electrode 5a and 5b diffuses into each gate oxide film by heat treatment (FIG. 1).
0 (j)).

Next, a titanium thin film having a thickness of 25 nm is formed on the entire surface,
A titanium nitride thin film having a thickness of 50 nm is sequentially deposited by the sputtering method. Then, heat treatment is performed at 700 ° C. for 1 minute in a nitrogen atmosphere to react all the titanium thin film with the polycrystalline silicon (gate electrode) and the silicon substrate, and the titanium silicide film only on the gate electrode and the source / drain diffusion layer region. 13 is formed. Then, for example, with an aqueous solution of hydrofluoric acid, a mixed solution of sulfuric acid and hydrogen peroxide,
The titanium nitride film 13 and the unreacted titanium thin film on the insulating film are peeled off (FIG. 11 (k)).

Next, as an interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 having a thickness of nm by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 11 (l)).

Next, silicon and copper are each added, for example, to 0.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 11M).

Although the ion species used to introduce fluorine into the gate electrode is BF ₂ in this example, it is not limited to this and, for example, fluoride ions of silicon, fluorine ions of arsenic and phosphorus are used. A compound ion or a compound ion of arsenic or phosphorus containing fluorine may be used. Although BF ₂ ions are used to form the diffusion layer 10a in the p-channel MOSFET region, boron may be ion-implanted at a low acceleration voltage, for example, 5 keV. In this case, the source
Since excess fluorine is not introduced into the gate oxide film from the drain diffusion layer, a highly reliable gate oxide film can be obtained.

12A to 14K are process cross-sectional views showing a third manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further heat-treating at high temperature (FIG. 12A).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is further formed as a gate electrode (FIG. 12B). ).

Next, using a resist mask (not shown), the polycrystalline silicon film is etched by the reactive ion etching method, and n-channel and p-channel MOSFEs are used.
The gate electrodes 5a and 5b of T are formed (FIG. 12).
(C)).

Next, BF ₂ ions 6 are implanted into the entire surface of the substrate at a dose of 5 × 10 ¹⁴ cm ^{-2 at} 30 keV, for example. Then, in a nitrogen atmosphere, for example, at 850 ° C. for 3
Heat treatment is performed for 0 minutes. At this time, the fluorine implanted as BF ₂ ions into the polycrystalline silicon film thermally diffuses into the gate oxide film 4. At this time, the heat treatment may not be performed, and the heat diffusion may be performed at the same time as the heat treatment for activating the dopant in the polycrystalline silicon of the gate electrode and the dopant in the source / drain diffusion layer in a later step (FIG. 12).
(D)).

Next, the p-channel MOSFET region is masked using the resist mask 8a. Subsequently, arsenic ions or phosphorus ions 7 are implanted at an acceleration voltage of 30 keV at a dose of 1 × 10 ¹⁵ cm ^-2 , and n-channel MOSFE is used.
The diffusion layer region 10b is formed on the T side. At this time, the ions are also implanted into the gate electrode of the n-channel MOSFET (FIG. 13 (e)).

Next, the side wall insulating film 12 made of a silicon nitride film having a thickness of about 10 nm is formed on the side wall of each gate electrode by the LP-CVD method (FIG. 13F).

Next, the n-channel MOSFET region is masked using the resist mask 8b. Subsequently, boron ions 9 are implanted at, for example, 5 × 10 ¹⁵ cm ⁻² at an acceleration of 10 keV, and a diffusion layer region 11 is formed on the p-channel MOSFET side.
a is formed. At this time, boron ions are also implanted into the gate electrode of the p-channel MOSFET (FIG. 13).
(G)).

Next, after removing the resist mask 8b,
The p-channel MOSFET region is masked using the resist mask 8c. Then, arsenic ions or phosphorus ions 7
Is ion-implanted at an acceleration voltage of 30 keV at 5 × 10 ¹⁵ cm ⁻² to form a diffusion layer region 11 on the n-channel MOSFET side.
b is formed. At this time, the ions are also implanted into the gate electrode of the n-channel MOSFET. Next, after removing the resist, the substrate is heat-treated in a nitrogen atmosphere at 950 ° C. for 1 minute to activate the dopant in each of the gate electrodes 5a and 5b and the dopant in each of the source / drain diffusion layers. At this time, the fluorine implanted as BF ₂ ions into each gate electrode diffuses into each gate oxide film by heat treatment (FIG. 13 (h)).

Next, a titanium thin film having a thickness of 25 nm is formed on the entire surface,
A titanium nitride thin film having a thickness of 50 nm is sequentially deposited by the sputtering method. Then, heat treatment is performed at 700 ° C. for 1 minute in a nitrogen atmosphere to react all the titanium thin film with the polycrystalline silicon (gate electrode) and the silicon substrate, and the titanium silicide film only on the gate electrode and the source / drain diffusion layer region. 13 is formed. Then, for example, with an aqueous solution of hydrofluoric acid, a mixed solution of sulfuric acid and hydrogen peroxide,
The titanium nitride film 13 and the unreacted titanium thin film on the insulating film are peeled off (FIG. 14 (i)).

Next, as an interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 having a thickness of nm by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 14 (j)).

Next, silicon and copper are added, for example, to 0.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 14K).

FIGS. 15 (a) to 17 (i) are process sectional views showing a fourth manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further performing heat treatment at a high temperature. (FIG. 15 (a)).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is further formed as a gate electrode (FIG. 15B). ).

Next, the resist mask 8a is used to mask the region where the p-channel MOSFET is to be formed, and arsenic or phosphorus ions 7 are ion-implanted (FIG. 15).
(C)). At this time, arsenic or phosphorus ions are implanted only into the polycrystalline silicon film 5 in the n-channel MOSFET formation region.

Next, after removing the resist film, BF ₂ ions 6 are applied to the entire surface of the substrate at a dose of 5 ×, for example, at 30 keV.
^Implant 10 ¹⁴ cm ^-2 ions. After that, heat treatment is performed in a nitrogen atmosphere at, for example, 850 ° C. for 30 minutes. At this time, the fluorine implanted as BF ₂ ions into the polycrystalline silicon film 5 thermally diffuses into the gate oxide film. Also,
At this time, heat treatment may not be performed, and heat diffusion may be performed in a heat treatment step of activating the dopant in the polycrystalline silicon film to be the gate electrode and the dopant in the source / drain diffusion layer in the subsequent step (FIG. 16 (d). )).

Next, the n-channel MOSFET region is masked using the resist mask 8b. Subsequently, boron ions 9 are implanted at an acceleration voltage of 10 keV, for example, at 3 × 10 ¹⁵ cm ⁻² (FIG. 16E).

Next, the gate portion is masked with the resist 8c and the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrodes 5a and 5b (FIG. 16 (f)).

Next, a sidewall insulating film 12 made of a silicon nitride film having a thickness of about 10 nm is formed on the sidewall of the gate electrode, and the source / drain diffusion layers 10a, 11a and 1 of the p-channel and n-channel MOSFETs are formed.
0b and 11b are formed (FIG. 17 (g)).

Next, as the interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 having a thickness of nm by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 17 (h)).

Next, silicon and copper are added, for example, to each other.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 17I).

18A to 20J are process cross-sectional views showing a fifth manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further heat-treating at high temperature (FIG. 18A).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is formed as a gate electrode (FIG. 18B). ).

Next, the resist mask 8a is used to mask the region where the p-channel MOSFET is to be formed, and arsenic or phosphorus ions 7 are ion-implanted. At this time, arsenic or phosphorus ions 7 are implanted only into the polycrystalline silicon film 5 in the n-channel MOSFET formation region (FIG. 18).
(C)).

Next, after removing the resist mask, the n-channel MOSFET formation region is masked using the resist mask 8b, and boron ions 9 are, for example, 3 × 10 ¹⁵ over the entire surface.
cm ⁻² ion implantation is performed (FIG. 18D).

Next, the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrodes 5a and 5b in the n-channel and p-channel MOSFET regions. Then, the p-channel MOSF is formed by the resist mask 8c.
Only the ET region is masked and arsenic or phosphorus ions 7 are ion-implanted to form an n-type source / drain diffusion layer 10b. At this time, the ions are also implanted into the gate electrode 5b in the n-channel MOSFET region (FIG. 19).
(E)).

Next, after removing the resist mask, BF ₂ ions 6 are applied to the entire surface at a dose of 5 ×, for example, at 30 keV.
^Implant 10 ¹⁴ cm ^-2 ions. After that, heat treatment is performed at 850 ° C. for 30 minutes in a nitrogen atmosphere. At this time, the fluorine implanted into the gate electrodes 5a and 5b as BF ₂ ions thermally diffuses into the gate oxide film. Further, at this time, the heat treatment may not be performed, and the heat diffusion may be performed at the same time as the heat treatment for activating the dopant in the polycrystalline silicon to be the gate electrode and the dopant in the source / drain diffusion layer in the subsequent step (FIG. 19 (f )).

Next, the side wall of each gate electrode has a thickness of 10 nm.
A side wall insulating film 12 made of a silicon nitride film is formed. Further, a resist mask 8d is formed in the p-channel MOSFET region, and the source / source of the n-channel MOSFET is formed.
The drain diffusion layer 11b is formed by ion implantation of arsenic or phosphorus ions 7 (FIG. 19 (g)).

Next, a resist mask 8e is formed in the n-channel MOSFET region, and a source / drain diffusion layer 11a of the p-channel MOSFET is formed by ion implantation of boron ions 9 (FIG. 20 (h)).

Next, as an interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 of nm thickness by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 20 (i)).

Next, silicon and copper are added, for example, to 0.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 20 (j)).

In the first to fifth manufacturing process examples described above, the gate electrode of the n-channel MOSFET also contains p-type impurities (boron), but n-type impurities (phosphorus or arsenic). The ion implantation amount of the n-type impurity may be adjusted so that the concentration is higher than the concentration of the p-type impurity.

21 (a) to 22 (h) are process sectional views showing a sixth manufacturing process example of this embodiment.

First, for example, the plane orientation (100) and the specific resistance 4
An n-type silicon substrate 1 having a thickness of 6 .OMEGA.
The element isolation insulating film 2 having a thickness of about 6 μm is formed. Then p
The well region 3 is formed by selectively ion-implanting the type dopant with high acceleration energy and further heat-treating at high temperature (FIG. 21A).

Next, a gate insulating film (silicon oxide film) 4 having a thickness of 3 to 8 nm is formed by thermal oxidation, and a polycrystalline silicon film 5 having a thickness of 200 nm is further formed as a gate electrode. The polycrystalline silicon film 5 contains phosphorus or arsenic as an n-type conductive impurity. This is obtained by adding a compound gas containing phosphorus or arsenic when the polycrystalline silicon film 5 is formed. For example, silane gas (SiH ₄ ) may be mixed with phosphine gas (PH ₃ ) or arsine gas (AsH ₃ ) and supplied to a heated silicon substrate. Alternatively, phosphorus or arsenic may be added after the polycrystalline silicon film is formed. For example, a method in which phosphorus oxychloride (POCl ₃ ) is used to diffuse phosphorus after depositing a polycrystalline silicon film, or a method in which phosphorus ions or arsenic ions are introduced by an ion implantation method may be used (FIG. 21B). .

Next, a resist mask (not shown) is used to mask the entire surface of the region where the p-channel MOSFET is to be formed and the region where the n-channel MOSFET is to be formed. Then, the polycrystalline silicon film is etched by the reactive ion etching method, and p
A gate electrode 5a in the channel MOSFET region is formed. Next, after removing the resist mask, BF ₂ ions 6 are ion-implanted at 5 × 10 ¹⁴ cm ⁻² at an acceleration voltage of 30 keV, and the diffusion layer region 10 is formed on the p-channel MOSFET side.
a is formed. At this time, BF ₂ ions are also implanted into the polycrystalline silicon film 5a of the p-channel MOSFET (FIG. 21 (c)).

Next, the resist mask 8a is used to mask the entire gate region of the n-channel MOSFET formation region and the p-channel MOSFET formation region. Then, the polycrystalline silicon film is etched by the reactive ion etching method to form the gate electrode 5b in the n-channel MOSFET region. Then, arsenic ions or phosphorus ions 7 are applied, for example, at an acceleration voltage of 3
1 × 10 ¹⁵ cm ⁻² ions are implanted at 0 keV to form a diffusion layer region 10b on the n-channel MOSFET side. (Fig. 2
1 (d)).

Next, the sidewall insulating film 12 made of a silicon nitride film having a thickness of about 10 nm is formed on the sidewalls of the gate electrodes 5a and 5b by the LP-CVD method. This sidewall insulating film is obtained by, for example, depositing a 10-nm-thick silicon nitride film on the entire surface by a CVD method and then performing anisotropic dry etching. Next, the resist mask 8b is used to mask the n-channel MOSFET region, and the boron ions 9 are, for example, 3 × 10 ¹⁵ cm ⁻² at an acceleration voltage of 20 keV.
Ions are implanted to form a p-type source / drain diffusion layer 11a. At this time, boron ions are also implanted into the polycrystalline silicon film 5a in the p-channel MOSFET region. In this ion implantation step, since the polycrystalline silicon surface and the substrate surface become amorphous during the above-mentioned BF ₂ ion implantation step, the range of boron ions can be reduced (FIG. 22 (e)).

Next, the p-channel MOSFET region is masked with a resist 8c, and arsenic ions or phosphorus ions 7 are added.
For example, 3 × 10 ¹⁵ cm ^-2 ions are implanted at 50 keV, and n
The source / drain diffusion layer 11b of the mold is formed. At this time, the polycrystalline silicon film 5 in the n-channel MOSFET region
The above ions are also implanted in b. After removing the resist mask, the substrate is heat-treated in a nitrogen atmosphere at 950 ° C. for 1 minute to activate the dopant in each gate electrode and the dopant in the source / drain diffusion layer. At this time, the fluorine implanted as BF ₂ ions into each gate electrode 5a and 5b diffuses into each gate oxide film 4 by heat treatment (FIG. 22 (f)).

Next, as an interlayer insulating film, a thickness of 300 is formed on the entire surface.
After depositing a silicon oxide film 14 having a thickness of nm by the CVD method, a contact hole 15 is opened in the silicon oxide film by anisotropic dry etching (FIG. 22G).

Next, silicon and copper are added, for example, to 0.
After forming an aluminum film having a thickness of 800 nm containing 5% each, the film is patterned to form a wiring 16 connected to the gate electrode and the source / drain diffusion layer.
After that, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen (FIG. 22H).

In the sixth manufacturing process example described above, the gate electrode of the n-channel MOSFET also contains p-type impurities (boron), but the concentration of the n-type impurities (phosphorus or arsenic) is p-type. The ion implantation amount of the n-type impurity may be adjusted so as to be higher than the impurity concentration. Also, p
Although the gate electrode of the channel MOSFET also contains n-type impurities (phosphorus or arsenic), ion implantation of p-type impurities is performed so that the concentration of p-type impurities (boron) is higher than the concentration of n-type impurities. Just adjust the amount.

In this embodiment, a silicon thermal oxide film is used as an example of the gate insulating film, but the gate insulating film is not limited to this, and a silicon oxide film containing nitrogen or a silicon nitride film may be used. Further, not only thermal oxidation but also an oxide film formed by using oxygen activated by microwave or laser may be used, and further a high dielectric film may be used.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

[0116]

According to the present invention, more halogen element can be introduced into the region corresponding to the end portion of the gate electrode than to the region corresponding to the center portion of the gate electrode. It is possible to effectively suppress the leak current and the interface state, and further improve the dielectric breakdown resistance of the gate insulating film and the stress induced current generation resistance.

Further, according to the present invention, by introducing a halogen element in the form of a halogen element compound into the gate electrode, the halogen element compound is decomposed during ion implantation, or only fluorine ions are taken out by mass separation. Such a process is unnecessary, and the ion implantation process can be performed in a short time. Therefore, it is possible to manufacture a semiconductor element having excellent characteristics and reliability such as improvement in film quality of the gate insulating film with high productivity.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross-sectional configuration of a MIS transistor according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view showing the first example of the method for manufacturing the MIS transistor according to the first embodiment of the invention.

3A to 3C are process cross-sectional views showing a second manufacturing method example of the MIS transistor according to the first embodiment of the invention.

FIG. 4 is a view showing another example of the method of manufacturing the MIS transistor according to the first embodiment of the invention.

FIG. 5 is a process cross-sectional view showing the first manufacturing method example of the MIS transistor according to the second embodiment of the invention.

FIG. 6 is a process cross-sectional view showing the first example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 7 is a process cross-sectional view showing the first example of the manufacturing method of the MIS transistor according to the second embodiment of the invention.

FIG. 8 is a process sectional view showing a second example of the method for manufacturing the MIS transistor according to the second embodiment of the present invention.

FIG. 9 is a process cross-sectional view showing the second example of the manufacturing method of the MIS transistor according to the second embodiment of the invention.

FIG. 10 is a process cross-sectional view showing the second example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 11 is a process cross-sectional view showing the second manufacturing method example of the MIS transistor according to the second embodiment of the invention.

FIG. 12 is a process cross-sectional view showing the third example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 13 is a process cross-sectional view showing the third example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 14 is a process cross-sectional view showing the third example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 15 is a process cross-sectional view showing the fourth example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

16A to 16C are process cross-sectional views showing a fourth manufacturing method example of the MIS transistor according to the second embodiment of the invention.

FIG. 17 is a process cross-sectional view showing the fourth example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 18 is a process sectional view showing a fifth manufacturing method example of the MIS transistor according to the second embodiment of the present invention.

FIG. 19 is a process cross-sectional view showing the fifth example of the manufacturing method of the MIS transistor according to the second embodiment of the invention.

FIG. 20 is a process cross-sectional view showing the fifth example of the method for manufacturing the MIS transistor according to the second embodiment of the invention.

FIG. 21 is a process sectional view showing a sixth manufacturing method example of the MIS transistor according to the second embodiment of the invention.

FIG. 22 is a process sectional view showing a sixth manufacturing method example of the MIS transistor according to the second embodiment of the invention.

[Explanation of symbols]

1, 51 ... Silicon substrate 2, 52 ... Element isolation region 3 ... Well region 4, 53 ... Gate insulating film 5 ... Polysilicon film 5a, 5b, 54 ... Gate electrode 6 ... BF ₂ ion 7 ... Arsenic or phosphorus ion 8a-8e ... Resist mask 9 ... Boron ions 10a, 10b, 11a, 11b, 55 ... Diffusion layer (source / drain region) 12 ... Sidewall insulating film 13 ... Silicide film 14, 57 ... Interlayer insulating film 15 ... Contact holes 16, 58 ... Wiring 56, 56a to 56f ... Insulating film containing fluorine

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/092 H01L 29/78 301S

Claims (3)

(57) [Claims] 1. A gate electrode formed on a semiconductor substrate of the first conductivity type via a gate insulating film, and a second conductivity type which is formed in regions corresponding to both ends of the gate electrode and serves as a source / drain region. In a method of manufacturing a semiconductor device having a diffusion layer, a step of forming an insulating film on at least a side surface of a gate electrode, and a step of introducing a halogen element into this insulating film
And a step of introducing the halogen element introduced into the insulating film into the surface regions of the gate insulating film and the semiconductor substrate by heat treatment, the method for manufacturing a semiconductor device. 2. A gate electrode formed on a semiconductor substrate of the first conductivity type through a gate insulating film, and a second conductivity type of a source / drain region formed in regions corresponding to both ends of the gate electrode. In a method of manufacturing a semiconductor device having a diffusion layer, a step of introducing a halogen element compound into a gate electrode, and a step of introducing a halogen element contained in the halogen element compound introduced into the gate electrode into at least the gate insulating film by heat treatment A method of manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein the halogen element compound is a compound containing an impurity element serving as a donor or an acceptor and a halogen element.