JPH0226034A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent defects within an element-forming area from being generated by making a polycrystalline silicon film to be an etching stopper when eliminating a PSG film of other parts leaving the PSG film only at the side wall part of a gate electrode in anisotropy etching of all surfaces. CONSTITUTION:A field insulation film 2 zoning an element forming are is provided on a semiconductor substrate 1, a gate insulation film 3 is formed on the surface of that area, and a gate electrode 4 is formed selectively on that insulation film 3. Then, a polycrystalline silicon film 7 and a silicon oxide film (PSG film) 8 where impurities were added are accumulated in sequence, anisotropic etching is performed on the entire surface leaving the PSG film 8 only on the side wall of the gate, impurities are ion-implanted with the gate electrode 4 and the PSG film 8 as well as the field insulation film 2 as masks, and a high-concentration diffusion area 9 connected to a low-concentration diffusion area 6 is formed within the element-forming area. It prevents the surface within the element forming area from being exposed to etching environment and defects within the area from being generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device having an insulated gate field effect transistor.

[Conventional technology]

Characteristics due to hot electrons generated as insulated gate field effect transistors become smaller.

In order to avoid fluctuations, punch-through, etc., there is a method of relaxing the electric field in the drain region by partially changing the impurity concentration in the diffusion region using a mask layer formed on the sidewalls of the gate electrode.

FIGS. 2(a) to 2(C) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

As shown in FIG. 2(a), a field insulating film is selectively provided on the P-type silicon substrate 1 to define an element formation region, and a gate oxide film 3 is formed on the surface of the element formation region. Next, a polycrystalline silicon layer is deposited on the surface including the gate oxide film 3, and this is selectively etched to form the gate electrode 4. Next, using the gate electrode 4 and field oxide film 3 as a mask, phosphorus ions are applied at a dose of 10"c.
ion implantation at a low concentration of N into the element formation region.
Next, a silicon oxide film 13 is deposited to a thickness of 0.3 μm over the entire surface by CVD.

Next, as shown in FIG. 2(b), the entire surface is anisotropically etched using a reactive ion etching method to form the gate electrode 4.
The silicon oxide film 13 is left only on the side wall portions. Next, arsenic ions are implanted into the element formation region at a dose of 015 cm-2 in alignment with the silicon oxide film 13,
High concentration N+ type diffusion region 9 connected to N− type diffusion region 6
form.

Next, as shown in FIG. 2(c), a silicon oxide film 14 is deposited on the entire surface, and an opening 11 for contact is provided.
By selectively providing an aluminum electrode 12 connected to the N+ type diffusion region 9 of the opening 11, L D D (Light
y Doped Drain) structure.

[Problem to be solved by the invention]

The conventional semiconductor device manufacturing method described above is a process in which the silicon oxide film is anisotropically etched so that the silicon oxide film remains only on the side walls of the gate electrode, and the silicon oxide film other than the side walls is completely removed. As a result, etching is continued even after the gate oxide film on the element forming area is removed, and the surface of the element forming area is exposed to the etching atmosphere, causing defects in the element forming area. will be introduced. If a semiconductor device is formed by continuing to proceed with the manufacturing process with such defects present, there is an open problem that the defects cause leakage current and deterioration of transistor characteristics.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: - providing a field insulating film on the main surface of a conductive type semiconductor substrate to define an element formation region, and forming a gate insulating film on the surface of the element formation region; a step of selectively forming a gate electrode thereon; a step of forming an insulating film covering the gate electrode; and a step of implanting impurity ions into the element forming region using the gate electrode and the field insulating film as masks. A step of forming a low concentration diffusion region of opposite conductivity type in a self-aligned manner, a step of sequentially depositing a polycrystalline silicon film and an impurity-doped silicon oxide film on the surface including the gate electrode, and anisotropic etching of the entire surface. and leaving the silicon oxide film only on the side walls of the gate, and ion-implanting impurities using the gate electrode, the silicon oxide film, and the field insulating film as masks to form the low concentration diffusion region in the element forming region. and a step of forming a high concentration diffusion region connected to the.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a), a P-type silicon substrate 1
A field insulating film 2 is selectively provided thereon to define an element formation region, and a gate oxide film 3 is formed on the surface of the element formation region by thermal oxidation. Next, a polycrystalline silicon layer is deposited on the surface including the gate oxide film 3, and this is selectively etched to form a gate electrode 4 with a width of approximately 1 μm. A film 5 is formed. Next, using the gate electrode 4 and the field insulating film 2 as masks, phosphorus ions are implanted at a dose of 1013 cm@-2 to form a low concentration N@- type diffusion region 6 in the element formation region.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 7 with a thickness of 20 nm and a silicon oxide film containing phosphorus with a thickness of 0.3 μm are formed by CVD on the surface including the silicon oxide film 5. (hereinafter referred to as PSG film) 8 is sequentially deposited.

Next, as shown in FIG. 1(c), the entire surface is anisotropically etched using a reactive ion etching method to form the gate electrode 4.
The PSG film 8 is left only on the side wall portions and the other portions of the PSG film 8 are removed. At this time, the polycrystalline silicon film 7 acts as an etching stopper to prevent the gate oxide film 3 on the N-type diffusion region 6 from being removed, thereby preventing defects from being introduced into the element formation region. 0th order, P
Arsenic ions are applied at a dose of 10”cm in alignment with the SG film 8.
-2 ion implantation to form a high concentration N+ type diffusion region 9 connected to the N- type diffusion region 6.

Next, as shown in FIG. 1(d), the polycrystalline silicon film 7 is oxidized in a water vapor atmosphere, and the silicon oxide film 1 is integrated with the silicon oxide film 5, the gate oxide film 3, and the PSG film 8.
form 0. Here, the PSG film 8 can quickly diffuse the water vapor that oxidizes the polycrystalline silicon film 7, and also has the function of diffusing phosphorus in the PSG JilS into the polycrystalline silicon film 7 to accelerate the oxidation. Next, a contact opening 11 is provided in the silicon oxide film 10, and an aluminum electrode 12 is selectively provided to connect to the N+ type diffusion region 9 in the opening 11, thereby forming a semiconductor device.

Note that the gate electrode 4 may have a laminated structure of a polycrystalline silicon layer and a high melting point metal silicide layer instead of the polycrystalline silicon layer, and a silicon oxide film containing phosphorus and boron may be used instead of the PSG film 8. Alternatively, arsenic may be used instead of phosphorus as an impurity atom for forming the N-type diffusion region 6.

〔Effect of the invention〕

As explained above, the present invention provides a polycrystalline silicon film and a PSG film on the surface including the gate electrode covered with the silicon oxide film.
To use the polycrystalline silicon film as an etching stopper when forming films by sequentially stacking them and removing the PSG film from other parts while leaving only the PSG film on the sidewalls of the gate electrode by anisotropic etching of the entire surface. This prevents the surface of the element forming area from being exposed to the etching atmosphere.
This has the effect of preventing the occurrence of defects in the element formation region and realizing a semiconductor device with improved reliability.

[Brief explanation of the drawing]

1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention, and FIG. 2(a)
) to (C) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... Gate electrode, 5...
・Silicon oxide film, 6... N- type diffusion region, 7...
Polycrystalline silicon film, 8...PSG film, 9...N+ type diffusion region, 10...silicon oxide film, 11...opening portion, 12...aluminum electrode, 13.14... Silicon oxide film.

Claims (1)

[Claims] a step of providing a field insulating film for partitioning an element formation region on the main surface of a semiconductor substrate of one conductivity type, forming a gate insulating film on the surface of the element formation region, and selectively forming a gate electrode on the gate insulating film; a step of forming an insulating film covering the gate electrode; and a step of ion-implanting an impurity using the gate electrode and the field insulating film as a mask to form a low concentration of a reverse conductivity type in the element formation region in a self-aligned manner. a step of forming a diffusion region, a step of sequentially depositing a polycrystalline silicon film and an impurity-doped silicon oxide film on the surface including the gate electrode, and anisotropically etching the entire surface to remove the oxide only on the sidewalls of the gate. a step of leaving a silicon film, and ion implantation of impurities using the gate electrode, the silicon oxide film, and the field insulating film as masks to form a high concentration diffusion region connected to the low concentration diffusion region in the element formation region. A method for manufacturing a semiconductor device, comprising the steps of: