JP2968548B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device such as an MIS transistor and a bipolar transistor and a method for manufacturing the same.

(Prior Art) In recent years, large-scale integrated circuits (LSIs) are frequently used in important parts of computers and communication devices. These LSIs are formed by integrating a large number of field effect transistors (FETs) on a semiconductor substrate of several mm square. Recently, this L
SIs are becoming more integrated to fulfill a wide variety of functions.

 A conventional method for manufacturing a MOSFET will be described with reference to FIG.

First, a polycrystalline silicon film (205 ₁ ) is placed on a thin thermal oxide film (204 ₁ ) (gate oxide film) on an N-type silicon substrate (201) on which a P well region (202) and a field oxide film (203) are formed. ) Is formed. Further, the polycrystalline silicon film (205 ₁ ) is provided with a P-type portion into which boron is introduced and an N-type portion into which phosphorus or arsenic is introduced (FIG. 9A).

Next, gate electrodes (205 ₂ ) and (205 ₃ ) are formed through a photolithography step and an anisotropic etching step. Thereafter, the exposed surface is oxidized to form a thin thermal oxide film (204 ₂ ) on the surface of the gate electrodes (205 ₂ ) (205 ₃ ). Further, by introducing boron into the PMOS region and phosphorus or arsenic into the NMOS region from above the gate electrode to the surface of the substrate (101), P-type and N-type source / drain regions ( 206 ₁ ) (206 ₂ ) (207 ₁ ) (207 ₂ ) are formed (FIG. 9 (b)).

After that, an insulating film (208) having a laminated structure of an oxide film and a BPSG film is deposited using a CVD method, and the insulating film on the gate electrode is planarized by performing a heat treatment in a steam atmosphere, and then contacting a desired region. A hole is provided to form an electrode wiring (210) (FIG. 9 (c)). Then, if necessary, a step of depositing a plasma CVD oxide film at a reasonable temperature on the wiring, providing a via hole in a desired region, and forming an upper wiring is repeated. Finally, a passivation film of a laminated structure of a plasma Si ₃ N ₄ and PSG over the uppermost wiring (20
After covering in step 9), a pad portion (not shown) is formed. Through these steps, the MOSFET is completed. However, such a MOSFET has the following problems.
(1) In a P ⁺ poly gate PMOS, when the gate oxide film becomes thinner, boron diffuses from the gate electrode through the gate oxide film to the substrate side and changes the impurity concentration in the channel region. Controllability is poor, and in some cases, the characteristics do not cut off. As a result, there is a problem that the gate oxide film thickness cannot be reduced according to the scaling rule.

(2) Smoothing the BPSG film at a low temperature requires a heating step in a steam atmosphere. However, when heat treatment for smoothing is performed in a steam atmosphere, the gate electrode and the diffusion layer are oxidized, and in particular, a silicide film is formed. In the case of using, the unevenness of the film surface becomes severe and deteriorates the film quality, and the impurities in the gate electrode and the diffusion layer are sucked out to the interlayer insulating film side, thereby increasing the sheet resistance of the gate electrode and the diffusion layer. I was

(1) There was a method of depositing on or under the BPSG film as a means for solving the LPCVD the Si ₃ N ₄ film (2), or cracks within the Si ₃ N ₄ film during the smoothing, Si ₃ N ₄ film and a BPSG
Stress may be applied due to the difference in the coefficient of thermal expansion between the film and the film, which may cause deterioration in device characteristics and reliability.

(Problems to be Solved by the Invention) In the conventional method of manufacturing a MOS transistor, the phenomenon of penetration of boron from a P ⁺ polysilicon gate, absorption of impurities from a gate electrode or a diffusion layer, and oxidation of the gate electrode and the diffusion layer. As a result, the film quality deteriorates, the threshold voltage becomes unstable due to an increase in bird's beak at the gate electrode edge, and the parasitic resistance increases.

The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device having good controllability of a threshold voltage and capable of easily forming a semiconductor device having a small parasitic resistance, and a method for manufacturing the same. I do.

[Constitution of the Invention] (Means for Solving the Problems) The present invention has been made in view of the above circumstances, and a first invention is directed to a transistor formed on a surface portion of a semiconductor substrate and a part of the transistor. A semiconductor device comprising: an interlayer film containing oxygen and nitrogen formed on a conductive film containing impurities, which forms: and a hydrogen-containing insulating film formed on the interlayer film. Things.

According to a second aspect of the present invention, a step of forming a transistor on a surface portion of a semiconductor substrate, a step of forming an interlayer film containing oxygen and nitrogen on a conductive film containing impurities forming a part of the transistor, Forming a hydrogen-containing insulating film on the interlayer film.

(Operation) According to the present invention, when a plasma nitride film is formed as a passivation film or in a water vapor atmosphere excellent in flattening, reflow is performed by including nitrogen serving as a diffusion barrier in an interlayer film on the device. H group, OH group and O
Can shut out radical invasion. Therefore, deterioration of the film quality due to oxidation of the conductive film or the diffusion layer containing impurities such as the gate electrode or the emitter electrode, the phenomenon of sucking out the impurities from the gate electrode or the diffusion layer, and the occurrence of bird's beak at the gate electrode edge are suppressed. As a result, a high-performance semiconductor device having a small parasitic resistance can be easily formed.

In addition, before forming a film in which hydrogen is likely to be generated after the wiring is formed, a nitrogen-containing oxide film that is difficult to pass through hydrogen is formed, so that a P ⁺ polysilicon gate caused by intrusion of hydrogen into the gate electrode is formed. The problem of controllability of the threshold voltage of the PMOSFET can be solved.

(Examples) Details of the present invention will be described using examples.

First Embodiment A method for manufacturing a field effect transistor according to a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (h).

First, a P-type well region (2) and a field oxide film (3) for element isolation are formed on the surface of, for example, an N-type single crystal silicon substrate (1). to form a thermal oxide film (4 _1). Next, LPCVD (Low Pressure Chemical Vapor Deposi
The polycrystalline silicon film (5 ₁ ) is deposited for about 3500Å by the method of (tion). The next (FIG. 1 (a)), the resist Makusu (6 ₁₎ is formed, a polycrystalline silicon film (5 ₁₎ a dose of boron fluoride ions in 3E15 cm ^-2 as a mask, the accelerating voltage 30KeV P ⁺ -type polycrystalline silicon by implanting in condition (5 ₂₎ forming a (FIG. 1 (b)).

After further removing the mask _(61), a resist mask (6 ₂₎ again, a dose of impurities e.g., phosphorus ions into the polycrystalline silicon film (5 ₁₎ as a mask (6 ₂₎
3E15 cm ^-2, this time by implanting in the conditions of an acceleration voltage 30KeV to form an N ⁺ polysilicon (5 ₃₎ (FIG. 1 (c)).

After that, the resist masks (6 ₂₎ is removed, again to form a mask for forming an electrode subjected to patterning on the removal surface, the unnecessary polysilicon film from above the mask, for example, by anisotropic etching By removing the N ⁺ -type gate electrode as a conductive film containing impurities ( ₅₅ )
And forming the P ⁺ -type gate electrode _(4). (4 ₂₎ is a gate oxide film of each of the gate electrode (FIG. 1 (d)).

Then, for example, in an oxygen atmosphere, and subjected to dry oxidation at 800 ° C., the gate electrodes (5 ₄₎ (5 ₅₎ and on the exposed substrate (1), 80 Å heat of about the P-well region (2) the surface forming an oxide film (4 _3). In the following description, this film is referred to as a post-oxide film. If the post-oxide film is too thick, bird's beaks will be formed under the electrode and the shape of the gate electrode will be deteriorated. When the bird's beak is extremely large, the gate oxide film on the electrode edge is effectively thickened, so that the threshold voltage of the transistor at the electrode edge increases. As a result, the gate bird's beak region leads to an increase in the parasitic resistance, and deteriorates the performance of the transistor. This is more noticeable in an LDD (Lightly Doped Drain) structure, a GDD (Graded Diffused Drain) structure, and the like. Forming a P ⁺ -type gate electrode through the post oxide film (5 ₄₎ by introducing boron into the substrate (1) on the mask P ⁺ -type source and drain regions (7 ₁₎ (8 _1). Similarly, to form a by introducing phosphorus N ⁺ -type gate electrode (5 ₅₎ in a self-aligned manner N ⁺ -type source and drain regions (7 ₂₎ (8 ₂₎ on a P-well region (2) (FIG. 1 (e)).

Next, an oxide film (9) is formed as a first interlayer insulating film by CVD (Chemical Vapor Deposition), for example, to a thickness of 2000 Å.
It is deposited (FIG. 1 (f)).

After the oxide film (9) forming step, the atmosphere is heated at 1100 ° C. for 60 minutes in an atmosphere containing a nitrogen-containing gas, for example, an ammonia gas.
The lamp is heated for 2 seconds to form an oxide film (10) containing nitrogen (FIG. 1 (g)).

Thereafter, a BPSG (Boro Phospho Silicate Glass) film (11) containing boron and phosphorus is formed as a second interlayer insulating film on the entire surface, and subsequently, in a POCl ₃ atmosphere or a nitrogen or argon atmosphere, 3 at 850 ° C
By performing the heat treatment for 0 minutes, the second interlayer insulating film is fluidized. Through the above such processes, the gate electrode ₍₄₎
(5 ₅₎ on after planarizing the interlayer insulating film, a gate electrode by photolithography method, a source, and a contact hole (12) on the drain region, an aluminum alloy as a wiring material, for example, Al-Si-Cu The wiring (13) is formed by depositing by sputtering and patterning. Finally, on the wiring passivation film, for example a plasma nitride layer (14 ₁₎ and PSG (Phospho S
After covering with a laminated film (14) of an ilicate glass) film (14 ₂ ), a pad portion (not shown) is opened (FIG. 1 (h)).

This plasma nitride film (14 ₁ ) is generated in an atmosphere of SiH ₄ and NH ₄ , and at this time, hydrogen atoms are taken into this plasma nitride film (14 ₁ ). Through the above-described steps, the NMOSFET and the PMOSFET can be formed on the same substrate. Subthreshold for PMOSFET
FIG. 2 shows the results of evaluating the characteristics.

In the conventional example, since the first interlayer insulating film (9) does not contain nitrogen, hydrogen atoms generated when a plasma nitride film as a passivation film is formed diffuse into the gate electrode (5), and the hydrogen atoms are diffused into the gate electrode (5). As a result, boron in the gate electrode (5) diffuses toward the substrate, forming a P-type layer on the substrate surface. Therefore, the channel region cannot be controlled by the gate voltage as shown in FIG. On the other hand, in the present embodiment, the first
Since the interlayer insulating film (10) contains nitrogen, diffusion of hydrogen atoms to the gate electrode (5) is suppressed, and diffusion of boron in the gate electrode (5) to the substrate side can also be suppressed. Therefore, good cut-off characteristics are obtained as shown in FIG. The drain leakage current in the region where the gate voltage is positive as shown in FIG. 2 (b) is a phenomenon that is observed when the gate oxide film is thinned, and the electric field intensity near the drain is reduced by using an LDD structure or the like. It has been confirmed that it can be reduced by This is not an essential problem in the present invention. As described above, even when the gate insulating film is thin, the PMOSFET can be formed with a desired threshold voltage. In this embodiment, a single-layer wiring has been described, but a multilayer wiring may be used if necessary. In other words, after forming the first layer wiring, the plasma CV is applied to the wiring at a reasonable low temperature.
A step of depositing a D oxide film, providing a wiring lead-out hole (via hole) with the first layer wiring in a desired region, and forming an upper layer wiring is repeated. Finally, a passivation film is formed on the uppermost layer wiring. The pad portion (not shown) may be opened after the cover. Further, in this embodiment, after forming an oxide film (10) containing nitrogen, BPSG (Boro Phospho Silo) containing boron and phosphorus is formed as a second interlayer insulating film on the entire surface.
icate Glass) film was formed, the second interlayer insulating film was fluidized by heat treatment, and the interlayer insulating film on the gate electrode was flattened. After this step, a resist etch back step was added as necessary. Alternatively, instead of fluidizing by heat treatment, this may be replaced by a flattening step using a resist etch-back technique.

LPCVD Si ₃ N ₄ described in the last part (prior art)
The problems caused by the cracks in the deposited Si ₃ N ₄ film when the film was deposited and the stress caused by the difference in the coefficient of thermal expansion could be solved.
This rapidly composition as the film quality itself deposited film SiO ₂
This is because the composition does not change from Si ₃ N ₄ to the composition SiO _x N _γ but continuously.

In this embodiment, the heat treatment for planarizing the second interlayer film may be performed in a steam atmosphere. At this time, hydrogen atoms in the water vapor atmosphere are taken into the second interlayer film.

FIG. 4 shows an IV characteristic of an NMOSFET manufactured by a conventional technique using reflow in a steam atmosphere and a comparison with that of the present invention.

In the conventional example (lower curve in FIG. 4), it can be seen that the rise of the linear region is slow, and the difference is small where the voltage applied to the source and drain is high. Such a remarkable difference was not observed at a place where the gate length was long. The above can be explained by the channel resistance and the parasitic resistance in series with the source and the drain. That is, when the gate length is long, the parasitic resistance can be ignored compared to the channel resistance. However, when the gate length becomes short and the parasitic resistance becomes large enough to be compared with the channel resistance, the difference shown in FIG. It is becoming. At this time, the sheet resistance of the diffusion layer and the sheet resistance of the gate electrode were increased by about 8 times and about 2 times, respectively, in the conventional example. These can be explained by deterioration of the film quality due to oxidation of the diffusion layer and the gate electrode, bird's beak formed at the gate edge, and outward diffusion of impurities. Further, it has been found that even when reflow in a steam atmosphere is used in the present invention, the electrical characteristics are not inferior to those of N ₂ and POCl ₃ . FIG. 3 shows the shape of the gate edge and the movement of boron ions in the conventional example and the present invention. FIG. 1A shows a conventional example, and FIG. 1B shows the present invention.

Second Embodiment An example in which the first embodiment is applied to a bipolar transistor will be described with reference to FIGS. 5 (a) to 5 (g).

A wafer is used in which an n-type epitaxial layer (103) is formed on a P-type silicon substrate (101) via an n ⁺ -type buried layer (102). A P-type layer (104) serving as a channel stopper is formed in an element isolation region of the wafer, and an oxide film (105) is formed by selective oxidation. After forming a thin oxide film (106) on the surface of the device region of this wafer, a nitride film (Si ₃ N ₄ film) (1
07), followed by the first polycrystalline silicon film (108)
Is deposited. Unnecessary portions on the element isolation region in the first polycrystalline silicon film (108) are changed to a thermal oxide film (109) by thermal oxidation. Next, the first polycrystalline silicon film (1
08), boron is ion-implanted and added, and the first polycrystalline silicon film (108) on the emitter formation region is etched by photoetching to provide an opening. (FIG. 5 (a)).

Thereafter, heat treatment is performed in an oxidizing atmosphere to form a thermal oxide film (110) on the surface of the polycrystalline silicon film (108). Using the oxide film (110) as a mask, the nitride film (107) in the opening is heated with phosphorus. Etching is removed with an acid aqueous solution. Then, the exposed thermal oxide film (106) is removed with an NH ₄ F aqueous solution to expose the wafer surface. At this time, by intentionally over-etching the etching of the nitride film (107) in the opening,
An overhang portion (111) is formed to expose a part of the first polycrystalline silicon film (108) (FIG. 5 (b)).

Next, a second polycrystalline silicon film (112) is deposited on the entire surface to fill the cavity below the overhang portion (111), and then the second polycrystalline silicon is etched to form an oxide film (110) and an opening. To expose the wafer surface (No. 5)
Figure (c).

Next, an oxide film (113) is formed on the exposed wafer surface and side surfaces of the polycrystalline silicon film by thermal oxidation. At this time, boron previously doped in the first polycrystalline silicon film (108) is diffused into the wafer surface through the second polycrystalline silicon film (112) of the overhang portion (111), and P An external base layer (114) for the mold is formed. next,
The base layer (11
5) Form. Next, a CVD insulating film (116) and a third polycrystalline silicon film (117) are deposited, and these are etched by reactive ion etching to leave them only on the side walls of the opening. Using 117) as a mask, the thermal oxide film on the wafer surface in the opening is removed. Then, a fourth polycrystalline silicon film (118) in which arsenic is ion-implanted at a high concentration is deposited (FIG. 5 (d)).

Thereafter, an oxide film (119) is formed as a first interlayer insulating film, for example, by CVD (Chemical Vapor Deposition) method.
0 ° is deposited (FIG. 5 (e)).

After the oxide film (119) forming step, at 1200 ° C. in an atmosphere containing a nitrogen-containing gas, for example, an ammonia gas.
Oxide film containing nitrogen (120) by lamp heating for 60 seconds
Is formed and arsenic is diffused to form an N-type emitter layer (123) (FIG. 5 (f)).

Next, after a bias sputtering film (121) is deposited as a second interlayer insulating film on the entire surface, the interlayer insulating film on the emitter electrode as a conductive film containing impurities is planarized, and the emitter, base, A contact hole is opened on the collector region, and an aluminum alloy, for example, Al—Si—Cu is deposited as a wiring material by a sputtering method and patterned to form a wiring (122) (FIG. 5 (g)).

In this figure, only the emitter electrode is shown. Finally, passivation film such as plasma nitride film and PSG
Pad part (not shown) after covered with film stack (124)
Open. An NPN transistor can be formed through the above steps. In this embodiment, a single-layer wiring has been described, but a multilayer wiring may be used if necessary. That is, after forming the first layer wiring, a process of depositing a plasma CVD oxide film, providing a wiring lead-out port (via hole) with the first layer wiring in a desired region, and further forming an upper layer wiring is repeated. A pad (not shown) may be opened after the uppermost wiring is covered with a passivation film. In this embodiment, after forming an oxide film containing nitrogen (120), a bias sputtered oxide film is formed as a second interlayer insulating film on the entire surface, and the second interlayer insulating film is fluidized by heat treatment to form an electrode. Although the upper interlayer insulating film is planarized, a resist etch-back step may be added after this step, if necessary.

The first and second polycrystalline silicon films (108) and (112) are used as base electrodes, and the fourth polycrystalline silicon film (11
8) is used as an emitter electrode.

The bipolar transistor manufactured as described above has an external base layer (114) and P ⁺ connected to the external base.
The absorption of boron from the polycrystalline silicon (108) (outward diffusion to the oxide film (110)) is suppressed. As a result, the base resistance can be reduced and excellent high-frequency characteristics can be obtained.

In this embodiment, a two-layer polycrystalline silicon process has been described as an example, but a one-layer polycrystalline silicon process may be used.
A process in which the emitter and the base are not formed in a self-aligned manner may be used.

In the first and second embodiments, an oxide film is used as a gate insulating film. However, other materials such as a nitride film or a TaO ₂ O ₅ film, and a stacked structure of these and an oxide film are used. However, the present invention can be applied to other MIS type FETs other than the MOS type FET.

In the first and second embodiments, the first interlayer film is nitrided by high-temperature, short-time thermal nitridation by lamp annealing. However, other methods, such as implantation of ions containing nitrogen (dose amount: 1E14 cm), may be used. ^-2 to 1E17cm ^-2 ). In the above embodiment, the interlayer insulating film on the gate or the emitter electrode has a different composition.
Although the description has been made of the case of being composed of three layers, an oxide film having the same film quality may be used. Unless a plasma-based film that easily generates hydrogen is used, an SOG (Spin On Glass) film and an LPD (Liquid
d Phase Deposition) film or the like may be used. Also,
These films may be combined into three or more layers. In the above embodiment, the extraction electrodes including the gate and the emitter are formed of a polycrystalline silicon film, but may be formed of a metal, for example, a laminated film of a high melting point metal or a compound film of a high melting point metal and silicon. .

In a third embodiment the first embodiment, but was contained nitrogen in the oxide film (10) may be the nitrogen is contained in the post-oxidation film (4 ₃₎ instead. That is, to form a post-oxide film (4 ₃₎ in FIG. 1 (e). Next, lamp heating is performed at a temperature of 1050 ° C. for 60 seconds in an atmosphere containing a nitrogen-containing gas such as an ammonia gas to form a nitrogen-containing post-oxide film.

Further, the surface of the post-oxide film may be oxidized again by performing a heat treatment at a temperature of 1050 ° C. for 60 seconds in an oxygen atmosphere. As a result, the post-oxide film has a lower nitrogen concentration in the vicinity of the surface, and has a denser distribution nearer to the gate electrode. Through these steps, the same effects as in the first embodiment can be obtained.

Fourth Embodiment A fourth embodiment of the present invention will be described. This embodiment is different from the first embodiment in that a post-oxide film containing nitrogen and fluorine is used instead of the post-oxide film containing nitrogen formed in the third embodiment. For example, a method of including fluorine in the post-oxide film is to perform heat treatment in a gas containing fluorine and nitrogen such as NF ₃ instead of ammonia gas, or to introduce and introduce fluorine by ion implantation after the formation of the post-oxide film. Subsequently, it can be formed by lamp heating in an ammonia atmosphere.

By using the post-oxide film containing fluorine and nitrogen in this way, the following effects can be obtained in addition to the effects obtained in the third embodiment. That is, by introducing fluorine, dangling bonds (dangrid) of silicon atoms at the interface between the silicon substrate (including the source / drain regions) and the gate oxide film.
ng bond) is filled, and the breakdown voltage and reliability of the FET are further improved.

The introduction of fluorine by ion implantation may be performed before the post-oxide film is formed, after the post-oxide film is formed, after the post-oxide film is nitrided, or after the post-oxidation film containing nitrogen is re-oxidized.

It has been found that the present invention is not limited to the above-described embodiment, but may be made as follows.

Although ammonia gas was used for nitriding, another gas containing nitrogen atoms, such as N ₂ , may be used. Although NF ₃ is used as the gas containing nitrogen and fluorine atoms, another gas containing fluorine may be used.

Thermal nitridation was used to nitride the post-oxide film. Other methods such as plasma nitridation and LPCVD (Low-
Pressure chemical vapor deposition) can be used to deposit a silicon nitride film (Si ₃ N ₄ ).

Although an oxide film is used for the gate insulating film, another material such as a nitride film may be used.
It can be applied to other MIS type FETs other than the type FET.

Although the gate electrode is formed of polycrystalline silicon, it may be formed of a metal, for example, a laminated film of a high melting point metal or a compound film of a high melting point metal and silicon.

Although silicon was used for the substrate, other semiconductors such as Ge, GaAs, and InP may be used.

Fifth Embodiment In the first embodiment, the oxide film (10) contains nitrogen, but in the present embodiment, the gate insulating film contains nitrogen.
That is, after forming the thermal oxide film (4 ₁ ) in the first embodiment,
By performing a lamp heat treatment at 1050 ° C. for 60 seconds in an ammonia atmosphere, the concentration of nitrogen atoms (atomic concentration) within an area of 10 mm from the interface between the silicon substrate and the gate insulating film containing nitrogen is 1 to 10 atom · on average. % Of the gate insulating film is formed.

FIG. 6 is a concentration profile (Auger analysis result) of silicon, oxygen and nitrogen of the gate insulating film manufactured according to this embodiment.

This embodiment has the following effects. That is, in a conventional semiconductor device obtained by diluting and oxidizing a silicon substrate with an HCl in a gate insulating film, as miniaturization progresses, the influence of surface roughness scattering in a high electric field portion increases, and there is a problem that mobility is reduced. This problem indicates that it is difficult to realize a high-speed device.

In contrast, the present invention does not have such a problem. This will be specifically described below.

FIG. 7 shows the mobility of a MOSFET manufactured using the present invention in comparison with that of a MOSFET manufactured using the conventional technique. FIGS. 7A and 7B correspond to N-channel and P-channel MOSFETs, respectively.

FIG. 8 shows the mobility on the high electric field side with respect to the concentration of nitrogen atoms (atomic concentration) with respect to silicon, oxygen and nitrogen atoms within a range of 10 ° from the interface between the silicon substrate and the gate insulating film containing nitrogen. FIGS. 8A and 8B correspond to N-channel and P-channel MOSFETs, respectively.

From the above figures, on the high electric field side, the MOSFET using the present invention is:
It can be seen that mobility increases significantly in the N channel and decreases in the P channel. According to the present invention, the concentration of nitrogen atoms (atomic concentration) at the interface between the silicon substrate and the gate insulating film containing nitrogen is in the range of 10 ° and the average of 1 to 10 atom ·% with respect to silicon, oxygen and nitrogen atoms. Therefore, surface roughness scattering caused by nitrogen atoms is reduced in the N channel and increased in the P channel as compared with the case where an oxide film is used as a gate insulating film.

The present invention is not limited to the above embodiment, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.

Further, the present invention can be applied to the manufacture of other semiconductor devices such as BICMOS.

[Effects of the Invention] As described above, according to the present invention, since nitrogen is contained in the interlayer insulating film, the post-oxide film, etc., boron penetrates from the P ⁺ polysilicon gate and the gate electrode or the diffusion layer does not. It is possible to prevent the impurity draining phenomenon, the instability of the threshold voltage due to the increase of the bird's beak at the gate electrode edge, the increase of the parasitic resistance, and the like, and it is possible to obtain a device excellent in high-speed operation with good controllability.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing an embodiment (MOSFET) of the present invention,
FIG. 2 is a diagram comparing another embodiment with a conventional example, FIG. 3 is a diagram illustrating the present invention, FIG. 4 is a diagram illustrating the effect of the present invention, and FIG. 5 is a second embodiment ( Bipolar transistor)
6, 7 and 8 are views for explaining the fifth embodiment, and FIG. 9 is a process cross-sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1 ... N-type single crystal silicon substrate, 2 ... P-type well region, 3 ... Device isolation region, 4 ... Gate insulating film, 5 ... Polycrystalline silicon film, 6 ... Resist film 7, 8 ... Source and drain regions 9 oxide film, 10 silicon oxide film containing nitrogen, 11 BPSG film, 12 contacts, 13 wiring, 14 passivation film, 101 p-type silicon substrate, 102 buried layer, 103 N-type epitaxial layer, 104 channel stopper, 105 oxide film, 106 thin oxide film, 107 nitride film, 108 polycrystalline silicon film, 109 ... Oxide film, 110 ... Oxide film, 111 ... Overhang portion, 112 ... Polycrystalline silicon film, 113 ... Thermal oxide film, 114 ... External base layer, 115 ... P-type diffusion layer (internal base) 116 116 CVD insulating film 117 117 Polycrystalline silicon film 118 Polycrystalline silicon film 119 Oxide film 120 Nitrogen Included oxide film, 121: Bias sputtered oxide film, 122: Aluminum wiring, 123: Emitter layer, 124: Passivation film, 201: N-type silicon substrate, 202: P-type well region, 203: Field Oxide film, 204: gate oxide film, 205: polycrystalline silicon film, 206, 207: source / drain region, 208: insulating film, 209: passivation film, 210: electrode wiring.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/092 29/73 29/78 (72) Inventor Shinichi Takagi 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Within Toshiba Research Institute (72) Inventor Hiroshi Iwai No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Within Toshiba Research Institute Co., Ltd. (56) References JP-A-61-154171 (JP, A) JP-A-63-236357 (JP, A) JP-A-59-117133 (JP, A) JP-A-1-228135 ( JP, A) Japanese Utility Model Showa 64-13125 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21 / 318,21 / 316 H01L 29 / 73,29 / 78

Claims (8)

(57) [Claims] 1. A transistor formed on a surface portion of a semiconductor substrate, a post-oxide film formed on a conductive film containing impurities forming a part of the transistor, and a post-oxide film formed on the post-oxide film. A semiconductor device, comprising: an interlayer film formed above the conductive layer and formed of a single layer containing oxygen and nitrogen; and an insulating film containing hydrogen formed above the interlayer film. 2. The semiconductor device according to claim 1, wherein said transistor is an MIS transistor, and said conductive film forms a gate electrode. 3. The semiconductor device according to claim 1, wherein said transistor is a bipolar transistor, and said conductive film forms an emitter electrode. 4. The semiconductor device according to claim 1, wherein said interlayer film further contains fluorine. 5. A step of forming a transistor on the surface of a semiconductor substrate, a step of forming a post-oxide film on a conductive film containing impurities forming a part of the transistor, and a step of forming a post-oxidation film above the oxide film. Forming an interlayer film comprising a single layer containing oxygen and nitrogen above the conductive film, and forming an insulating film containing hydrogen above the interlayer film. Device manufacturing method. 6. A step of forming a transistor on a surface portion of a semiconductor substrate, a step of forming an oxide film above a conductive film forming a part of the transistor and containing impurities, and adding nitrogen to the oxide film. A method of manufacturing a semiconductor device, comprising: introducing a hydrogen-containing insulating film on an oxide film into which nitrogen has been introduced. 7. The method of manufacturing a semiconductor device according to claim 6, wherein said means for introducing nitrogen is heat treatment in an atmosphere containing nitrogen atoms. 8. The method according to claim 5, wherein the hydrogen-containing insulating film is flattened by performing a heat treatment in a steam atmosphere.