JPH04245442A - Manufacture of ldd transistor - Google Patents

Abstract

PURPOSE:To eliminate a need of tilting an ion beam, to make a source and a drain easily symmetric and to prevent an enhanced diffusion by a method wherein an ion implantation operation is performed in a state that an Si3N4 film has been applied and a heat treatment is executed in an oxidizing atmosphere. CONSTITUTION:A gate electrode 14 is formed; Si3N4 is deposited on the whole surface of a semiconductor substrate 11 an Si3N4 film 15 is formed; P<-> ions are implanted vertically into the semiconductor substrate 11 by making use of the gate electrode 14 as a mask; an N<-> source-drain 16 is formed. In succession, an SiO2 film is formed; an anisotropic etching operation is executed to it; a sidewall spacer 17 is formed. As<+> ions are implanted vertically into the semiconductor substrate 11 by making use of the gate electrode 14 and the sidewall spacer 17 as a mask; an N<+> source-drain 18 is formed. After that, a heat treatment is executed in an oxidizing atmosphere in a state that the Si3N4 film 15 has been applied.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an LDD transistor, and more particularly, to prevention of channeling during formation of a source/drain and prevention of accelerated diffusion during diffusion of a source/drain.

0002

2. Description of the Related Art Generally, in MOS transistors whose channel length is miniaturized to about 1 μm or less, MOS transistors with a so-called LDD structure (hereinafter referred to as "LDD transistors") are used to reduce hot carrier effects. . Conventionally, to manufacture an LDD transistor, as shown in Fig. 5, sidewall spacers (1) made of SiO2 or Si3N4 are used and ion implantation is performed to connect the low concentration source/drain (2) and the high concentration source/drain. It formed a drain (3). In order to prevent channeling during such ion implantation, the angle of incidence of the ion beam is inclined by about 7 degrees from the vertical direction.

[0003] This technique is described, for example, on pages 234 to 237 of IEDM Technical Digest (1988 edition).

0004

However, when the ion beam is tilted, the left-right symmetry of the source and drain deteriorates, and the electrical characteristics also become asymmetrical. In addition, when the sidewall spacer (1) is formed of SiO2, if heat treatment is performed in an oxidizing atmosphere, oxygen will diffuse into the sidewall spacer (1), forming a low concentration source/drain (2). It reaches the surface and the lightly doped source/drain (2) undergoes accelerated diffusion. As a result, there is a problem that the effective channel length of the transistor becomes shorter than necessary.

Furthermore, when the sidewall spacer (1) is formed of Si3N4, cracks may occur in the sidewall spacer (1) due to the stress of Si3N4, or leakage current may occur between the source/drain and the semiconductor substrate. may occur.

[0006]

[Means for Solving the Problems] The present invention has been made in view of the above-mentioned conventional problems.After forming a gate electrode, the entire surface of a semiconductor substrate is covered with a Si3N4 film, and the Si3N4 film is With the attached state, the source of LDD structure
It is characterized by performing an ion implantation process for drain formation and a subsequent heat treatment process in an oxidizing atmosphere.

[0007]

According to the above method, since the entire surface of the semiconductor substrate is covered with the Si3N4 film after forming the gate electrode, the Si3N4 film acts as a channeling prevention film against ion implantation. This eliminates the need to tilt the ion beam from the vertical direction in order to prevent channeling, as is the case in the prior art, making it possible to form sources and drains with good left-right symmetry.

Furthermore, during the subsequent heat treatment step in an oxidizing atmosphere, the Si3N4 film acts as an oxidation-resistant film. This makes it possible to prevent oxygen from diffusing to the surface of the semiconductor substrate and prevent the source/drain from undergoing accelerated diffusion.

[0009]

Embodiments Next, embodiments of the present invention will be described in detail with reference to FIGS. 1 to 4. First, as shown in FIG. 1, a gate oxide film (1
2) Approximately 30% polysilicon is deposited by LPCVD method through
A polysilicon layer (13) is deposited to a thickness of 0.00 Å and then doped with phosphorus.

Next, as shown in FIG. 2, a gate oxide film (1
2) and the polysilicon layer (13) by selectively performing an anisotropic etching process, the gate electrode (14
) to form. Then, as shown in Fig. 3, Si3N4 is
Si3N is deposited on the entire surface of the semiconductor substrate (11) using the PCVD method.
4 and has a thickness of about 500 Å (
15), and using the gate electrode (14) as a mask, P
Accelerating voltage of approximately 60 KeV by ion implantation of + ions
, is vertically implanted into the semiconductor substrate (11) at a dose of approximately 3×10 13 /cm 2 to form an N-source/drain (16).

Here, since the Si3N4 film (15) acts as a channeling prevention film for P+ ions, there is no need to tilt the ion beam from the vertical direction in order to prevent channeling as in the conventional case, and the beam has good left-right symmetry. N-
It has the advantage of being able to form a source/drain (16). Note that if a thermal oxide film of about 200 Å is formed on the semiconductor substrate (11) before forming the Si3N4 film (15), the effect on the surface of the semiconductor substrate (11) will be reduced.
5) stress can be alleviated.

Next, as shown in FIG. 4, SiO2 was subjected to LPC
A SiO2 film is formed by depositing on the entire surface by VD method, and the S
Sidewall spacers (17) are formed by subjecting the iO2 film to anisotropic etching. Using the gate electrode (14) and sidewall spacer (17) as a mask, As+ ions are applied to the semiconductor substrate (1
1) N+ source/drain (18
) to form.

Here, the Si3N4 film (15) is similarly
Since it acts as a channeling prevention film for s+ ions, there is no need to tilt the ion beam from the vertical direction to prevent channeling as in the conventional method, and it is possible to form an N+ source/drain (18) with good left-right symmetry. It has the advantage of being able to After that, with the Si3N4 film (15) attached, a heat treatment process is performed in an oxidizing atmosphere.
. Examples of the heat treatment process include a source/drain diffusion process (for example, 950°C O2+N2), a BPSG film flow process (for example, 900°C O2), and the like. Here Si
Since the 3N4 film (15) has a property of not allowing oxygen in the oxidizing atmosphere to pass through, it can prevent accelerated diffusion of the source and drain due to the influence of oxygen.

In particular, since accelerated diffusion of the N-source/drain (16) is prevented, there is an advantage that the controllability of the effective channel length of the LDD transistor can be improved. Furthermore, the Si3N4 film (15) is formed with a relatively thin film thickness of about 500 Å, and the sidewall spacer (17) is formed with a relatively thin film thickness of about 500 Å.
) is made of SiO2, it also has the advantage that the influence of stress can be reduced compared to the conventional case in which the entire sidewall spacer is made of Si3N4.

[0015]

As explained above, according to the present invention, there is no need to tilt the ion beam from the vertical direction in order to prevent channeling as in the conventional method, so that N-source/drain (N-source/drain) with good bilateral symmetry can be obtained. 16) and N+ source・
A drain (18) can be easily formed.

Furthermore, according to the present invention, accelerated diffusion of the N- source/drain (16) and N+ source/drain (18) due to the influence of oxygen is prevented, and in particular, controllability of the effective channel length of the LDD transistor is improved. It has the effect of

[Brief explanation of the drawing]

FIG. 1 is a first cross-sectional view according to an embodiment of the present invention.

FIG. 2 is a second sectional view according to an embodiment of the present invention.

FIG. 3 is a third sectional view according to an embodiment of the present invention.

FIG. 4 is a fourth sectional view according to the embodiment of the present invention.

FIG. 5 is a sectional view of a conventional example.

Claims (2)

[Claims] 1. A step of sequentially forming a gate insulating film and a conductive layer on a semiconductor substrate of one conductivity type, and a step of selectively performing anisotropic etching treatment on the conductive layer to form a gate electrode, After forming a silicon nitride film on the entire surface of the semiconductor substrate, using the gate electrode as a mask, first impurity ions are implanted into the semiconductor substrate by an ion implantation method to form a low concentration source/drain of opposite conductivity type. After forming a sidewall spacer made of SiO2 on the sidewall of the gate electrode via the silicon nitride film, second impurity ions are implanted into the substrate using the gate electrode and the sidewall spacer as a mask. 1. A method for manufacturing an LDD transistor, comprising a step of implanting a high concentration source/drain of opposite conductivity type, and a heat treatment step in an oxidizing atmosphere. 2. Claim 1, wherein the first and second impurity ions are phosphorus ions and arsenic ions.
A method of manufacturing the LDD transistor described above.