JPS6126264A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the manufacturing process and contrive to improve the accuracy and reproducibility by a method wherein the part of lower concentration and that of higher concentration are formed in the same semiconductor region by varying the dosage of impurity ions. CONSTITUTION:An oxide film 102 is formed on a p type Si substrate 101. Successively, a single crystal Si layer 103 is grown and an oxide film 104 is formed thereon. Further, a poly Si gate 105 is formed on the film 104. Next, impurity ions 107 of As or the like are implanted by the use of the gate 105 as a mask, thus forming effective source-drain regions 108 and 109. Then, impurity ions are implanted by avoiding the neighborhood of the gate 106, resulting in the formation of source-drain regions 111 and 112 of high concentration. When ion implantation is thus finished, finally high-seat-resistant regions 108 and 109 and low- seat-resistant regions 111 and 112 are formed by heat treatment. In such a manner, the field intensity of a MIS type transistor can be inhibited and its micro fabrication can be attained without the need of a spacer and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a concentration difference is created in the same semiconductor region by changing the amount of impurity ions implanted.

The present invention is applied, for example, to a method of manufacturing a semiconductor device such as an MIS transistor.

[Prior Art] In recent years, advances in electron beam lithography, ion lithography, and the like have made it possible to manufacture extremely fine and high-performance semiconductor devices, but various problems have also appeared with miniaturization.

Hereinafter, the case of a MIS type transistor will be explained as an example.

In the case of MIS type transistors, there is a problem in that the electric field strength increases because each region is brought close to each other due to miniaturization, and the electric field strength increases to the extent that hot carriers are generated, especially in the vicinity of the drain region.

When hot carriers are generated, they are trapped in the insulating film, causing a change in the threshold voltage of the transistor, a decrease in the drain breakdown voltage, etc., and greatly reducing the reliability of the transistor.

In order to suppress the increase in electric field strength that causes such problems, the impurity concentration in the source and drain regions near the gate is lowered to expand the depletion layer toward each region.
in) structure is usually adopted. The LDD structure is formed of a lightly doped, shallow semiconductor region and a highly doped, deep semiconductor region.

FIG. 3 shows a conventional example of a method for manufacturing a semiconductor device having an LDD structure.

In FIG. 3(&), an oxide film 2 is formed on a semiconductor substrate l, and a gate metal 3 is further formed thereon. and,
Impurity ions 4 are implanted by an ion implantation method using the gate metal 3 as a mask, and a shallow, low concentration effective source region 5 and effective drain region 6 are formed in a self-aligned manner.

Next, as shown in FIG. 3(b), the gate metal 3
A spacer 7 is provided on the side wall of.

Then, as shown in FIG. 3(C), the gate metal 3
Using the and spacer 7 as a mask, impurity ions 4 are implanted at a higher acceleration voltage than the previous time to form a highly concentrated and deep source region 8 and drain region 9.

Such a conventional method allows miniaturization of transistors because the effective lengths of the effective source region 5 and the effective drain region 6 are determined by the spacer 7.

However, there are problems in that a process for forming the spacer 7 is required and the reproducibility of the spacer is not sufficient.

FIG. 4 is a cross-sectional view of an MIS type transistor having an SOI structure manufactured by another conventional example.

In the figure, an insulating film 10 is formed inside or on the surface of a silicon substrate l by ion implantation and thermal oxidation, and a single crystal silicon layer 11 is epitaxially grown thereon. Next, a gate metal 13 is formed across the insulating film 12, and using the gate metal as a mask, source/drain regions 1 of a conductivity type opposite to that of the single crystal silicon layer 11 are formed by ion implantation.
4 and 15 are formed.

In a MIS transistor having such an SOI structure, since the thickness of the single crystal silicon layer 11 is sufficiently thin,
Source/drain regions 14 and 15 are formed in the same depth direction using the normal ion implantation method and diffusion method, so that the depths thereof are uniform. Further, the bonding does not break even when a normal ohmic contact formation method is used.

Therefore, the SOI structure is advantageous for miniaturization of MIS type transistors.

However, in this conventional example, the impurity concentration in the portions of the source-drain regions 14 and 15 close to the gate metal 13 is as high as in other portions, so an increase in electric field strength cannot be sufficiently suppressed. had.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional problems, and
The purpose is to provide a method for manufacturing a semiconductor device that can easily achieve miniaturization without increasing the number of steps.

[Summary of the Invention] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device by changing the dose of impurity ions in a portion of the source/drain region near the gate in a method for manufacturing an MIS transistor. Characterized by low impurity concentration.

[Embodiments of the invention] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment of a method for manufacturing a semiconductor device according to the present invention, and here a MOS transistor is taken up.

First, in FIG. 1(a), the impurity concentration is 1o15Cm-
3 (7) to the p-type silicon 5i (1oo) substrate lO1,
Accelerating 02 ions at a voltage of 160kV and a dose of 5X 10
Ion implantation was performed at 17 cm-2, followed by N2 annealing at 1150°C for 2 hours to a depth of ~0. An oxide film 102 having a thickness of 0.27 zm is formed at the position of IILm.

Next, the thickness is increased using the single crystal silicon remaining on the surface as a core.
A single crystal silicon layer 103 of 0.3 gm is epitaxially grown, and an oxide film 104 of ~300 gm thick is formed thereon. Furthermore, ~4000 polysilicon layers are deposited on the oxide film 104, and a polysilicon gate 105 is formed by patterning.

Next, as shown in FIG. 1(b), using the polysilicon gate 105 as a mask, an acceleration voltage of 200 kV and a dose of 1014 cm were applied using the FIB (focused ion beam) method.
In step 2, impurity ions 107 such as As are implanted to a depth of 0.
, 31Lm, sheet resistance 530Ω/mouth effective source・
Drain regions tOa and 109 are formed.

Next, as shown in FIG. 1C, impurity ions such as As are implanted at an acceleration voltage of 200 kV and a dose of 1016 cm-2, avoiding the vicinity of the polysilicon gate 106, to form a highly concentrated source-drain region. Areas 111 and 112
form.

FIG. 2 is a graph of the impurity concentration distribution in the depth direction of the effective source/drain regions 1O8 and 109 and the source/drain regions 111 and 112 formed by the above-mentioned ion drawing.

In the figure, a curve 113 shows the impurity concentration distribution of the low concentration effective source/drain regions 108 and 109,
Surface concentration ~ 3XIO15cm-3, maximum concentration 1019c
It is m-3. A curve 114 shows the impurity concentration distribution of the high concentration source/drain regions 111 and 112, with a surface concentration of ~3×1011017C and a maximum concentration of 1021cm.
-3. However, a broken line 115 in the figure represents the interface between the single crystal silicon layer 103 and the oxide film 102.

When the ion implantation is completed, heat treatment is performed at 950° C. for 30 minutes, and finally, the effective source/drain regions 108 and 109 have a depth of 0.3 m, a sheet resistance of 530 Ω/hole, and a source/drain region 111. and 11
2 has a depth of 0.3 gm and a sheet resistance of 25 Ω/mouth.

In this way, the electric field strength of the MIS type transistor can be suppressed and miniaturization can be achieved without requiring a step of forming a spacer or the like.

Note that in the first embodiment, the low concentration regions (the effective source region 108 and the effective drain region 109) are formed first, and then the high concentration regions (the source region lll and the drain region 112) are formed. Of course, the formation is not limited to this, and may be formed in the reverse order.

In addition, if a lithography device that can change the accelerating voltage and dose in steps during lithography is used, it is possible to
As shown in FIG. 2, by changing the dose amount at positions a and b, the low concentration region and the high concentration region can be formed in one drawing. In this manufacturing method,
Higher alignment accuracy can be obtained than in the first embodiment.

Furthermore, if a lithography device that can continuously change the dose amount during lithography is used, polysilicon film) 10
By continuously decreasing the dose of impurity ions 110 as it approaches 6, the effective source/drain region 1
The concentration difference between 08 and 109 and the source/drain regions 111 and 112 can be made not in a step shape but in a slope shape.

The MIS transistor manufactured in this way can suppress an increase in electric field strength compared to the transistor in the first embodiment [Fig. 1(C)], and can also improve drain breakdown voltage characteristics and threshold voltage. This has the effect of making it easier to control.

Note that methods for changing the dose amount used in the above embodiments include a method in which the lithography conditions are kept constant and the lithography ion current is varied, and a method in which the lithography ion current is kept constant and the lithography conditions are varied. The above writing conditions are the scanning speed and scanning pitch in the ion writing method using a Gaussian beam, and the irradiation area and the irradiation time in the ion writing method using a rectangular beam. In terms of ease of control, a method in which the drawing ion current is kept constant is better.

In addition, in this example, the case of SOI structure was explained, but
The present invention is not limited to this, and the present invention is also applicable to the normal structure shown in FIG. 3(C).

Furthermore, by using a lithography system that can change the ion acceleration voltage as well as the dose during lithography, the design possibilities in the depth direction will increase, and source/drain regions with an impurity concentration distribution equivalent to the LDD structure can be created. It can be formed in one step.

[Effects of the Invention] As explained in detail above, the method for manufacturing a semiconductor device according to the present invention is capable of forming a low concentration portion and a high concentration portion in the same semiconductor region by varying the amount of impurity ion implanted. , the manufacturing process can be simplified, and accuracy and reproducibility can be improved.

Furthermore, when applied to the manufacture of MIS type transistors, it is possible to suppress the increase in electric field strength near the source and drain regions, improve the reliability of the transistor, and further advance miniaturization.

[Brief explanation of the drawing]

1(a) to (C) are manufacturing process diagrams showing a first embodiment of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a concentration distribution diagram of impurity ions in this embodiment, and FIG. 3(a) ) to (C) are manufacturing process diagrams showing an example of the conventional manufacturing method, and FIG. 4 is a SO diagram for explaining another example of the conventional manufacturing method.
FIG. 3 is a cross-sectional view of an MO3 type transistor having an I structure. 101...Silicon substrate 102.104...Oxide film 103...Single crystal silicon layer 106@...Polysilicon gate 111...Source region 108...Fist effective source region 109...φ effective drain region 112 - Drain region Fig. 1 (C) Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] (1) A first semiconductor region and a second semiconductor region of opposite conductivity type in a semiconductor layer of one conductivity type, and a conductor provided with an insulating film on the surface of the semiconductor layer separated from the first and second semiconductor regions. In the method of manufacturing a semiconductor device having at least A method of manufacturing a semiconductor device characterized by increasing impurity concentration in a remote part.