JPH01143357A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress a short channel effect by providing the high concentration impurity layer of source, drain electrodes of a LDD structure in a substrate. CONSTITUTION:After a field insulating film is formed on a low concentration P-type silicon substrate and an active region is isolated, an insulating film is formed by thermal oxidizing. A polycrystalline silicon layer 10 and a polycrystalline silicon layer 11 to become a gate electrode are deposited. The gate 11 is formed by implanting phosphorus ions to low concentration impurity layers 30, 30' with the upper insulating layer as a mask. Then, arsenic is ion implanted thereby to form a high concentration impurity layer 20. Thereafter, with a spacer 41 as a mask the layer 10 is etched, and the gate 10 is formed. In this step, the overlapping amount with the layer 30 can be controlled by controlling the length of the spacer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an insulated gate field effect transistor having good electrical characteristics.

[Prior art] A structure in which a gate overlaps a source/drain electrode layer in an LDD structure is disclosed in Publication No. 60-43863.
etc. are known. These focused on the electric field between electrode layers such as source and drain and the gate electrode.

[Problems to be Solved by the Invention] The above-mentioned conventional technology does not take into consideration the electric field inside the substrate.

An object of the present invention is to obtain good electrical characteristics by utilizing the effect that overlapping gates have on the electric field inside the substrate.

[Means for Solving the Problems] The above object is achieved by providing a highly concentrated impurity layer for the source/drain electrodes of the LDD structure inside the substrate.

[Operation] The electric field at the source/drain electrodes is relaxed by the gate field effect, so the breakdown voltage is improved and the short channel effect can be suppressed.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of an element that best represents the features of the present invention.

In FIG. 1, the source/drain electrodes are formed by a lightly doped impurity layer 30, 30' and a highly doped impurity layer 20,20'. The low concentration impurity layer 30, 30' is overlapped by the second gate electrode 10 protruding from the lower side surface of the first gate electrode 11.

In the first embodiment, a field fIAs film with a thickness of about 0.2 to 1 μm is formed on a low-concentration P-type silicon substrate (or a P-well with a higher concentration than the substrate) to isolate the active region, and then thermal oxidation is performed to separate the active region. Thickness 5 that becomes the gate insulating film in the active region
An insulating film of about 50 nm is formed. A polycrystalline silicon layer 10 which will become a gate electrode is deposited by the CVD method, a layer having conductivity and which will later become a mudguard during etching, such as a thin natural oxide film, is deposited, and a polycrystalline silicon layer 11 is further deposited. The M open fiber layer is placed on top and patterned, and the gate electrode 11 is processed by using this as a mask to etch the natural oxide film that acts as an etching stopper, for example, using microwaves. In this etching, there is a two-digit difference in etching speed between the oxide film and polycrystalline silicon, so the underlying layer 10 is not etched. (FIG. 2(a)) For the gate 11, a low concentration impurity layer 30.30' is formed by ion implantation of phosphorus at a concentration of about 10@12 cm@-2 and an energy of about 40 KeV using the upper insulating layer as a mask. (Fig. 2(b)) An insulating layer of SiO2 is applied by the CVD method, and etched by equilateral etching, and by controlling the amount of etching, the gate 11 is etched.
It is possible to leave the layer that will become the spacer 41 on the side surface to a predetermined size with good control = 3-.

Using this as a mask, apply arsenic at a concentration of about 1015cm-1.
By performing ion implantation with an energy of approximately 80 KeV, a highly concentrated impurity layer 20 having a peak distribution at a depth of approximately 0.1 μm within the substrate is formed. (Second
(Figure (C)) Next, N10 is etched using the spacer 41 as a mask to process the gate 10. By controlling the spacer length in this step, the amount of overlap with the low concentration impurity N30 can be controlled.

In this example, the drain electrode 20.20' is highly biased, the gate 10.11 and the source electrode 20.30
Even when the bias voltage is set to a low bias, the low concentration impurity layer 30' on the train side is kept at a relatively low bias. Therefore, the electric field on the channel side of the high concentration impurity N2o' is also relaxed. Therefore, from the gate 10 to the high concentration impurity layer 2 of the drain electrode.
0' can be increased, and punch-through inside the substrate can be suppressed.

In this embodiment, the sides of gate 10 can be partially oxidized and isolated. Therefore, by providing a conductive layer thereon, contact can be made with the source/drain layer in a self-aligned manner.

Although the explanation was given here using an n-channel device, P
The same applies to channel devices.

As shown in FIG. 3, by providing a reverse type impurity layer 50 (for example, a high concentration layer of P-type impurity in an n-channel device) serving as a punch-through stopper on the channel side of the high-concentration impurity layer 20, the punch-through can be improved. can increase resistance to

In the above embodiment, the spacer 41 was provided in one layer, but as shown in FIG.
You can add 2.

In this case, by performing ion implantation using the spacer 42 as a mask and providing a high concentration impurity layer in the electrode layer 35, the resistance at the electrode can be lowered when contact is made.

In this embodiment as well, as shown in FIG. 5, punch-through can be further suppressed by providing a P-type impurity layer 50 in the case of an n-channel device, for example.

As shown in FIG. 6, a second gate 1 is attached to the side of the gate 10.
1, an overlapping structure can be realized. Even in this case, the short channel effect can be further suppressed by providing the punch-through stopper layer 50.

[Effects of the Invention] According to the present invention, the electric field in the source/drain electrode layer can be relaxed by the electric field effect of the GaI electrode, so that breakdown voltage and the like are improved and good electrical characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a device according to a first embodiment of the present invention, and FIG. 2 is a diagram showing a manufacturing method of the first embodiment. 3 to 6 are sectional views showing other embodiments. 10.11...Gate electrode, 20.20', 35...High concentration impurity layer, 30.30
'...Low concentration impurity layer, 41,. 42... Spacer, 50... Punch-through stopper layer. Sannomi Seri 31 countries 1o. 3o '''';, t1.
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Claims (1)

[Claims] 1. In an insulated gate field effect transistor comprising a high concentration impurity diffusion layer electrode, a low concentration impurity diffusion layer electrode, and a gate electrode having a structure overlapping with these electrode layers provided on a semiconductor substrate. A semiconductor device characterized in that a high concentration impurity diffusion layer electrode is provided inside a substrate at least on the drain side. 2. In an insulated gate field effect transistor consisting of a high-concentration impurity diffusion layer electrode, a low-concentration impurity diffusion layer electrode, and a gate electrode having an overlapping structure with these electrode layers, the high concentration is at least on the drain side. 1. A method for manufacturing a semiconductor device characterized in that a concentrated impurity diffusion layer electrode is provided inside a substrate, and the semiconductor device is characterized in that an overlapping structure of a gate electrode and an impurity diffusion layer electrode is provided in a self-aligned manner.