JPH067556B2 - MIS type semiconductor device - Google Patents
MIS type semiconductor deviceInfo
- Publication number
- JPH067556B2 JPH067556B2 JP5172185A JP5172185A JPH067556B2 JP H067556 B2 JPH067556 B2 JP H067556B2 JP 5172185 A JP5172185 A JP 5172185A JP 5172185 A JP5172185 A JP 5172185A JP H067556 B2 JPH067556 B2 JP H067556B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- region
- gate electrode
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 64
- 239000000758 substrate Substances 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、ＭＩＳ型半導体装置に関し、特にドレイン領
域の構造を改良したＭＩＳ型半導体装置に係る。TECHNICAL FIELD OF THE INVENTION The present invention relates to a MIS semiconductor device, and more particularly to a MIS semiconductor device having an improved drain region structure.
最近、ＭＩＳ型半導体装置（例えばＭＯＳ型半導体集積
回路）の高集積化が進行し、そのトランジスタがより微
細化されるに伴なってドレイン領域近傍の高電界を緩和
し、耐圧を向上するために、ドレイン領域を低濃度及び
高濃度の拡散領域の二重構造とした、いわゆるＬＤＤ
（Light Doped Drain）構造が開発、実用化されてい
る。Recently, in order to alleviate a high electric field in the vicinity of the drain region and improve the breakdown voltage, the MIS type semiconductor device (for example, a MOS type semiconductor integrated circuit) is highly integrated and the transistor is further miniaturized. , The so-called LDD in which the drain region has a double structure of low-concentration and high-concentration diffusion regions
(Light Doped Drain) structure has been developed and put to practical use.
しかしながら、ＬＤＤ構造の低濃度拡散領域はドレイン
電界を緩和することによりホットキャリアの発生を抑制
する反面、ホットキャリアによってゲート絶縁膜中に生
成された電界の影響を受けて、該低濃度拡散領域の表面
が空乏化し易くなる。その結果、ＬＤＤ構造のトランジ
スタは低濃度拡散領域による寄生抵抗が増大し、電流駆
動能力が低下するという特有の劣化現象を生じる。ＬＤ
Ｄ構造において、ドレイン電界緩和効果は低濃度拡散領
域の濃度が低い程大きいが、上述した特有の劣化現象も
濃度が低くなる程大きくなり、相反する要求により低濃
度拡散領域の濃度選択範囲は小さくなるという問題があ
った。However, while the low-concentration diffusion region of the LDD structure suppresses the generation of hot carriers by relaxing the drain electric field, the low-concentration diffusion region of the LDD structure is affected by the electric field generated in the gate insulating film by the hot carriers, The surface is easily depleted. As a result, the LDD-structured transistor has a peculiar deterioration phenomenon in which the parasitic resistance due to the low-concentration diffusion region increases and the current driving capability decreases. LD
In the D structure, the drain electric field relaxation effect is greater as the concentration of the low-concentration diffusion region is lower, but the above-mentioned characteristic deterioration phenomenon is also greater as the concentration is lower, and the concentration selection range of the low-concentration diffusion region is small due to conflicting requirements. There was a problem of becoming.
本発明は、ＬＤＤ構造の低濃度拡散領域によるドレイン
電界緩和効果を維持しつつ、該拡散領域による寄生抵抗
の増加に伴う電流駆動能力の低下に防止した高性能で高
信頼性のＭＩＳ型半導体装置を提供しようとするもので
ある。The present invention provides a high-performance and highly reliable MIS semiconductor device that maintains the drain electric field relaxation effect of the low-concentration diffusion region of the LDD structure and prevents the current driving capability from being lowered due to the increase of parasitic resistance due to the diffusion region. Is to provide.
本発明は、第１導電型の半導体基板と、この基板表面に
互に電気的に分離して設けられた第２導電型のソース，
ドレイン領域と、これら領域間のチャンネル領域を含む
基板表面にゲート絶縁膜を介して設けられたゲート電極
とを具備したＭＩＳ型半導体装置において、前記ゲート
電極の側面に幅の異なる二重の絶縁材料からなる壁体を
設け、かつ前記ソース，ドレイン領域のうち少なくとも
ドレイン領域を前記ゲート電極、第１の壁体、第２の壁
体に対して自己整合的に形成された第２導電型の第１，
第２，第３の拡散領域により構成すると共に、該第３拡
散領域を第２拡散領域より高濃度に、第２拡散領域を第
１拡散領域より高濃度に設定したことを特徴とするもの
である。かかる本発明によれば、既述の如くＬＤＤ構造
の低濃度拡散領域によるドレイン電界緩和効果を維持し
つつ、該拡散領域による寄生抵抗の増大に伴う電流駆動
能力の低下を防止した高性能で高信頼性のＭＩＳ型半導
体装置を得ることができる。The present invention relates to a semiconductor substrate of a first conductivity type and a source of a second conductivity type, which are electrically isolated from each other on the surface of the substrate.
In a MIS type semiconductor device comprising a drain region and a gate electrode provided on a substrate surface including a channel region between these regions via a gate insulating film, a double insulating material having different widths on the side surface of the gate electrode. And a second conductivity type second wall formed by self-aligning at least the drain region of the source and drain regions with the gate electrode, the first wall body, and the second wall body. 1,
It is characterized in that it is composed of second and third diffusion regions, and that the third diffusion region is set to have a higher concentration than the second diffusion region and the second diffusion region is set to have a higher concentration than the first diffusion region. is there. According to the present invention, as described above, while maintaining the drain electric field relaxation effect of the low-concentration diffusion region of the LDD structure, it is possible to prevent the deterioration of the current drivability due to the increase of the parasitic resistance due to the diffusion region and to achieve high performance and high performance. It is possible to obtain a reliable MIS type semiconductor device.
以下、本発明をｎチヤンネルＭＯＳＩＣに適用した例に
ついて第１図〜第４図の製造方法を併記して説明する。Hereinafter, an example in which the present invention is applied to an n-channel MOSIC will be described together with the manufacturing method shown in FIGS.
まず、ｐ型シリコン基板１に、選択酸化によりフィール
ド酸化膜２を形成した後、熱酸化処理を施して該フィー
ルド酸化膜２で分離された島状の基板１領域表面に厚さ
２５０Ａ°のゲート酸化膜３を形成した。つづいて、全
面に厚さ４０００Ａ°の多結晶シリコン膜を堆積し、Ｐ
ＯＣｌ３の雰囲気中でリン拡散を行なって該多結晶シリ
コン膜にリンをドープし低抵抗化させた後、フォトエッ
チング技術によりパターニングしてゲート電極４を形成
した。ひきつづき、ゲート電極４をマスクとしてリンを
加速電圧３５KeV、ドーズ量２×1015cm-2の条件でイオ
ン注入し、活性化して基板１表面にゲート電極４に対し
て自己整合的にｎ−型拡散領域（第１拡散領域）５１，
５２を形成した（第１図図示）。First, a field oxide film 2 is formed on a p-type silicon substrate 1 by selective oxidation, and then a thermal oxidation process is performed to form a gate with a thickness of 250 A ° on the surface of the island-shaped substrate 1 region separated by the field oxide film 2. The oxide film 3 was formed. Subsequently, a polycrystalline silicon film with a thickness of 4000 A ° is deposited on the entire surface, and P
Phosphorus was diffused in an atmosphere of OCl 3 to dope the polycrystalline silicon film with phosphorus to reduce the resistance, and then the gate electrode 4 was formed by patterning with a photoetching technique. Subsequently, using the gate electrode 4 as a mask, phosphorus is ion-implanted under the conditions of an accelerating voltage of 35 KeV and a dose amount of 2 × 10 15 cm −2 , and activated to self-align with the gate electrode 4 on the surface of the substrate 1 and n − type. Diffusion area (first diffusion area) 5 1 ,
5 2 was formed (Figure 1 shown).
次いで、熱酸化処理を施して多結晶シリコンからなるゲ
ート電極４の上面及び側面に厚さ１０００Ａ゜の酸化膜
（第１の壁体）６を形成した。つついて、ゲート電極４
及び酸化膜６をマスクとして拡散係数の比較的小さい砒
素を加速電極３５KeV、ドーズ量１×１０14cm-2の条件
でイオン注入し、活性化して基板１表面にゲート電極４
側面の酸化膜６に対して自己整合的に前記拡散領域
５１，５２より高濃度のｎ型拡散領域７１，７２を形成
した（第２図図示）。Then, a thermal oxidation process was performed to form an oxide film (first wall body) 6 having a thickness of 1000 A ° on the upper surface and the side surface of the gate electrode 4 made of polycrystalline silicon. Poking, gate electrode 4
Also, using the oxide film 6 as a mask, arsenic having a relatively small diffusion coefficient is ion-implanted under the conditions of an acceleration electrode 35 KeV and a dose amount of 1 × 10 14 cm -2 , and activated to activate the gate electrode 4 on the surface of the substrate 1.
To form a self-aligned manner with said diffusion region 5 1, 5 2 higher concentrations of n-type diffusion regions 7 1, 7 2 against oxidation film 6 side (FIG. 2 shown).
次いで、全面に厚さ２０００Ａ°のＳｉＯ２膜を堆積
し、反応性イオンエッチング法により全面エッチングを
行なってゲート電極４側面に対応する酸化膜６のＳｉＯ
２からなる第２の壁体８を形成した。つづいで、ゲート
電極４、酸化膜６及び第２の壁体８をマスクとして砒素
を加速電圧４０ＫｅＶ、ドーズ量５×１０15cm-2の条件
でイオン注入し、活性化して基板１表面に第２の壁体８
に対して自己整合的にｎ型拡散領域７１，７２より高濃
度のｎ＋型拡散領域（第３拡散領域）９１，９２を形成
した。この工程によりｎ−型拡散領域５１、ｎ型拡散領
域７１及びｎ＋型拡散領域９１からなるソース領域１０
が形成されると共に、ｎ−型拡散領域５２、ｎ型拡散領
域７２及びｎ＋型拡散領域９２からなるドレイン領域１
１が形成された（第３図図示）。Then, a SiO 2 film having a thickness of 2000 A ° is deposited on the entire surface, and the entire surface is etched by the reactive ion etching method to form the SiO 2 film of the oxide film 6 corresponding to the side surface of the gate electrode 4.
A second wall body 8 of 2 was formed. Subsequently, using the gate electrode 4, the oxide film 6 and the second wall body 8 as a mask, arsenic is ion-implanted under the conditions of an acceleration voltage of 40 KeV and a dose amount of 5 × 10 15 cm −2 , activated, and then activated on the surface of the substrate 1. 2 walls 8
To form a self-aligned manner n-type diffusion regions 7 1, 7 2 higher concentrations of n + -type diffusion region (third diffusion region) 9 1, 9 2 against. By this step, the source region 10 including the n − type diffusion region 5 1 , the n type diffusion region 7 1 and the n + type diffusion region 9 1 is formed.
Together but are formed, n - type diffusion region 5 2, drain region 101 made of n-type diffusion region 7 2 and the n + -type diffusion region 9 2
1 was formed (shown in FIG. 3).
次いで、全面にＣＶＤ−ＳｉＯ２膜１２を堆積し、該Ｃ
ＶＤ−ＳｉＯ２膜１２及びゲート酸化膜３等にフォトエ
ッチング技術によりコンタクトホール１３を開孔した
後、Ａｌ膜の蒸着、パターニングを行なうことにより前
記ソース，ドレイン領域１０，１１のｎ+型拡散領域９
１，９２及びゲート電極４とコンタクトホール１３を通
して接続するＡｌ配線１４，１５，１６を形成してｎチ
ャンネルＭＯＳＩＣを製造した（第４図図示）。Then, a CVD-SiO 2 film 12 is deposited on the entire surface, and the C
After forming a contact hole 13 in the VD-SiO 2 film 12 and the gate oxide film 3 by a photo-etching technique, an Al film is deposited and patterned to form the n + type diffusion regions of the source and drain regions 10 and 11. 9
1, 9 to form a 2 and Al wires 14, 15, 16 to be connected through the gate electrode 4 and the contact hole 13 was prepared n-channel MOSIC with (FIG. 4 shown).
しかして、本発明のＭＯＳＩＣは第４図に示すようにゲ
ート電極４の側面に厚さの異なる第１の壁体（酸化膜）
６及び第２の壁体８を設け、ｐ型シリコン基板１表面に
ゲート電極４、第１の壁体６、第２の壁体８に対して自
己整合的にｎ−型拡散領域（第１拡散領域）５１，
５２、ｎ型拡散領域（第２拡散領域）７１，７２、ｎ+
型拡散領域（第３拡散領域）９１，９２を設け、これら
拡散領域５１，７１，９１によりソース領域１０を、拡
散領域５２，７２，９２によりドレイン領域１１を構成
したＬＤＤ構造をなす。従って、ドレイン領域１１のｎ
−型拡散領域５２によりホットキャリアの発生を抑制し
てドレイン電界を緩和することができる。また、ホット
キャリアによってゲート酸化膜３中に生成した電界の影
響によるｎ−型拡散領域５２付近への空乏化を、それに
隣接するｎ型拡散領域７２により緩和でき、ひいては電
界駆動能力の低下を抑制できる。Therefore, as shown in FIG. 4, the MOSIC of the present invention has a first wall body (oxide film) having a different thickness on the side surface of the gate electrode 4.
6 and the second wall body 8 are provided, and the n − -type diffusion region (the first wall body 4 and the first wall body 6 and the second wall body 8 are self-aligned on the surface of the p-type silicon substrate 1 in a self-aligned manner). Diffusion area) 5 1 ,
5 2 , n-type diffusion region (second diffusion region) 7 1 , 7 2 , n +
Type diffusion regions (third diffusion regions) 9 1 and 9 2 are provided, and the diffusion regions 5 1 , 7 1 and 9 1 form a source region 10 and the diffusion regions 5 2 , 7 2 and 9 2 form a drain region 11. The LDD structure is formed. Therefore, n of the drain region 11
- it is possible to relieve the drain electric field to suppress the generation of hot carriers by diffusion region 5 2. Further, n due to the influence of the electric field generated in the gate oxide film 3 by a hot carrier - depletion in the diffusion region 5 2 vicinity, it can be mitigated by n-type diffusion region 7 2 adjacent thereto, thus lowering the electric field driving capability Can be suppressed.
更に、ｎ−型拡散領域５１，５２及びｎ型拡散領域
７１，７２の幅は、第１，第２の壁体６，８により容易
に制御できるため、前記二つの相反する問題を解消する
のに適した濃度、幅をもつｎ−型，ｎ型の拡散領域
５１，５２，７１，７２を形成できる。Furthermore, since the widths of the n − type diffusion regions 5 1 and 5 2 and the n type diffusion regions 7 1 and 7 2 can be easily controlled by the first and second wall bodies 6 and 8, the above two contradictory problems are encountered. It is possible to form n − type and n type diffusion regions 5 1 , 5 2 , 7 1 , 7 2 having concentrations and widths suitable for eliminating the above.
なお、上記実施例ではソース領域をも３つの濃度の異な
る拡散領域で形成したが、ドレイン領域のみ３つの濃度
の異なる拡散領域で形成してもよい。Although the source region is also formed of three diffusion regions having different concentrations in the above embodiment, only the drain region may be formed of three diffusion regions having different concentrations.
また、第１〜第３の拡散領域としてのｎ−型拡散領域、
ｎ型拡散領域、ｎ＋型拡散領域の形成条件は上記実施例
に限定されず、本発明の目的を達する範囲内で自由に変
更できる。Further, an n − type diffusion region as the first to third diffusion regions,
The conditions for forming the n-type diffusion region and the n + -type diffusion region are not limited to those in the above embodiment, and can be freely changed within the range where the object of the present invention is achieved.
上記実施例では、ｎチャンネルＭＯＳＩＣに適用した例
について説明したが、CMOSIC又はMNOS等のゲート絶縁膜
として酸化膜以外の材料を使用したＭＩＳ型ＩＣにも同
様に適用できる。In the above-mentioned embodiment, the example applied to the n-channel MOSIC has been described, but the present invention can be similarly applied to a MIS type IC using a material other than an oxide film as a gate insulating film such as CMOSIC or MNOS.
以上詳述した如く、本発明によればＬＤＤ構造の低濃度
拡散領域によるドレイン電界緩和効果を維持しつつ、該
拡散領域による寄生抵抗の増加に伴う電流駆動能力の低
下を抑制した高性能で高信頼性のＭＩＳ型半導体装置を
提供できる。As described above in detail, according to the present invention, while maintaining the drain electric field relaxation effect of the low-concentration diffusion region of the LDD structure, it is possible to achieve high performance with high performance by suppressing the decrease of the current driving capability due to the increase of parasitic resistance due to the diffusion region. A reliable MIS semiconductor device can be provided.
第１図〜第４図は本発明の実施例におけるｎチャンネル
ＭＯＳＩＣを得るための製造工程をす断面図である。 １…ｐ型シリコン基板、２…フィールド酸化膜、３…ゲ
ート酸化膜、４…ゲート電極、５１，５２…ｎ−型拡散
領域（第１拡散領域）、６…酸化膜（第１の壁体）、７
１，７２…ｎ型拡散領域（第２拡散領域）、８…第２の
壁体、９１，９２…ｎ＋型拡散領域（第３拡散領域）、
１０…ソース領域、１１…ドレイン領域、１４〜１６…
Ａｌ配線。1 to 4 are sectional views showing manufacturing steps for obtaining an n-channel MOSIC in the embodiment of the present invention. 1 ... p-type silicon substrate, 2 ... field oxide film, 3 ... gate oxide film, 4 ... gate electrode, 5 1, 5 2 ... n - -type diffusion region (first diffusion region), 6 ... oxide film (first Wall), 7
1 , 7 2 ... N type diffusion region (second diffusion region), 8 ... Second wall body, 9 1 , 9 2 ... N + type diffusion region (third diffusion region),
10 ... Source region, 11 ... Drain region, 14-16 ...
Al wiring.
Claims (1)
に互に電気的に分離して設けられた第２導電型のソー
ス，ドレイン領域と、これら領域間のチャンネル領域を
含む基板表面にゲート絶縁膜を介して設けられたゲート
電極とを具備したＭＩＳ型半導体装置において、前記ゲ
ート電極の側面に幅の異なる二重の絶縁材料からなる壁
体を設け、かつ前記ソース，ドレイン領域のうち少なく
ともドレイン領域を前記ゲート電極、第１の壁体、第２
の壁体に対して自己整合的に形成された第２導電型の第
１，第２，第３の拡散領域により構成すると共に、該第
３拡散領域を第２拡散領域より高濃度に、第２拡散領域
を第１拡散領域より高濃度に設定したことを特徴とする
ＭＩＳ型半導体装置。1. A substrate surface including a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type electrically isolated from each other on the substrate surface, and a channel region between these regions. In a MIS type semiconductor device having a gate electrode provided via a gate insulating film, a wall made of a double insulating material having different widths is provided on a side surface of the gate electrode, and At least a drain region of the gate electrode, the first wall body, and the second wall
Of the second conductivity type first, second, and third diffusion regions formed in a self-aligning manner with respect to the wall body of the second diffusion region, the third diffusion region having a higher concentration than the second diffusion region, 2. A MIS type semiconductor device characterized in that the second diffusion region is set to have a higher concentration than the first diffusion region.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5172185A JPH067556B2 (en) | 1985-03-15 | 1985-03-15 | MIS type semiconductor device |
| DE8585309209T DE3581797D1 (en) | 1984-12-27 | 1985-12-18 | MISFET WITH LOW-DOPED DRAIN AND METHOD FOR THE PRODUCTION THEREOF. |
| EP85309209A EP0187016B1 (en) | 1984-12-27 | 1985-12-18 | Misfet with lightly doped drain and method of manufacturing the same |
| US07/319,873 US4935379A (en) | 1984-12-27 | 1989-03-01 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5172185A JPH067556B2 (en) | 1985-03-15 | 1985-03-15 | MIS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61210673A JPS61210673A (en) | 1986-09-18 |
| JPH067556B2 true JPH067556B2 (en) | 1994-01-26 |
Family
ID=12894749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5172185A Expired - Lifetime JPH067556B2 (en) | 1984-12-27 | 1985-03-15 | MIS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH067556B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02250331A (en) * | 1989-03-24 | 1990-10-08 | Hitachi Ltd | Semiconductor device and its manufacture |
| JP2789109B2 (en) * | 1989-05-25 | 1998-08-20 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| FR2654258A1 (en) * | 1989-11-03 | 1991-05-10 | Philips Nv | METHOD FOR MANUFACTURING A MITTED TRANSISTOR DEVICE HAVING A REVERSE "T" SHAPE ELECTRODE ELECTRODE |
| FR2654257A1 (en) * | 1989-11-03 | 1991-05-10 | Philips Nv | METHOD FOR MANUFACTURING A MOUNTED TRANSISTOR DEVICE HAVING A DEPTHING GRID ON PORTIONS OF LOW DOPED SOURCE AND DRAIN REGIONS. |
| KR930010124B1 (en) * | 1991-02-27 | 1993-10-14 | 삼성전자 주식회사 | Semiconductor transistor structure and making method thereof |
-
1985
- 1985-03-15 JP JP5172185A patent/JPH067556B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61210673A (en) | 1986-09-18 |
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