JP2506947B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a submicron buried channel MOS transistor capable of improving the electrical characteristics of the subthreshold region which deteriorates when the buried channel MOS transistor is miniaturized to the submicron region. Is.

2. Description of the Related Art Conventionally, a p-channel MOS transistor using an n ⁺ poly Si gate uses the same buried channel structure as the source and drain. This makes it possible to obtain a high-speed transistor in which the electric field strength near the drain is lower than that in the surface channel structure, the resistance to the hot electron effect is high, and the deterioration in mobility is small. The same effect can be expected for an n-channel MOS transistor by controlling the work function.

However, with the miniaturization of devices, the buried channel MOS transistor has a great influence on the potential of the SiO ₂ -Si interface of the drain voltage, the leak current in the subthreshold region increases, and the dependency of the threshold voltage on the drain voltage is strong. Become. In order to cope with this, there is a structure (EPS: Effecient Punchthvough Stop) as shown in FIG. 8 as disclosed in Japanese Patent Publication No. 61-160975. That is, in the figure, 8a and 8b are source and drain regions, 5 is a gate electrode, 4 is a gate oxide film, 7a and 7b are sidewall oxide films, 3 is a p-type buried channel region, and 6a and 6b are n ⁺ layers,
1 is an n well. This structure keeps the subthreshold current coefficient low, and also reduces the drain voltage.
It was also possible to keep V _T fluctuations small.

The method of forming the n ⁺ layers 6a and 6b in this structure is as follows. After the gate electrode 5 is formed, phosphorus, which is an n-type impurity, is doped by the ion implantation method, and then an oxide film is deposited by the CVD method. After etching, sidewall oxide films 7a and 7b
And a p ⁺ layer to be the source and drain regions is formed by ion implantation of boron.
At this time, since the sidewall oxide films 7a and 7b serve as a mask at the time of implanting the source and drain, the n ⁺ layers 6a and 6b are formed below the region where the side of the channel region is in contact with the source and drain.
b can be left self-aligned.

However, in order to further miniaturize, it is required not only to shorten the length of the gate electrode in the channel length direction but also to narrow the width of the sidewall oxide film. Therefore, n ⁺
The area where the layer is formed becomes narrower, the effect of the n ⁺ layer weakens,
There is a problem that the influence of the drain voltage on the electrical characteristics in the subthreshold region cannot be suppressed.

Therefore, the present invention suppresses the subthreshold current count to a low level even if the region where the n ⁺ layer is formed becomes narrow due to the narrowing of the sidewall oxide film accompanying the miniaturization of the device, and the potential due to the drain voltage is reduced. It suppresses the elongation and reduces the fluctuation of the threshold voltage due to the drain voltage.

Means for Solving the Problems The present invention provides a semiconductor device including a high-concentration impurity layer below a region where a side of a channel region is in contact with a source / drain region and immediately below the channel region.

That is, the semiconductor device of the present invention includes a semiconductor substrate of the first conductivity type, a gate insulating film and a gate electrode selectively formed on the substrate, and a second insulating film formed immediately below the gate insulating film. A conductive type channel region and a second conductive type source selectively formed on a side portion of the channel region;
A drain region, the channel region and the source,
A first-conductivity-type high-concentration impurity layer is provided below a region in contact with the drain region, and a first-conductivity-type high-concentration impurity layer is provided immediately below the channel region. A step of forming a second conductivity type channel region and a first conductivity type high-concentration impurity layer immediately below the second conductivity type channel region in a portion to be a MOS transistor region selectively formed on the semiconductor substrate by ion implantation; Forming a high-concentration impurity layer of the first conductivity type by ion implantation so as to include a part of the lower portion of the channel region using the gate insulating film and the gate electrode formed on the base surface of the channel region as a mask; A step of forming an insulating film so as to cover the side surface of the gate electrode, and a second step using the gate electrode whose side surface is covered with the insulating film as a mask
The method includes a step of forming a conductive type source and drain by ion implantation.

Operation According to the present invention, the subthreshold current coefficient can be suppressed to a low level by the high-concentration impurity layer provided directly below the channel region, and the high-concentration impurity layer provided directly below the channel region allows the channel to be formed. Even if the junction depth becomes shallow and the surface concentration of the channel region increases, the high-concentration impurity layer provided below the region where the side of the channel region and the source / drain region contact each other suppresses the extension of the potential of the drain voltage. It is possible to obtain a semiconductor device in which the threshold voltage does not change due to the voltage.

First Embodiment FIG. 1 is a diagram showing a structural cross section of a semiconductor device according to a first embodiment of the present invention, which is a p-channel MOS transistor. The n-type high-concentration impurity layer 2 provided immediately below the buried p-channel 3 can make the channel junction depth shallow and suppress the subthreshold current coefficient low. Further, n-type high-concentration impurity layers 6a and 6b provided under the regions where the side portions of the channel region 3 are in contact with the sources and drains 8a and 8b.
As a result, it is possible to suppress the potential extension due to the drain voltage and suppress the threshold voltage variation due to the drain voltage.

The manufacturing method of this embodiment configured as described above will be described with reference to FIGS. As shown in FIG. 2, after forming the n-well 1 according to the normal process, the 10 nm oxide film 11 is formed.
To form the buried channel 3 for controlling the threshold voltage, BF ₂ is 60 kev, the dose is 3.0 × 10 ¹² / cm ² ,
Further, in order to form the n-type high-concentration impurity layer 2 for making the channel junction shallow under the channel 3, 170 k of phosphorus is used.
Ion implantation is performed with an ev and a dose of 2.0 × 10 ¹² / cm ² . Next, after removing the oxide film 11 used for the ion implantation, the gate insulating film 4 is deposited to a thickness of 10 nm and the poly-Si5 is deposited to a thickness of 350 nm, and then a gate electrode is formed through a normal process. Using this gate electrode as a mask, as shown in FIG. 3, in order to form the n-type high-concentration impurity layers 6a and 6b so as to include the lower portion of the channel 3, phosphorus is 130 kev and the dose is 3.2 × 10 ¹² / cm ^2. Ion implantation is performed. Further, after forming the oxide film 12 having a thickness of 10 nm, the oxide film 7 having a thickness of 150 nm is formed by the CVD method as shown in FIG. After that, the sidewall oxide films 7a and 7b with a width of 150 nm are anisotropically etched.
To form source and drain regions 8a and 8b in a self-aligned manner
It is formed by implanting F ₂ at 40 kev and a dose of 4 × 10 ¹⁵ / cm ² .
After that, the MOS type transistor shown in FIG. 1 is completed by a known method.

6 and 7 show examples of electrical characteristics of the semiconductor device manufactured as described above in this example. Figure 6 shows W /
Sub-threshold region electrical characteristics of a transistor of L = 10 / 0.5 μm are shown. The horizontal axis shows the gate voltage V _G , the vertical axis shows the drain current I _D, and the drain voltage is 1 to 4 V (1 V step) as parameters. The subthreshold current coefficient is suppressed to a low level, and good characteristics without the drain voltage dependence of the threshold voltage are obtained. Figure 7 shows the gate length dependence of the threshold voltage.
Even if the thickness is 0.5 μm or less, good characteristics with small short channel effect are obtained.

For comparison, similar electrical characteristics of the conventional example shown in FIG. 8 are shown in FIGS. 9 and 10. The semiconductor device of this conventional example is manufactured under the same conditions as the present embodiment except that there is no n-type high-concentration impurity layer immediately below the channel. However, in order to adjust the threshold voltage, BF ₂ was 60 kev and the dose was 1.7 × 10 ¹² / cm ² for channel injection. Compared with the present embodiment, the sub-threshold characteristic is dependent on the drain voltage, and the sub-threshold coefficient is also increased. Furthermore, the short channel effect has a gate length of about 0.7.
It is large below μm.

As described above, according to the present embodiment, the n-type high-concentration impurity layer is provided immediately below the channel region as well as under the region where the side of the channel region and the source / drain region are in contact with each other. Even if the width of the sidewall oxide film is narrowed in the region, the subthreshold current coefficient can be suppressed to a low level, the potential extension due to the drain voltage can be suppressed, and the fluctuation of the threshold voltage due to the drain voltage can be reduced.

As a second embodiment, instead of the normal n-well,
A retrograde type well is used. The well is formed under the condition that phosphorus is added to a p-type substrate of 10 to 15 cm · Ω.
Ion implantation was performed at 700 kev and a dose amount of 1.0 × 10 ¹³ / cm ² , and the heat treatment of the well was performed at 1050 ° C. for 2 hours to obtain normal n
A surface concentration equivalent to that of a well can be obtained. Other steps may be performed in the same manner as in the first embodiment. However, since the concentration just below the channel is slightly higher due to the retrograde well, it is necessary to correct the concentration of the n-type high concentration impurity layer. According to this embodiment, not only the same effect as that of the first embodiment can be obtained, but also when it is used as a CMOS circuit in combination with an n-channel MOS transistor, the latch-up resistance can be improved.

Although this embodiment relates to a p-channel MOS type transistor, it goes without saying that the present invention can also be applied to an n-channel MOS type transistor.

As described above, even if the region where the n ⁺ layer is formed becomes narrow due to the width of the sidewall oxide film becoming narrower with the miniaturization of the device, by using the semiconductor device of the present invention,
It is possible to suppress the subthreshold current coefficient to be low, suppress the potential extension due to the drain voltage, and reduce the fluctuation of the threshold voltage due to the drain voltage, and its practical effect is extremely large.

EFFECTS OF THE INVENTION As described above, according to the present invention, the sub-threshold current coefficient can be suppressed to a low level when the device is miniaturized, and further, the extension of the potential due to the drain voltage can be suppressed to reduce the threshold voltage due to the drain voltage. It is possible to realize a buried channel MOS transistor with a small fluctuation of, and it is extremely useful in a semiconductor integrated circuit.

[Brief description of drawings]

FIG. 1 is a sectional view of the structure of a p-channel MOS transistor according to an embodiment of the present invention, FIGS. 2 to 5 are sectional views for explaining a part of the manufacturing method of the present embodiment, and FIG. FIG. 7 is a diagram showing the sub-threshold characteristic of the example, FIG. 7 is a diagram showing the gate length dependence of the threshold voltage of the present embodiment, and FIG.
FIG. 9 is a sectional view showing the structure of a channel MOS transistor, FIG. 9 is a conventional subthreshold characteristic diagram, and FIG. 10 is a diagram showing the gate length dependence of the conventional threshold voltage. 1 ... n well, 2 ... n type high-concentration impurity layer, 3 ... buried p-channel region, 4 ... gate oxide film, 5 ... n ⁺ poly-Si gate electrode, 6a, 6b ... n-type high concentration Impurity layer, 7a, 7b
…… Sidewall oxide film, 8a, 8b …… Source and drain.

Claims (2)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a gate insulating film and a gate electrode selectively formed on the semiconductor substrate, and a second dielectric type channel formed directly below the gate insulating film. A region, a source / drain region of a second conductivity type selectively formed on a side portion of the channel region, and a first high-concentration impurity region of a first conductivity type formed immediately below the channel region. The first region is formed under the region where the channel region and the source / drain regions contact each other.
And a second high-concentration impurity region of the first conductivity type having a different impurity concentration. 2. A channel region of the second conductivity type is formed in a portion to be a MOS transistor region selectively formed on a semiconductor substrate of the first conductivity type, and a first conductivity type first region is provided immediately below the channel region of the second conductivity type. A step of forming a high-concentration impurity region by ion implantation; a first step of forming an impurity concentration different from that of the first high-concentration impurity region using the gate insulating film and the gate electrode formed on the substrate surface of the channel region as a mask; Forming a second high-concentration impurity region of conductivity type by ion implantation so as to include a part of the lower portion of the channel region, and forming an insulating film so as to cover the side surface of the gate electrode.
Forming a second conductive type source and drain region by ion implantation using the gate electrode whose side surface is covered with an insulating film as a mask; and forming the second high-concentration impurity region in the channel region and the channel region. A method for manufacturing a semiconductor device, which is formed below a region where a source region and a drain region are in contact with each other.