JP3282375B2 - Complementary insulated gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor (MOSFET) used in an analog circuit section or a circuit section in which an analog circuit and a digital circuit are simultaneously mounted.

[0002]

2. Description of the Related Art Complementary MOSFET used in integrated circuit devices
(Hereinafter abbreviated as CMOS) are p-channel MOSFET and n-channel MO
It is composed of SFETs. Conventionally, only the following two types of configurations have been considered for CMOS depending on whether the material used for the gate electrode is n ⁺ polysilicon or p ⁺ polysilicon. (1) If n ⁺ polysilicon is used for the gate electrode, the n-channel MOSFET becomes a surface channel type and the p-channel MOSFET
ET is of the buried channel type. (2) If n ⁺ polysilicon and p ⁺ polysilicon are used for the gate electrodes, respectively, the n-channel MOSFET becomes a surface channel type with the n ⁺ polysilicon gate, and the p-channel MOSFET
The SFET is a surface channel type with a p ⁺ polysilicon gate.

Here, as shown in (2), n ⁺ polysilicon and p
^The use of ⁺ polysilicon complicates the CMOS manufacturing process and increases manufacturing costs. However, this CMOS has p
The channel MOSFET can be a surface channel type, which is advantageous for the short channel effect. Generally, when a MOSFET is miniaturized to a submicron region or less, phenomena such as a decrease in threshold voltage (threshold voltage, hereinafter referred to as V _th ), an increase in drain voltage dependency of V _th , and an increase in leakage current in the sub threshold region. And the like, and these adverse effects on miniaturization are called short channel effects. The surface channel type is stronger than the buried channel type with respect to the short channel effect that appears due to miniaturization. This is because the drain current flows near the SiO ₂ / Si interface and is less affected by the drain voltage in the surface channel type.

In practice, even in the case of a buried channel type p-channel MOSFET, the sub-micron region can be improved by devising it as shown in FIG. 7 (FIG. 9 in this description) proposed in Japanese Patent Publication No. 4-82064. It can respond to miniaturization up to. In FIG. 9, 16 is a p-type source / drain region, 17 is a gate electrode, 18 is a gate oxide film, 19 is a sidewall oxide film, 20 is a p-type channel region of the same conductivity type as the source / drain region, and 21 is An n-type high-concentration impurity layer 22 of the opposite conductivity type to the channel region, and 22 is an n-type well. The buried p-channel MOSFET shown in FIG.
Is formed, the extension of the potential due to the drain voltage can be suppressed, and the short channel effect can be suppressed to some extent. However, buried channel types are inherently vulnerable to short channel effects. So high speed like digital circuit,
In circuits requiring high integration and low power consumption, p-channel MOSFETs also tend to be surface channel types that are advantageous for miniaturization.

By the way, MOSFs used in analog circuits
For ET, it is more important to stabilize the process and improve the accuracy than to miniaturize. It is a MOSFET in analog circuits
Variation due to the manufacturing process (such as MOSFET pairing)
This is because it immediately leads to a decrease in circuit performance. For this reason, the gate length of MOSFETs used in analog circuits is generally several μm.
m or more and the performance is maintained. This is a value sufficiently larger than the gate length (1 μm or less) of the MOSFET used in the digital circuit, and it is a point that improvement is desired.

[0006] The performance required of the CMOS for the analog circuit includes the internal noise of the MOSFET in addition to the pairing of the MOSFET. In particular, MOSFETs have larger internal noise than bipolar transistors, and have a practical problem. The n-channel MOSFET as described in (1) is a surface channel type,
When the channel MOSFET is a buried channel type, or when the n-channel MOSFET and the p-channel MOSFET are both surface channel types as in (2), these have been improved by focusing on miniaturization, but the internal noise No improvement has been made from the viewpoint of reduction of the amount of slag. 4-8206 mentioned above
The publication 4 is also for the purpose of suppressing the short channel effect (achieving miniaturization), and does not consider reducing internal noise. For this reason, MO
As a method of reducing internal noise in an SFET, a method of increasing the gate area has been adopted. It is generally reported that the internal noise of a MOSFET is inversely proportional to the gate area (eg,
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.ED-29,
NO.6, JUNE 1982), and there were no other effective methods for reducing internal noise, so the gate area was increased to reduce internal noise and to improve the pairing of MOSFETs. Therefore, there is a problem that increasing the degree of integration in an analog circuit is hindered by a noise problem. In an analog circuit in which internal noise is a problem, a bipolar transistor using a region with good crystallinity, which is known to have low noise, has been used.

In the case where the analog circuit section and the digital circuit section are both composed of CMOS in a circuit in which an analog circuit and a digital circuit are mixed (analog / digital mixed circuit), the CMOS configuration of the conventional digital circuit section remains unchanged. It was used up to the analog circuit. That is, as mentioned earlier
In the case where the n-channel MOSFET is a surface channel type and the p-channel MOSFET is a buried channel type as in (1), the CMOS configuration of (1) is used for both the digital circuit section and the analog circuit section. In addition, the n-channel MOSF described in (2)
If both the ET and the p-channel MOSFET are surface channel type, the p-channel MOSFET is replaced with the surface channel type for the performance required for the digital circuit part (high speed, high integration, and low power consumption by miniaturization of elements). However, the CMOS configuration of (2) has been used not only for digital circuits but also for analog circuits. For this reason, no special means has been taken to reduce the internal noise of the analog circuit section, and the gate area of the analog circuit section has been increased to reduce the internal noise. If the internal noise is still a problem, the analog circuit uses bipolar transistors and the digital circuit uses CMOS.

[0008]

However, when CMOS is used in an analog circuit, it has been described that the gate area is increased in order to reduce internal noise. However, this increases the chip area of the analog circuit and increases the product area. There was a problem of increasing costs. Furthermore, when the gate area is increased, the gate oxide film capacitance and the junction capacitance between the source and drain are increased, causing a phenomenon of lowering the operation speed and increasing the power consumption. In addition, when a bipolar transistor is used in an analog circuit, the bipolar transistor has a problem in that it consumes substantially higher power than CMOS, and cannot have a large input impedance because the element operates by flowing a base current. Was. In general, the manufacturing process of a bipolar transistor includes a process of epitaxially growing silicon on a silicon substrate, and this process has a problem that the manufacturing cost is higher than that of the CMOS manufacturing process.

Further, in the analog / digital mixed circuit, when both the analog circuit section and the digital circuit section are manufactured by CMOS, in order to reduce the noise of the analog circuit section,
It is necessary to increase the gate area of the MOSFET in the analog circuit section, and as a result, there is a problem that the chip area is increased and the manufacturing cost is increased. In addition, when the gate area is increased, the gate oxide film capacity and the junction capacity between the source and the drain are increased, so that there is a problem that the operation speed is reduced and the power consumption is increased. In an analog / digital mixed circuit, when an analog circuit portion is manufactured by a bipolar transistor and a digital circuit portion is manufactured by CMOS, a bipolar transistor manufacturing process and a CMOS manufacturing process are required.
Since different types of manufacturing processes are required for the same chip, the manufacturing process becomes very complicated, and there is a problem that the manufacturing cost is greatly increased. Furthermore, there are also problems of power consumption and input impedance. In addition, when both the n-channel MOSFET and the p-channel MOSFET are of the surface channel type as described in (2) above in the analog / digital hybrid circuit, the performance required for the digital circuit section (high-speed, small- High integration and low power consumption), but the performance required of the analog circuit (reduction of internal noise and gate area) cannot be satisfied. There is a problem that different required performances cannot be satisfied at the same time.

Accordingly, an object of the present invention is to provide a configuration for reducing internal noise of CMOS used in an analog circuit section in an analog circuit and an analog / digital mixed circuit,
An object of the present invention is to provide a CMOS for an analog circuit that can simultaneously reduce the internal noise of the CMOS and the gate area.
Another object of the present invention is to provide a CMOS for an analog circuit which does not require the use of a bipolar transistor in the analog circuit section due to the problem of internal noise in an analog circuit and an analog / digital mixed circuit. Further, an object of the present invention is to provide a performance required for an analog circuit section (reduction of internal noise and a reduction in gate area) and a performance required for a digital circuit section (high-speed, An object of the present invention is to provide a CMOS for an analog / digital mixed circuit that simultaneously satisfies both high integration and low power consumption.

[0011]

In order to solve the above-mentioned problems, according to the present invention, the transistor of the analog circuit section of the present invention is constituted by CMOS, and the gate electrode has n ⁺ polysilicon and p ⁺ polysilicon. Silicon is used respectively, the n-channel MOSFET is of a buried n-channel type by using a p ⁺ polysilicon gate, and the p-channel MOSFET is of a buried p-channel type by using an n ⁺ polysilicon gate. Another configuration is
The transistors of the analog / digital hybrid circuit are composed of CMOS, the gate electrode is made of n ⁺ polysilicon or p ⁺ polysilicon, and the n-channel MOSFET of the analog circuit section uses p ⁺ polysilicon gate. Buried n-channel type and p-channel
The MOSFET is of a buried channel type by using an n ⁺ polysilicon gate. The n-channel MOSFET in the digital circuit section is a surface channel type by using an n ⁺ polysilicon gate, and a p-channel MOSFET is used.
ET is characterized in that it is of a surface channel type by using a p ⁺ polysilicon gate.

[0012]

The operation of the present invention will be described based on the following experimental facts. FIG. 8 shows a surface channel type,
It is a measurement result of internal noise of each buried channel type MOSFET. The internal noise is shown on the vertical axis as the input converted noise voltage density at 10 Hz. The horizontal axis indicates the gate voltage _Vg , and the threshold voltage _Vth is subtracted (V
_g - _Vth ), the deviation of _Vth of the element is corrected. As a measurement condition, since an element in an analog circuit is used in a saturation region, internal noise is measured in a saturation region for each gate voltage. The solid line is the measurement result of the surface channel type MOSFET, and the broken line is the measurement result of the buried channel type MOSFET. In both cases, the gate length, gate width, and gate oxide film thickness are the same. As a result, it is clear that the buried channel type has lower internal noise for any gate voltage, and the buried channel type has lower internal noise by about 70% at the maximum.

This is qualitatively explained as follows.
In the surface channel type MOSFET, the drain current is SiO ₂ / Si
It flows near the interface. On the other hand, embedded channel type MO
In the SFET, the drain current spreads and flows from near the SiO ₂ / Si interface. In addition, there are many lattice defects near the SiO ₂ / Si interface, and the lattice defects randomly capture and emit current carriers flowing in the channel region, thereby causing a fluctuation in current density and generating internal noise. It is believed that. From these facts, the buried channel type MOSFET is SiO ₂ / Si
Since the current spreads from the vicinity of the interface, it is considered that the current is less likely to be affected by the vicinity of the SiO ₂ / Si interface than the surface channel type, and the internal noise is expected to be small. That the prediction is almost correct is shown by the measured data in FIG.

[0014]

The effects of the present invention will be described based on the experimental results. According to claim 1 of the present invention, p-type, n-type
Since both types have a buried channel configuration, a current flows in a deep region of each channel, and a complementary insulated gate field effect transistor in which internal noise hardly occurs is obtained. Also,
As compared with a conventional analog circuit having a CMOS configuration, a circuit with less internal noise and a smaller gate area and higher integration is realized. Also, since the channel type embedded analog circuits in analog / digital mixed circuit is used, the internal noise in the analog circuit can be reduced. Claim 2
According to even those which form the buried channel type and the surface channel type at the same time, there is the effect of reducing the internal noise by buried channel type, channel embedded into the analog circuitry in the analog / digital mixed circuit as shown in claim 3 By using the surface channel type for the mold and the digital circuit unit, it is possible to simultaneously satisfy the performance such as high speed required for the digital circuit unit and the performance required for the analog circuit unit.

That is, in an analog circuit section of an analog circuit and an analog / digital mixed circuit, an n-channel MO is used.
By making the SFET and the p-channel MOSFET both buried channel types, the internal noise of the n-channel MOSFET is greatly reduced by using the buried channel type in the case of (1) described in the related art. . In the case described in the prior art (2), n
Since both the channel MOSFET and the p-channel MOSFET are buried channel type, the internal noise of both the n-channel MOSFET and the p-channel MOSFET is greatly reduced.

In an analog / digital mixed circuit, an n-channel MOSFET and a p-channel MOSF in an analog circuit section are provided.
If the ET is a buried channel type and the n-channel MOSFET and p-channel MOSFET in the digital circuit are both a surface channel type, the performance (reduction of internal noise and gate area) required for the analog circuit is satisfied with the buried channel type. The performance required for the digital circuit section (high speed, high integration, and low power consumption by miniaturization of elements) can be satisfied by the surface channel type. , Internal noise can be reduced, and at the same time, the gate area can be reduced. As a result, it is possible to avoid an increase in cost due to an increase in chip area, to achieve an improvement in operation speed, and to reduce power consumption.

Conventionally, when a bipolar transistor is used in an analog circuit section, it may be possible to manufacture the CMOS circuit by applying the present invention. In this case, the power consumption is lower than that of a conventional configuration using a bipolar transistor. Power, high input impedance, and reduction in manufacturing cost can be realized. In particular, in the case where the analog circuit section is manufactured by using the CMOS according to the present invention, the manufacturing cost can be greatly reduced as compared with the case where the analog circuit section is manufactured using bipolar transistors and the digital circuit section is manufactured using CMOS in the mixed analog / digital circuit. Therefore, according to the configuration of the present invention, it is possible to realize a mixed analog / digital circuit having a CMOS configuration that simultaneously satisfies different performances required for the analog circuit section and the digital circuit section.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments. FIG. 1 shows a CM used in the analog circuit of the present invention.
FIG. 2 is a schematic cross-sectional view of an OS. In FIG. 1, a Si substrate 1
Then, an n-type Si well 2 and a p-type Si well 3 are formed, and p ⁺
A type Si source / drain 4 is formed on the n-type Si well 2, and an n ⁺ type Si source / drain 5 is formed on the p-type Si well 3. A p ^- type channel region 6 and an n ^- type channel region 7 are provided between respective source / drain portions, and a Si oxide film (LOCOS oxide film) 8 for element isolation.
Are separated by The gate Si oxide film 9, the sidewall oxide film 10, the n ⁺
The type polysilicon gate electrode 11, p ⁺ type polysilicon gate electrode 12, metal silicide (silicide) 13, interlayer insulating film 14, and Al wiring 15 constitute a MOSFET.

FIGS. 2 to 4 illustrate the steps of manufacturing the CMOS for the analog circuit shown in FIG. First, as shown in FIG. 2, a surface concentration of 2.
0 × 10 ¹⁶ (cm ^-3 ) n-type Si well 2, surface concentration 2.0 × 10
^{A 17} (cm ^-3 ) p-type Si well 3 is formed, and a Si well 3 for element isolation is formed.
After an oxide film (LOCOS oxide film) 8 is formed and a gate oxide film 9 of 160 ° is formed, ion implantation for controlling the threshold voltage V _{th is performed by} implanting 30 KeV boron (B) on the n-type Si well 2. , 1.0
Under the condition of × 10 ¹² (cm ⁻² ), the p-type Si well 3 contains phosphorus (P).
At 80 KeV and 3.5 × 10 ¹² (cm ⁻² ), and the p ^- type Si
A channel region 6 and an n ⁻ type Si channel region 7 are formed.

Next, as shown in FIG. 3, neutral (non-doped, high-resistance) polysilicon is made to have a volume by a chemical vapor deposition method by a known technique, and phosphorus (P) is added to the polysilicon on the n-type Si well 2. Then, boron (B) is ion-implanted into the polysilicon on the p-type Si well 3 to selectively form the n ⁺ -type polysilicon gate electrode 11 and the p ⁺ -type polysilicon gate electrode 12.

Next, as shown in FIG. 4, after forming an electric field relaxation layer (not shown) according to a normal process, SiO ₂ is deposited by a chemical vapor deposition method, and is removed by etching to form a side wall oxide film 10 to form a self-alignment. Specifically, p ⁺ -type Si source / drain 4 is formed on n-type Si well 2, and n ⁺ -type Si source / drain 5 is formed on p-type Si well 3.

Next, a silicide 13 is formed on the polysilicon gates 11 and 12 and the source / drain 4 and 5 in a self-aligned manner by a known technique, and an interlayer insulating film 14 is deposited by a chemical vapor deposition method. After drilling a contact hole for connecting the drain and the Al wiring, Al (aluminum) is pattern-deposited to form an Al wiring 15 (FIG. 1), as shown in FIG. Thereafter, although not shown, the MOSFET is formed according to the normal process.
To complete.

In the analog circuit manufactured in this manner, both the n-channel MOSFET and the p-channel MOSFET are of the buried channel type, and the internal noise is smaller than that of the CMOS manufactured in a normal process.

(Second Embodiment) FIG. 5 shows an embodiment of a CMOS used in an analog / digital mixed circuit of the present invention.
This will be described with reference to FIGS. FIG. 5 is a schematic cross-sectional view of a CMOS structure in which two analog circuit parts and two digital circuit parts are formed side by side on the same Si substrate 1. Si substrate 1 has n-type
A Si well 2 and a p-type Si well 3 are provided separately in an analog circuit section and a digital circuit section, respectively. Then, the p ⁺ -type Si source / drain 4 is placed in the n-type Si well 2,
An n ⁺ -type Si source / drain 5 is formed in the p-type Si well 3, and a layer of a p ⁻ -type channel region 6 and an n ⁻ -type channel region 7 is formed between each source / drain. Since the channel regions 6 and 7 of the analog circuit portion are of different conduction types from the wells, they are buried layers, respectively, and the channel regions 6 and 7 of the digital circuit portion are formed in the same conduction type wells. , Merely acts as a layer for adjusting the carrier concentration and acts as a surface channel.

An Si oxide film (LOCOS oxide film) 8 for element isolation is formed so as to separate the wells 2 and 3 from each other.
A gate Si oxide film 9 is provided on each channel region,
The n ⁺ -type polysilicon gate electrode 11 is on the p ⁻ -type channel region 6 and the p ⁺ -type polysilicon gate electrode 12 is
^A pattern is formed on the-type channel region 7, and sidewall oxide films 10 are formed on both sides of each gate. Then, a metal silicide (silicide) 1 is formed on the source / drain regions.
After covering with the thin film of No. 3, the entire upper surface of the Si substrate 1 is protected by the interlayer insulating film 14, an opening serving as a contact of a source / drain portion is provided, and an Al wiring 15 is formed there. A circuit CMOS is formed.

FIGS. 6 and 7 illustrate a process of manufacturing the CMOS for an analog / digital mixed circuit shown in FIG. As shown in FIG. 6, n-type Si well 2 of surface concentration 2.0 × 10 ¹⁶ (cm ^-3) according to the usual process on the Si substrate 1, p-type Si well 3 surface concentration 2.0 × 10 ¹⁷ (cm ^-3) Are formed, a Si oxide film (LOCOS oxide film) 8 for element isolation is formed, a gate oxide film 9 of 160 ° is formed, and ion implantation for controlling the threshold voltage V _th is performed by an analog circuit section. N-type Si
On the well 2, boron (B) is added at 30 KeV, 1.0 × 10 ¹² (c
m ⁻² ), and phosphorus (P) on the p-type well 3 of the analog circuit section at 80 KeV and 3.5 × 10 ¹² (cm ⁻² ).
Furthermore, phosphorus (P) is placed on the n-type Si well 2 of the digital circuit section.
Under the conditions of 80 KeV, 2.0 × 10 ¹² (cm ⁻² ), and boron (B) of 30 KeV, 2.
The process is performed under the condition of 0 × 10 ¹¹ (cm ⁻² ) to form the p ⁻ type Si channel region 6 and the n ⁻ type Si channel region 7, respectively.

Next, as shown in FIG. 7, neutral (non-doped, high-resistance) polysilicon is deposited by a chemical vapor deposition method by a known technique, and the polysilicon 11a on the n-type Si well 2 of the analog circuit portion is deposited. Phosphorus (P) is ion-implanted, and boron (B) is implanted into the polysilicon 12a on the p-type Si well 3 in the analog circuit portion, and boron (B) is implanted into the polysilicon 12d on the n-type Si well 2 in the digital circuit portion. ), And the polysilicon (11d) on the p-type Si well 3 of the digital circuit portion is phosphorus (P).
To selectively pattern the n ⁺ -type polysilicon gate electrode 11 and the p ⁺ -type polysilicon gate electrode 12. Thereafter, the analog / digital converter shown in FIG. 5 is manufactured by the same manufacturing method as in the first embodiment.
A CMOS for a digital embedded circuit can be obtained.

The analog / digital hybrid circuit manufactured as described above has an analog circuit portion having a buried channel type and low internal noise, and a digital circuit portion having a surface channel type suitable for miniaturization. Hardly complicated.

As described above, the CMOS for an analog circuit according to the present invention comprises an n-channel MOSFET and a p-channel MOSFET.
Both are buried channel types, and it is possible to realize a CMOS that simultaneously achieves a reduction in internal noise and a reduction in gate area. Further, the analog / digital mixed circuit according to the present invention realizes a CMOS analog / digital mixed circuit in which the analog circuit section is of a buried channel type and simultaneously satisfies different performances required for the analog circuit section and the digital circuit section. It is also possible.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a CMOSFET showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a manufacturing process according to the first embodiment of the present invention (part 1).

FIG. 3 is a schematic cross-sectional view of a manufacturing process according to the first embodiment of the present invention (part 2).

FIG. 4 is a schematic cross-sectional view of a manufacturing process according to the first embodiment of the present invention (part 3).

FIG. 5 is a schematic sectional view of a CMOSFET showing a second embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view (1) of a manufacturing process according to a second embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a manufacturing process according to a second embodiment of the present invention (part 2).

FIG. 8 is a view for explaining the principle of the present invention and is a view showing measurement results of internal noise of a buried channel type and a surface channel type.

FIG. 9 is a cross-sectional view of a conventional buried channel MOSFET improved with respect to miniaturization.

[Explanation of symbols]

1. . 1. Si substrate . 2. n-type Si well . 3. p-type Si well . 4. p ⁺ Si source / drain . n ⁺ Si source / drain . p ^- Si channel region (analog part is embedded type,
The digital part is a surface type. . n ^- Si channel region (analog part is embedded type,
(Digital part is surface type) . 8. Si oxide film for isolation between devices (LOCOS oxide film) . Gate Si oxide film 10. . 10. Side wall oxide film . n ⁺ -type polysilicon gate electrode 12. . 12. p ⁺ type polysilicon gate electrode . 13. Metal silicide (silicide) . 14. Interlayer insulating film . Al wiring 16. . p-type source / drain 17. . Gate electrode 18. . Gate oxide film 19. . Side wall oxide film 20. . 21. p-type channel region of the same conductivity type as the source / drain regions . 22. n-type high-concentration impurities of the opposite conductivity type to the channel region; . n-type well

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 29/78 H01L 21/334-21/336 H01L 27/04

Claims (3)

(57) [Claims] 1. A complementary insulated gate field effect transistor in which an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor are formed on the same substrate, wherein an n-type main surface and a p-type main surface are provided. A buried channel type n-channel insulation formed on the p-type main surface including a semiconductor substrate having: a p-type gate electrode; a pair of n-type source / drain regions; and an n-type channel region. A buried channel type p-channel insulation formed on the n-type main surface including a gate field effect transistor, an n-type gate electrode, a pair of p-type source / drain regions, and a p-type channel region It has a gate field effect transistor, the complementary formed on the same substrate an insulated gate field effect
Transistor is the same for analog and digital circuits
A complementary insulated gate field effect transistor, which is an analog circuit element of a circuit formed on a substrate . 2. A complementary insulated gate field effect transistor in which an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor are formed on the same substrate, wherein an n-type main surface and a p-type main surface are provided. A buried channel type n-channel insulation formed on the p-type main surface including a semiconductor substrate having: a p-type gate electrode; a pair of n-type source / drain regions; and an n-type channel region. A buried channel type p-channel insulation formed on the n-type main surface including a gate field effect transistor, an n-type gate electrode, a pair of p-type source / drain regions, and a p-type channel region A gate field effect transistor; an n-type gate electrode formed on the p-type main surface;
A channel-type n-channel insulated-gate field-effect transistor including a pair of source / drain regions of a p-type and a p-type channel region; a p-type gate electrode formed on the n-type main surface;
A complementary insulated gate field effect transistor having a surface channel type p-channel insulated gate field effect transistor including a pair of source / drain regions of an n-type and an n-type channel region. 3. The buried channel type n-channel insulated gate when the complementary insulated gate field effect transistor formed on the same substrate is used for a circuit in which an analog circuit and a digital circuit are formed on the same substrate. The field-effect transistor and the buried-channel p-channel insulated-gate field-effect transistor are both elements used in an analog circuit section. The surface-channel n-channel insulated-gate field-effect transistor and the surface-channel p-channel transistor 3. The complementary insulated gate field effect transistor according to claim 2, wherein the insulated gate field effect transistor is an element used in a digital circuit unit.