JPH0482064B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a sub-channel MOS field effect transistor that can improve the electrical characteristics in the threshold region and subthreshold region, which deteriorate when miniaturizing a buried channel MOS field effect transistor to the submicron region. It concerns a micron buried channel MOS field effect transistor (MOSFET).

Conventional technology In ultra-integrated circuit devices, so-called VLSI,
The importance of CMOS technology is increasing. CMOS
are p-channel MOSFET and n-channel
The following two types of configurations can be considered for CMOS depending on whether the material used for the gate electrode is n ⁺ -polysilicon or p ⁺ -polysilicon. That is, (1) When n ⁺ -polysilicon is used for the gate electrode, the n-channel MOSFET becomes a surface channel type, and the p-channel MOSFET becomes a buried channel type.

(2) If n ⁺ -polysilicon and p ⁺ -polysilicon are used for the gate electrode, n-channel
The MOSFET is a surface channel type with an n ⁺ -polysilicon gate, and the p-channel MOSFET is a p ⁺
- Surface channel type with polysilicon gate.

Here, a p-channel MOSFET (1) using n ⁺ -polysilicon for the gate electrode will be explained.

When an n ⁺ -poly-Si gate is used as a p-channel MOSFET, the channel region of the p-channel MOSFET has the same conductivity type as the source and drain regions, making it a so-called buried channel MOSFET.
Compared to so-called surface channel MOSFETs, in which the channel region has the opposite conductivity type as the source and drain regions, buried channel MOSFETs have a device structure that has lower electric field strength near the drain and is more resistant to the hot electron effect. ,Also,
A high-speed MOSFET with little degradation in mobility can be obtained. Similar effects can be expected for n-channel MOSFETs by controlling the work function.

However, when embedded MOSFETs are miniaturized to the submicron region, the influence of the drain voltage on the potential ψ ₅ of the SiO ₂ -Si interface is large, resulting in an increase in leakage current in the subthreshold region and the dependence of the threshold voltage V _T on the drain voltage. Strengthen your sexuality.

To address this, e.g. IEEE
Transactions on Electron Devices ED−
31pp.964-968 As disclosed in KIT.M.CHAM et al. in 1984, it had a structure as shown in Figure 7. That is, in the figure, 11 is the source and drain region, 12 is the gate electrode, 13 is the gate oxide film, 1
4 is a sidewall oxide film, 15 is a p-type channel region, 16 is
is an n ⁺ layer, and 17 is an n-well. In this structure, the source and drain junction depths are made shallow to 0.1 μm, and in order to make the channel junction depth shallow,
Channel doping is done with BF ₂ at 45keV, and As is ion-implanted at 200keV. The p-type channel region 15 has a surface concentration value of approximately 3.0x10 ¹⁶ cm ^-3 and the n ⁺ layer 16 has a surface concentration value of approximately 2.0x10 ¹⁶ cm ^-3 .

At this time, by implanting an n-type impurity As into the p region formed by implanting the p-type impurity _BF2 , a part of the p-channel region is compensated to become an n region, and the p-type channel area
It is formed extremely shallow down to 0.09μm. Further, an n ⁺ layer 16 is formed on the entire surface immediately below the channel region 15 . This enables miniaturization of a buried p-channel MOSFET with a gate oxide film of 150 angstroms to an effective channel length of 0.6 μm (gate length > 0.8 μm).

Problems to be Solved by the Invention However, such a structure cannot suppress the short channel effect of the buried p-channel MOSFET. In other words, for the short channel effect, (1) the threshold voltage V _T due to the drain voltage
(2) an increase in the subthreshold current coefficient, and both of these effects become significant as embedded p-channel MOSFETs are miniaturized.

In the conventional MOSFET shown in Figure 7, the subthreshold current coefficient in (2) can be kept low by making the channel junction depth shallow, but the variation in the threshold voltage V _T due to the drain voltage in (1) can be suppressed. I can't.

The reason for this will be explained using Figure 5 (IEEE
Transactions on Electron Devices ED−
33pp.317-321 1986). Figure 5 shows two types of buried p-channels with different channel junction depths.
For MOSFET, Si-
Absolute value of total impurity distribution concentration value ( _｜ N _D −N _A ｜:
Here, N _D indicates the n-type impurity concentration and N _A indicates the p-type impurity concentration. In the figure, 8 is a p-channel MOSFET with a channel junction depth of 0.24 μm, and 9 is a p-channel MOSFET with a channel junction depth of 0.12 μm.
It is a channel MOSFET.

Both p-channel MOSFETs 8 and 9 have a gate oxide film of 100 angstroms, a gate length of 0.5 μm, and a threshold voltage V _T of -0.6V. The p-channel MOSFET 8 is formed on the n-well with a surface concentration of 1.0x10 ¹⁶ cm ^-3 by ion implantation of 40 keV boron, and the p-channel MOSFET 8 is formed on the n-well with a surface concentration of 1.0x10 16 cm -3.
^{The n-}
It is formed on a well.

If we try to obtain a shallow channel junction from p-channel MOSFET 8 to p-channel MOSFET 9 while keeping the threshold voltage V _T constant at -0.6V due to the characteristics of p-channel MOSFETs 8 and 9 in FIG. , it can be seen that the channel doping dose must be increased to increase the surface concentration value.

If the channel junction depth is made shallow in this way, the subthreshold current coefficient will not deteriorate, but in order to _{set V} becomes susceptible to fluctuations depending on the drain voltage, making it impossible to suppress fluctuations in V _T due to the drain voltage.

On the other hand, if you try to reduce the junction depth of the p-type channel while keeping the low surface concentration constant without increasing the surface concentration of the channel, the threshold voltage V _T will become -1.1V or less. , V _T cannot be set to −0.6V. In other words, V _T
In order to set the voltage to −0.6V, the surface concentration value of the channel must be increased.

Therefore, in the configuration shown in FIG. 7, even if an extremely shallow channel junction depth can be achieved and the subthreshold current coefficient can be kept low,
In order to set the threshold voltage V _T constant, it is necessary to increase the surface concentration value of the p-type channel, and as a result, the fluctuation of V _T due to the drain voltage becomes large. Become.

Furthermore, in order to further suppress the expansion of the potential due to the drain voltage, if the n ⁺ layer 16 formed on the entire surface immediately below the p-channel is highly doped, the subthreshold is The JORD current coefficient also deteriorates.

Therefore, the present invention suppresses the subthreshold current coefficient and suppresses the expansion of the potential due to the drain voltage.
This is to reduce V _T fluctuation.

Means for Solving the Problems The technical means of the present invention for solving the above-mentioned problems is to apply a high concentration layer directly below the channel region and on the sides of the source/drain region to suppress the expansion of the potential due to the drain voltage. This forms an impurity layer.

Effect The effect of this technical means is as follows.
In other words, an impurity having a conductivity type opposite to that of the channel region has a peak concentration value at a position shallower than the junction depth of the source and drain regions under the channel doped region on the side of the source and drain regions in a part directly below the channel region. By forming a layer, an impurity layer of the opposite conductivity type is formed on the entire surface immediately below the channel region as in the conventional method, and an increase in the surface concentration of the channel region due to a shallow channel junction depth is reduced, and This suppresses the increase in drain voltage potential. As a result, the threshold voltage V _T
This provides an embedded channel MOSFET with no fluctuations.

Embodiment Hereinafter, an embodiment of the present invention will be described based on FIGS. 1 to 7. In FIG. 1, 1 is a p-type source and drain region, 2 is a gate electrode, 3 is a gate oxide film, 4 is a sidewall oxide film, and 5 is a p-type channel region of the same conductivity type as the source and drain regions. n-type high concentration impurity layer 6 of the opposite conductivity type to the region
is formed. Further, 7 is an n-well.

2 to 4 illustrate the manufacturing process of the p-type buried channel MOSFET shown in FIG. 1 and having a gate length of 0.5 μm. As shown in Fig. 2, after forming the n-well 7 according to the normal process, BF ₂ for controlling the threshold voltage V _T is applied.
Ions are implanted through a 200 Å oxide film at 40 keV and a dose of 3.2×10 ¹² /cm ² to form a p-type channel region 5, and a 100 Å gate oxide film 3 and a gate electrode 2 are formed.
selectively formed. Next, as shown in Figure 3, add phosphorus.
The n ⁺ layer 6 is formed directly under the p-type channel region 5 by implanting at a dose of 130keV and a dose of 1.0×10 ¹² /cm ² . Next, as shown in Figure 4, chemical vapor deposition (CVD) is applied.
After depositing SiO ₂ , it is removed by etching.
After forming the SiO ₂ sidewall 4, the source,
Drain region 1: BF ₂ : 40kev, dose: 3×
Formed by injection at 10 ¹⁵ /cm ² . Thereafter, although not shown, the MOSFET is completed using a well-known method.

In the MOSFET obtained in this way, it is not necessary to make the channel junction depth extremely shallow in order to suppress the short channel effect, and as explained using FIG. 5, the channel junction depth can be made shallow. It is possible to suppress an increase in the impurity surface concentration in the channel region due to

Curves 10 and 11 in FIG. 6 show the drain current I _D value and drain voltage when the drain voltage V _D of the MOSFET (gate length 0.5 μm) of this example is -3V.
The drain current I _D value when V _D is -0.5V was measured by changing the gate voltage V _G , but it is different from that of a conventional MOSFET (gate length
As can be seen from the comparison with measurement curves 10A and 11A of 0.5 μm), in the MOSFET of this example, V _T fluctuation due to drain voltage fluctuation is reduced.

Effects of the Invention As explained above, the present invention is a buried channel type MOS field effect transistor in which high concentration impurities of the opposite conductivity type to the channel region are formed on the sides of the source and drain regions in a part immediately below the channel region. Since the layer is formed, the subthreshold current coefficient is small, and V _T fluctuation due to drain voltage can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a buried channel type MOS field effect transistor according to an embodiment of the present invention.
Figures 2 to 4 are cross-sectional views explaining the manufacturing process of the same transistor, and Figure 5 is a buried p-type transistor.
Figure 6 is a characteristic diagram showing the relationship between _MOSFET channel junction depth and _impurity distribution. The figure is conventional
FIG. 2 is a cross-sectional view of a MOS field effect transistor. 1... Source, drain region, 2... Gate electrode, 3... Gate oxide film, 4... Sidewall oxide film, 5
. . . p-type channel region, 6 . . . n-type high concentration impurity layer, 7 . . . n-well.

Claims (1)

[Claims] 1. A buried channel MOS field effect transistor having a source/drain region and a channel region of a conductivity type opposite to that of the substrate on the surface of a semiconductor substrate of one conductivity type, which is selectively formed on the substrate. source/drain regions having a conductivity type opposite to that of the substrate; a channel region having a conductivity type opposite to that of the substrate formed so as to be connected to the source/drain regions on the surface of the substrate; and a channel region covering the source/drain regions. , a gate insulating film formed on the substrate; and a gate insulating film formed on the source/drain region side directly below the channel region and on a side of the source/drain region from the side of the source/drain region. In order to achieve this, a high concentration impurity layer of one conductivity type is provided so as not to entirely cover directly beneath the channel region, and the high concentration impurity layer suppresses the extension of potential from the source/drain to the substrate. MOS type field effect transistor.