JP2635096B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MIS-type electric field which is suitable for suppressing a short channel effect of an MIS-type field-effect transistor and which has an excellent source-drain breakdown voltage. Related to effect transistors.

[Conventional technology]

As a measure for preventing the short channel effect of the conventional MIS transistor, a high-concentration layer described in Japanese Patent Application No. 58-124713 is formed over the entire surface, assuming that a punch-through stop layer is provided inside the substrate, or I E Day
M, Technical Digest (1985) pp. 230-233 (IEDM, Technical Digest pp 230-233 (198
As discussed in 5)), there is one in which a high concentration layer is formed around the source and drain. The former is shown in FIG.

[Problems to be solved by the invention]

In the above prior art, the latter has a high-concentration layer for punch-through stopper around the source and drain, which is certainly effective in suppressing the short-channel effect. However, the latter operation lowers the drain withstand voltage or increases the photocarrier effect. This leads to a decrease in reliability.

In the method of embedding the high-concentration layer 8 as shown in FIG. 2, the effect on the photocarrier effect is small because the impurity concentration near the substrate surface does not change. It has to be shallow, which also causes a decrease in drain withstand voltage. This will be described in the case of a single-drain structure n-channel MOSFET. FIG. 3A shows the substrate impurity concentration distributions 30a to 34a in the depth direction and the distribution 34 of the source / drain diffusion layers. 31a to 33a are distributions having a high concentration buried layer, the peak positions of which are changed, and 30a is a normal distribution without a buried layer. FIG. 3B shows the threshold voltage V _TH versus the effective channel length Leff (V _TH -Leff) characteristic showing the degree of the short channel effect of the device having these substrate impurity distributions, and the minimum drain breakdown voltage BV _DS .min vs. Leff ( The BV _DS .min-Leff characteristic is shown in FIG. 3c. The V _TH -Leff characteristic is improved by providing the buried layer, and the degree is better when the peak position of the buried layer is shallower. Here, 30b to 33b correspond to elements having a distribution of 30a to 33a, respectively. On the other hand, BV _DS .min is determined by the balance between a mechanism that reduces the occurrence of parasitic bipolar due to the formation of a low-resistance layer in the substrate and a mechanism that decreases due to an increase in substrate current, which is a seed of the parasitic bipolar effect. . Therefore, as the buried layer becomes shallower, the latter becomes dominant as shown in FIG. Where 30c-33c
Corresponds to an element having a distribution of 30a to 33a. Therefore, in the above-mentioned buried layer method, if the degree of suppression of the short channel effect is improved, the drain withstand voltage is reduced.

Another prior art is Japanese Patent Application No. 62-137231.

An object of the present invention is to suppress the short channel effect without impairing the operation reliability such as the reduction of the drain withstand voltage and the increase of the hot carrier effect.

[Means for solving the problem]

The object of the present invention is to provide, within a substrate of an MIS field-effect transistor, an impurity region having a higher concentration than a shallow first substrate of the same conductivity type as a substrate for a punch-through stopper, and a first impurity region deeper than the first impurity region. First contact so as to be in contact with the impurity region of
This is achieved by providing a second impurity region having the same conductivity type as the substrate at a higher concentration than the impurity region.

[Action]

The first high-concentration impurity region is for suppressing the short channel effect such as the punch-through stopper as described above. Since the substrate surface concentration itself does not change, the increase in the hot carrier effect is small.

The second high-concentration impurity region is located deeper than the first high-concentration impurity region in the substrate, and does not contribute to the improvement of the short channel effect such as punch-through stopper. However, since a low-resistance layer is formed inside the substrate, It becomes an efficient collector of the substrate current, and the parasitic bipolar effect is more unlikely to occur. As a result, the drain withstand voltage is further improved.

〔Example〕

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

FIGS. 1 and 4b show a typical first and second high-concentration buried layer of the present invention having a single drain structure n.
It is formed on a channel MOS transistor. a is the impurity distribution in the depth direction, and 34 is the source. The drain diffusion layer 40a is the impurity distribution in the substrate according to the present invention. For comparison, a conventional impurity distribution 32a in which the first high concentration layer 7 has the same concentration is shown in 32a.

V _TH -Le of devices having two substrate impurity distributions respectively
The ff characteristics and the minimum drain breakdown voltage BV _DS .min-Leff characteristics are shown in FIGS. 3a and 3b. For V _TH -Leff characteristics, 32b and 40b
And there is almost no difference. This is because the first high-concentration buried layer 7 acting as a punch-through stopper is the same, and the effect of the second high-concentration buried layer 8 of the present invention is small. In contrast, the minimum drain withstand voltage went from 32c to 40c.
It has improved by 1V or more. This is because the substrate current increased in the first buried layer 7 is absorbed by the second buried layer 8 having a lower resistance, thereby making it difficult to generate a parasitic bipolar effect.

As a result, the suppression of the short channel effect and the improvement of the drain withstand voltage can be realized at the same time, which is very effective for a MOSFET having a submicron, particularly a gate length of 0.5 μm or less.

Embodiment 2 Next, another embodiment of the structure of the present invention will be described with reference to FIGS. 5 and 6. FIG.

FIG. 5 (a) shows that the buried layers 7 and 8 are the same as those of the first embodiment, and the source. The drain structure has a low concentration drain (LDD, Lightly doped Drain). As a result, the short channel effect can be suppressed and the drain withstand voltage can be improved as in the first embodiment, and further, the long-term operation reliability of the hot carrier effect can be improved. Further, the structure shown in FIG.
In the structure, the upper portions of the low concentration source and drain are all covered with the gate electrode, and the reliability is further improved as compared with the above LDD.

In the embodiment shown in FIGS. 6A, 6B and 6C, the first high-concentration impurity region 7 for the punch-through stopper is used.
The shape of is changed. In (a), although the basic characteristics are not different from those of the first embodiment, the junction capacitance can be reduced because the lower portions of the source and drain are not directly in contact with the high concentration layer. In (b), since there is no high-concentration impurity layer below the channel, the effect of reducing the short channel effect such as suppression of punch-through is slightly inferior to that of the first embodiment. The variation of the threshold voltage due to the substrate effect is small.

(C) shows a structure in which a first high-concentration layer 7 for punch-through stoppers is provided around a low-concentration layer having an LDD structure, and a second high-concentration layer 8 is provided below the first high-concentration layer 8. In this structure, the drain withstand voltage is easily reduced, but this is prevented by the high concentration layer 8.

As described above, in the present invention, the first short channel effect suppressing
The shape of the high-concentration buried layer may be arbitrary according to the purpose of the device. It is necessary that the second high-concentration buried layer be present at least below the channel near the drain inside the substrate than the first high-concentration layer. It is.

Embodiment 3 Next, an embodiment of a manufacturing method for manufacturing a typical structure of the present invention will be described with reference to FIG.

First, as shown in FIG. 7A, p-type silicon (resistivity)
After forming a thermal oxide film 11 of 20 to 30 nm on the substrate 1, a silicon oxide film 10 of 500 to 700 nm for element isolation is selectively formed. Next, as shown in FIG. 7 (b), boron is first implanted at an energy of 300 to 500 KeV, and an implantation amount is 1 × 10 ^{13 to} 3 × 1.
0 ¹³ cm ^-2 is implanted over the entire surface to form a second high-concentration impurity region 8
Then, the entire surface is implanted with an implantation energy of 100 to 200 KeV and an implantation amount of 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² to form a first high-concentration impurity region 7. Here, the first high-concentration impurity region 7 is a punch-through stopper for suppressing the short channel effect, and the second high-concentration impurity region 8 is a low-resistance layer for improving drain withstand voltage. Thereafter, as shown in FIG. 7 (c), a gate oxide film 2 is formed to a thickness of 10 to 25 nm, and boron 9 for setting a threshold voltage is implanted to a thickness of about 10 ¹¹ to 10 ¹³ cm ⁻² . Subsequently, 200 to 300 nm of phosphorus-doped polycrystalline silicon is formed and patterned by photo-etching to form the gate electrode 3. Finally, 5 × 10 ¹⁵ cm of arsenic is used with the gate electrode 3 as a mask.
^-2 Implantation A high concentration source / drain 4 is formed. Thus, the structure of the first embodiment shown in FIG. 4B can be realized only by adding the ion implantation step twice without increasing the mask. In this embodiment, the high-concentration buried layer
Since the layers 7 and 8 are formed on the entire surface, the channel stopper under the element isolation oxide film 10 can be formed by the buried layers 7 and 8 without special formation.

Embodiment 4 Finally, another embodiment of the manufacturing method for forming the structure of the present invention will be described with reference to FIGS.

In the embodiment shown in FIGS. 8A to 8C, the high concentration buried layers 7, 8 are formed by ion implantation over the entire surface after the gate electrode 3 is formed. In this case, the buried layers 7, 8
However, ion implantation with higher energy than in the third embodiment is used so that it is formed inside the substrate under the gate. As a result, the high-concentration buried layers 7, 8 are not directly in contact with the lower portion of the source / drain diffusion layers 4, so that an increase in parasitic capacitance can be prevented.

Further, the embodiment shown in FIG. 9 is a combination of the manufacturing method shown in FIGS. 7 and 8. That is, in the manufacturing method of the present invention, the first high-concentration buried layer 7 for the punch-through stopper and the second high-concentration buried layer 8
It may be formed at any time during the manufacturing process for forming the MIS field effect transistor. Further, the structure of the present invention and the manufacturing method thereof can be easily applied to a CMOS process which is becoming the mainstream of LSI in recent years.

〔The invention's effect〕

According to the present invention, it is possible to prevent a decrease in drain withstand voltage that occurs in a conventional MIS field-effect transistor having a buried layer type punch-through stopper layer, and at the same time, suppress a short channel effect. Therefore, U with a gate length of 0.5 μm or less
It is effective as a basic device of LSI (Ultra Large Scale Integration).

[Brief description of the drawings]

1 is a cross-sectional view of a structure showing a typical example of the present invention, FIG. 2 is a cross-sectional view of a conventional structure, FIG. 3 is a diagram showing main electric characteristics of the conventional structure, and FIG. 5 and 6 are cross-sectional views of a structure showing another embodiment of the present invention, and FIGS. 7, 8, and 9 show typical manufacturing methods of the present invention. FIG. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Gate insulating film, 3 ... Gate electrode, 4 ... High-concentration source / drain, 5 ... Low-concentration source / drain, 6 ... Side wall spacer, 7 ...
... First high concentration buried layer, 8... Second high concentration buried layer.

Claims (7)

(57) [Claims] A semiconductor substrate, a source region and a drain region formed separately on the surface of the semiconductor substrate, a gate insulating film formed on the semiconductor substrate between the source region and the drain region, A semiconductor device including a MOS transistor having a gate electrode formed on the gate insulating film, a punch-through stopper formed inside the semiconductor substrate surface and suppressing punch-through of the MOS transistor; A semiconductor device further comprising: a parasitic bipolar effect suppressing means provided at a lower portion for suppressing a parasitic bipolar effect on the MOS transistor. 2. A semiconductor substrate having a first conductivity type, and a first substrate formed on the entire surface of the semiconductor substrate and having a first conductivity type and having a higher concentration than an impurity in the semiconductor substrate. A semiconductor layer formed on the first semiconductor layer and having a first conductivity type;
A second semiconductor layer having a concentration lower than the impurity concentration in the first semiconductor layer, a channel layer formed on the second semiconductor layer, and a gate insulating film formed on the channel layer A semiconductor device comprising: a gate electrode formed on the gate insulating film; and a source region and a drain region connected to the channel layer and formed on both sides of the gate electrode. 3. A semiconductor substrate having a first conductivity type, and formed on the entire surface of the semiconductor substrate and having the first conductivity type.
A first semiconductor layer having a higher concentration than the impurity concentration in the semiconductor substrate; and a first conductivity type formed on the first semiconductor layer, having a first conductivity type, and having a higher concentration than the impurity concentration in the first semiconductor layer. A second semiconductor layer having a low concentration, a source region and a drain region formed separately above the second semiconductor layer, a channel layer formed between the source region and the drain region, and the channel layer A semiconductor device comprising: a gate insulating film formed thereon; and a gate electrode formed on the gate insulating film. 4. A semiconductor substrate having a first conductivity type, a gate insulating film formed on a surface of the semiconductor substrate, a gate electrode formed on the gate insulating film, and a second electrode different from the first conductivity type. In a semiconductor device including a MOS transistor having a source region and a drain region having a conductivity type, the source region and the drain region each have first and second impurity regions, and the first impurity region is 2
The impurity concentration is lower than that of the first impurity region, and the second impurity region extends closer to the vicinity of the gate electrode than the second impurity region. Further, the first impurity region is formed around the first impurity region.
A third impurity layer having a conductivity type; and a third impurity layer having a first conductivity type, the impurity concentration being higher than the third impurity layer, under the third impurity layer and over the entire lower surface of the MOS transistor. And a fourth impurity layer formed. 5. A first semiconductor layer having a first conductivity type and having a higher concentration than an impurity concentration in the semiconductor substrate is formed in a first depth region of a semiconductor substrate having a first conductivity type. And forming a second semiconductor layer having a first conductivity type and a lower concentration than the impurity concentration of the first semiconductor layer at a second depth shallower than the first depth. Forming a gate insulating film on the surface of the semiconductor substrate; forming a gate electrode on the gate insulating film; and introducing an impurity into the semiconductor substrate in a region where the gate electrode is not formed. Forming a source region and a drain region by performing the method. 6. A step of forming a gate insulating film on a surface of a semiconductor substrate having a first conductivity type; a step of forming a gate electrode on the gate insulating film; A first conductivity type in a first depth region, a second depth region deeper than the first depth below the region where the gate electrode is not formed, and Forming a first semiconductor layer having a concentration higher than the impurity concentration of: forming the gate electrode below the gate electrode at a third depth shallower than the first depth of the semiconductor substrate; A second semiconductor layer having the first conductivity type and having a lower concentration than the impurity concentration of the first semiconductor layer is provided in a fourth depth region shallower than the second depth below the region where the first semiconductor layer is not formed. And forming the gate electrode Forming a source region and a drain region by introducing an impurity into a fifth depth region shallower than the fourth depth below the non-existing region. 7. A first semiconductor layer having a first conductivity type and having a higher concentration than an impurity concentration in the semiconductor substrate is formed in a first depth region of a semiconductor substrate having a first conductivity type. Forming a gate insulating film on the surface of the semiconductor substrate; forming a gate electrode on the gate insulating film; and forming a gate electrode on the semiconductor substrate below the region where the gate electrode is not formed. A first semiconductor layer having a first conductivity type in a second depth region shallower than the first depth and a third depth lower than the second depth below the gate electrode; Forming a second semiconductor layer having a concentration lower than the impurity concentration of: forming a source region and a drain region by introducing impurities into the semiconductor substrate in a region where the gate electrode is not formed; Characterized by having Semiconductor device manufacturing method.