JPH01120067A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a stable and high-reliability MIS type FET which suppresses a short-channel effect without spoiling reliability even with a gate length of 0.5mum or less and whose process is easy by a method wherein a drain or both a source and the drain are constituted by a first low-concentration layer situated only under a gate electrode and by a high-concentration diffusion layer adjacent to the layer. CONSTITUTION:In an MIS type field-effect transistor which is formed on a semiconductor substrate 1 of a first conductivity type and which contains a single gate electrode 4 whose cross-sectional shape is a quadrilateral, the following are contained: first low-concentration semiconductor regions 5 of a second conductivity type whose source and drain are situated or whose drain is situated only under the gate electrode 4; semiconductor regions of the second conductivity type which are adjacent to the regions, which reach the outside of the gate electrode 4 from the lower part of the gate electrode 4 and whose concentration is higher than that of the first semiconductor regions 5. In addition, a third semiconductor region 2 of a first conductivity type which is adjacent to at least said first semiconductor regions 5 and whose concentration is higher than that of the semiconductor substrate 1 is contained. For example, an impurity concentration value of said second semiconductor region 7 is set to be high at 10<19> cm<-3> or more.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and is particularly suitable for improving the reliability of MIS type field effect transistors, and has excellent hot carrier resistance effect or high breakdown voltage. This invention relates to MIS field effect transistors.

[Conventional technology]

In conventional MIS type field effect transistors, as the gate length becomes shorter, the electric field near the drain during operation becomes larger, and the characteristics change due to the injection of hot carriers become larger.

Various structures have been considered to prevent this and improve the breakdown voltage, but one of the most effective structures with a gate length of 1 μm is the one described in Japanese Patent Application Laid-open No. 121771/1983, in which a high concentration diffusion layer is formed from the gate. A low concentration drain (LDD) with a low concentration region provided between the two.

Lightly Doped Drain) structure. This is shown in FIG. 2(a).However, even with a single-layer structure, reliability becomes insufficient when the gate length becomes 0.5 μm or less. In recent reports, I.E.E.

Electron Device Letters, EDL-8, (1987) pp. 151-153 (I
E E E Electron Device Ls
ttersVol, EDL-8 (1987) PP, 15
1-153) is mentioned. This is an improved version of the LDDtA structure. This is the second
Shown in Figure (b).

In addition, as a method for suppressing the latch-up effect caused by parasitic thyristors in complementary semiconductor devices, Japanese Patent Laid-Open No. 62
As described in No. 84547, there is a structure in which a high concentration layer of the same conductivity type as the substrate (well in this case) is provided below the source diffusion layer.

This is shown in FIG. 2(c).

[Problem that the invention seeks to solve]

In the above conventional technology, when the gate length becomes 0.5 μm or less, in the LDDi structure, due to hot carrier deterioration inherent to the LDD structure caused by the sidewall insulating film,
It is not possible to reduce the concentration of the low concentration layer to 10180-8 or less, resulting in a lack of reliability.

Moreover, the short channel effect becomes severe. Also, IT-LD
In D, the short channel effect was severe and the process was complicated and unstable.

An object of the present invention is to provide a highly reliable MIS type field effect transistor which suppresses channel effects without impairing reliability even when the gate length is 0.5 μm or less, and which is easy to process and stable. It is in.

Another object of the present invention is to improve the drain breakdown voltage of a MIS field effect transistor.

[Means for solving problems]

The above object is to provide a MIS field effect transistor having a single gate electrode with a square cross section, in which the drain or source and both drains are connected to a low-concentration first diffusion layer located only under the gate electrode. and a second diffusion layer having a higher concentration than the first diffusion layer in contact with the layer, and further,
This is achieved by providing a third buried N (a so-called punch-through stopper layer) in the substrate so as to be in contact with the first diffusion layer and having a higher concentration than the substrate and the same conductivity type as the substrate.

Furthermore, this can be achieved by forming the second diffusion layer described above so as to reach the gate electrode from the sidewall insulating film formed on the gate sidewall.

Further, the purpose of the above function is to provide a low resistance conductive layer for extracting majority carriers in the substrate under the source inside the substrate under the source of the MIS type field effect transistor, and to provide a low resistance conductive layer inside the substrate under the channel of the transistor. In contact with the drawing layer,
This is achieved by providing an impurity region having a higher concentration than the substrate and the same conductivity type as the substrate.

[Effect]

In the above structure, all the low concentration diffusion layers are under the gate electrode, and the lower part of the sidewall insulating film is a higher concentration diffusion layer, so the hot carrier deterioration inherent to the LDD structure described above does not occur, and the low concentration The concentration of the diffusion layer is 101δ■''
3 or less, and the reliability can be greatly improved.Also, since there is a punch-through stopper layer inside the substrate, the short channel effect can be suppressed even if the diffusion depth of the low concentration diffusion layer is increased.

In terms of reliability, the deeper the depth of the expanded M layer is, the better.6 Furthermore, the process is significantly simplified compared to the conventional IT-LDD structure formation process, and manufacturing yield and cost can be reduced.

Furthermore, the drain breakdown voltage of an MIS field effect transistor is determined by breakdown due to a parasitic bipolar effect induced by substrate current in the case of an n-channel transistor. This is pn
This is because the breakdown occurs at a voltage lower than the breakdown voltage of the junction. This is shown in Figure 2(d).
Explain using. In the case of an n-channel type, current during operation is generated by electrons flowing from the source to the drain. At this time, electrons collide and separate W1 in the high electric field region near the 5 drain, generating electron-hole pairs. Of these, electrons flow to the drain, but most of the holes flow to the substrate. Increasing the drain voltage increases the substrate current due to holes. Along with this, the potential inside the substrate also rises due to the resistance of the substrate itself, and finally the pn junction between the source in the substrate and the source diffusion layer 7 becomes forward, the lateral npn bipolar transistor operates, and the current flows. Increase rapidly. This situation in a typical transistor is shown in FIG. 2 (8), where the drain withstand voltage at each gate voltage differs as the substrate current increases.

Based on the above, in order to improve this drain breakdown voltage, attempts have been made to reduce the generation of substrate current that causes breakdown, and a high breakdown voltage structure as shown in Figure 2 (a) has been devised. . The present invention further provides a method for achieving high breakdown voltage by not suppressing the generation of substrate current itself, but by realizing a structure that is unlikely to break down even if it occurs. This is a region 2 for gearia extraction under the source side diffusion layer, for example, a high concentration diffusion layer (10"cm-"
By providing a diffusion layer of the same conductivity type as the substrate with a medium concentration (for example, 10" m - 88 degrees) below the channel of the transistor, the above parasitic bipolar effect becomes less likely to occur. In other words, the parasitic bipolar effect that occurs near the drain The substrate current is
This is because the light immediately passes through the medium concentration diffusion layer at the bottom of the channel and is extracted by the high concentration diffusion layer at the bottom of the source. In this structure, the emitter and base of the parasitic bipolar transistor of the MOS transistor are shorted to prevent the parasitic bipolar transistor from operating. Thereby, the drain breakdown voltage can be improved to around the drain pn junction breakdown voltage. This situation is shown in FIG. 2(f), similar to FIG. 4(b) above.

Also, as in the prior art shown in FIG. 2(c).

When only the high concentration layer is located below the source, the potential at the bottom of the channel is likely to rise due to substrate current, and the above effect is small.

〔Example〕

<Example 1> The present invention will be explained in detail below.

The structure of the present invention shown in FIG. 1 has a structure in which the low concentration diffusion layer 5 of the LDD structure is entirely under the gate electrode 4, and the reliability against the hot carrier effect is improved. Furthermore, the low concentration diffusion M4 is formed slightly deeper from the end of the gate 4, and bunch through between the source and drain is prevented by the high concentration layer 2 formed inside the substrate. As a result, the short channel effect can be prevented and the depth of the source and drain diffusion layers can be increased, so that the hot carrier effect can be further reduced.

Furthermore, in terms of process, the shape of the gate electrode remains the same as the conventional normal structure, except that the process of forming the high concentration layer 2 for the punch-through stopper is added to the conventional LDD structure forming process. However, the difference from the conventional LDD is that in the structure shown in FIG. 1, the thickness of the sidewall insulating film 6 must be smaller than the lateral extension of the source and drain heavily doped diffusion layers 7.

Further, in the structure shown in FIG. 1, the buried heavily doped p-type layer 2 for the punch-through stopper is a lightly doped n-type drain.

Not only the source diffusion layer 5 but also the highly doped n-type drain.

It is also in contact with the source diffusion layer 7. This is because the impurity concentration of the low-concentration n-swelled diffusion layer becomes increasingly low (below 10"cm"8) due to hot carrier resistance, etc., whereas the buried p-type layer for the punch-through stopper has a gate length. As the length becomes shorter, the concentration must be higher (1017cx-'' or higher). Therefore, when the gate length is 0.5 μm, the buried p-type layer 2 has a concentration comparable to that of the lightly doped n-type drain and source diffusion layer 5.

As a result, even if the lightly doped n-type drain/source expansion M layer 5 is formed deeply so as to surround the highly doped n-type drain/source layer 7, it is still a lightly doped n-type drain.

Since the lower part of the source diffusion layer becomes p-type due to the buried p-type layer 2, the effective vertical depth of the low concentration type drain/source diffusion layer 5 becomes shallow. In order to suppress the hot carrier effect, it is advantageous for the low concentration n-swelled diffusion layer 5 to have a larger lateral extension, and the structure of the present invention shown in FIG. 1 achieves this while suppressing bunch-through. .

In addition, in order to prevent the hot carrier deterioration inherent in the conventional LDD structure, there must be no low concentration diffusion layer under the sidewall insulating film, and it is sufficient that the concentration is at least medium concentration, and the structure according to the present invention has no problem with such a structure. Prevents hot carrier deterioration.

<Example 2> In the example shown in FIG. 3, the punch-through stopper layer high concentration p-type layer 2 formed in the substrate is a source.

This structure is located only below the drain 7. In this example,
Although the bunch-through suppressing effect is somewhat reduced compared to the first embodiment shown in FIG. 1, other characteristics are not impaired. In this structure, since the substrate impurity concentration directly under the channel portion is low, the substrate effect constant of the MOS transistor is small.

In an LSI, the structure of this embodiment is suitable for use in a place where a substrate back bias is applied, such as a transfer gate.

<Example 3> In addition, in the example shown in FIG. 4, the low concentration n-swelling diffusion layer 5 is
It exists around the high concentration diffusion layer 7. this is,
The impurity concentration of the buried p-type layer 2 for the punch-through stopper is lower than that of the low concentration n-swelled diffusion layer 5, or the buried p-type layer 2 is formed in the substrate, which is deeper than the diffusion depth of the low concentration n-swelled diffusion layer 5. corresponds to the case. When used in a location within an LSI where a slightly longer gate length is acceptable, the buried p-type layer 2 may be doped with a lower concentration than in the embodiment shown in FIG.

In addition, in places that do not require as high reliability as conventional LDDs,
The concentration of the low concentration n-swelling diffusion layer can be increased, resulting in a structure as shown in FIG. In this embodiment, since the low concentration n-swell diffusion layer 5 is provided around the high concentration n-swell diffusion layer 7, the junction capacitance can be reduced and the junction breakdown voltage can be improved.

<Example 4> Next, in the example shown in FIG. 5, the low concentration n-type diffusion layer 5 is also formed by diffusion from the outside of the sidewall insulating film 6 similarly to the high concentration n-swelling diffusion layer 7. .

As above, if the amount of improvement in signal quality is only a small amount.

A structure like this example with a small width of the low concentration n-type wave dispersion layer may also be used. In this example, the overlap capacitance between the gate and the diffusion layer can be reduced, and the processed gate length can be shortened with respect to the effective channel length. It is possible to do this.

<Example 5> The example shown in FIG. 6 is a MOS) in which a shallow n-type layer 8 is formed in the channel region in the example shown in FIG.
The transistor channel has been changed from a surface type to a buried type. This makes it possible to obtain a structure with higher current drive capability and higher reliability than a surface channel type element. however.

The buried channel type has severe short channel effects.

Therefore, in FIG. 6, a second buried p-type layer 9 for a punch-through stopper is further formed.

Furthermore, in the buried channel method, the buried p-type layer for the punch-through stopper may be formed by combining 2.9 in FIG. 6 into one.

Furthermore, the embodiment shown in FIG. 7 is different from the buried p-type layer 2 for punch-through stopper in the embodiment shown in FIG.
is formed by high-energy implantation over the entire surface after forming the gate electrode tfi4, and is formed slightly shallower under the gate electrode 4 and deeper inside under the source and drain. This allows the source.

The above-mentioned first method can be achieved without increasing the parasitic capacitance of the drain.
It is very good at producing the effect of the structure of the figure.

It should be noted that all of the embodiments described above can be applied to n-channel transistors and p-channel transistors by reversing the conductivity type polarity.

<Embodiment 6> Next, another embodiment of the present invention will be described using FIGS. 8 to 11. In all of the embodiments described so far, the source/drain is made up of a high concentration n-type diffusion layer and a low concentration n-type diffusion layer, but in the embodiments shown in FIGS. A diffusion layer is provided. In these examples, a heavily doped n-type layer.

1013 cm-” or more, and the low concentration n-type layer is 1Q11
10-8 or less, and the medium concentration n-type layer is in the middle.

First, in the structure shown in FIG. 8, in the embodiment shown in FIG.
A medium concentration n-type diffusion M10 reaching the lower end is provided. This not only improves reliability against hot carriers, but also improves drain breakdown voltage (drain voltage determined by plane-down due to parasitic bipolar effect or drain pn junction avalanche).

In addition, the structure shown in FIG. 9 is one in which the high concentration n-swelled diffusion layer 7 in the embodiment shown in FIG. 8 is also formed so as to reach the lower part of the end of the gate electrode 4. This structure reduces source and drain parasitic resistance and improves current drive capability.

Furthermore, the structure shown in FIG.
0 is formed from the outside of the sidewall insulation film 6 like the high concentration n-swelling diffusion layer 7, and the medium concentration n-swelling diffusion layer 10 surrounds the high concentration n-swelling diffusion layer 7. There is. In this example, the impurity concentration of the medium concentration n-swelled diffusion layer 10 is higher than that of the buried p-type layer 2 for the punch-through stopper, so that the shape as shown in FIG. 10 is obtained.

The junction capacitance of the drain can be reduced.

Finally, in the structure shown in FIG. 11, separate sidewall insulating films were formed twice, 6 and 11, for forming medium and high concentration diffusion layers. Thereby, by changing the width of each sidewall insulating film, the amount of overlap with the gate electrode and the amount of offset can be arbitrarily determined without changing the depth of each diffusion layer.

<Example 7> Finally, an example of a manufacturing method for forming a typical structure of the present invention will be described using FIGS. 12 and 13.

First, as shown in FIG. 12(a), a gate oxide film 3 of 10" to 25 nm is formed on one surface of a p-type silicon (specific resistance 10 Ω-1) substrate by thermal oxidation, and is used for setting a threshold voltage on the entire surface. boron 9 of about 1011-101801'', and
To form the buried layer 2 for the punch-through stopper, boron is deposited at an energy of 100 to 250 KeV for 10” to
This is done by implanting about 10 inches, thereby forming a high-concentration embedding M2 for a punch-through stopper uniformly inside the substrate as shown in FIG. 12(a).

Next, 200 to 300 nm of phosphorus-doped polycrystalline silicon is
m is formed and patterned by photo-etching to form the gate electrode 4. Next, using this gate electrode as a mask, approximately 5×10" to 1×10" of phosphorus is implanted to form a low concentration n-type source.

A drain diffusion layer 5 is formed. At this time, the low concentration diffusion layer 5
can be sufficiently extended in the horizontal direction by subsequent annealing as shown in FIG. 12(b), but cannot be extended any further in the vertical direction because of the buried layer 2. The horizontal extension of the low concentration diffusion layer 5 is 0.15 to 0.25 μm, and the vertical extension is 0.1 to 0.2 μm.

Finally, as shown in Figure 12C, the 5iOz film was
After deposition by chemical vapor deposition of 0 to 250 nm, it is removed by reactive ion etching to form a 5 ift side wall 6 on the side wall of the gate electrode 4. At this time, the width of the sidewall 6 is 0.1 to 0.2 μm. Subsequently, a high concentration n-type diffusion layer 7 is formed by implanting arsenic at a density of 5×10 cm and subsequent annealing.

At this time, the lateral elongation of the high concentration diffusion layer is 0.15 to 0.2
It becomes 5 μm. However, what is important is that the diffusion end of this high concentration diffusion layer 7 formed from the outside of the sidewall 6 should reach directly under the gate electrode 4.

This can be done by setting the high concentration diffusion M7, the lateral extension, and the width of the sidewall insulating film 6 to 114 m, and can be formed in a self-aligned manner without increasing the number of masks. This structure is the same as the embodiment of FIG.

Furthermore, in the embodiment shown in FIG. 13, the p-type cavity concentration layer 2 for the punch-through stopper in the embodiment shown in FIG. Since it is formed by implanting boron at a high energy of 200 to 1000 KeV, the lower part of the gate electrode 4 is made slightly shallower to serve as a punch-through stopper, as shown in FIG. 13(c).

The lower portions of the source and drain diffusion layers should be avoided to be formed deeper into the substrate. In the embodiment of FIG. 13, the source.

The parasitic capacitance of the drain diffusion layer can be reduced. Also.

Although the p-type buried layer 2 is formed after the sidewall insulating film is formed in FIG. 13, it may be formed immediately after the gate electrode is formed.

Although the above embodiment has described the manufacturing method for an n-channel MO3FET, it can also be applied to a p-channel by reversing the conductivity type. Furthermore, the gate electrode may be made of not only polycrystalline silicon but also a polycide gate with a metal or metal silicide layer coated thereon, or a metal gate, which can further reduce wiring resistance.

<Embodiment 8> An embodiment of the present invention will be described below with reference to FIGS. 5 to 10.

The embodiment shown in FIG. 15 outlines the manufacturing process of the embodiment shown in FIG. 14.

First, as shown in FIG. 15(a), a gate oxide film 3 of 10 to 20 nm is formed on a p-type silicon substrate 1 of about 10Ω■, and boron is irradiated with high energy (100 to 200 KaV).
10'' to 5×10121 an-” and low energy (5 to 20 KeV) to an IQ of 11 to 10”Ca1-” and heat treatment.

At this time, the high energy implantation layer 2 is for a punch-through stopper, and the low energy implantation layer 8 is for threshold voltage control.

Next, as shown in FIG. 15(b), the polycrystalline silicon film 4 is
0 to 300 nm, and the silicon oxide film 16 to 100 to 3
After 00 nm coating, these two layers were patterned together by photoetching.

A gate electrode 4 is formed. Thereafter, as shown in FIG. 15(c), using this gate electrode 4 as a mask, arsenic is added to IQIII to 1
A diffusion layer 7 is formed by implanting to a depth of about 0.013 cm-''.

Then, as shown in FIG. 15(d), after coating a resist with a thickness of about 1 μm, an opening is formed in the source diffusion layer by photolithography, and boron is implanted with a high energy temperature of about 1014 to 1×1011 sam-8 at 100 to 200 K e V (7). , a p-middle diffusion layer 10 is formed so as to be in contact with the source n-middle layer 7. After removing the resist, the process may be exactly the same as the conventional MOS process.

In this structure, since there is a punch-through stopper layer 2 on the entire surface of the substrate, the short channel effect can be suppressed, and furthermore, holes generated near the drain are immediately removed from the pm2
It flows into the source side, passes through the p-type intermediate layer 10 for extraction, and reaches the source n-diffusion layer. Therefore, in this embodiment, punch-through is suppressed and drain breakdown voltage is improved at the same time. Note that the high concentration p medium diffusion layer 10 may be formed before the source/drain n diffusion layer is formed.

Furthermore, since the above-mentioned drawing layer 10 may be made of a low-resistance conductive material, it may be made of not only a P medium scattering layer but also a metal or a metal silicide compound.

<Embodiment 9> In the embodiment shown in FIG. 16, the drain structure itself was changed from a single drain structure to an LD0411 structure in the structure shown in FIG. 15. That is, a side wall spacer 6 made of an insulating film is formed on the side wall of the gate electrode 4, and a low concentration drain n shadow region 5 is formed below it. A punch through stopper p-type layer 2 and a buried pull-out layer 10 are present below the drain. This improves not only drain breakdown voltage but also long-term reliability due to hot carriers.

Further, the embodiment shown in FIG. 17 also has a double drain structure for high reliability, similar to the structure shown in FIG. 16 above. However, in FIG. 17, the low concentration drain n
- The diffusion M5 is formed by diffusion from the edge of the gate, but the n-diffusion layer 7 is formed from the edge of the sidewall insulating film 6, and the edge of the diffusion layer also reaches the lower part of the gate electrode. Furthermore, since there is a punch-through stopper M2 inside the substrate, the n-layer inside the substrate is canceled out, resulting in a structure as shown in the figure.

The effect is similar to that shown in FIG.

Embodiment 10 The embodiments shown in FIGS. 18 and 19 show other embodiments regarding the connection between the buried pull-out layer and the source. The extraction layer is a p-type buried layer, which is the same as that shown in FIG.

First, the structure shown in FIG. 18 has only the source diffusion layer side.
A buried electrode 11 reaching the buried p-middle layer 10 is formed. This buried electrode 11 may be made of a low resistance material such as polycrystalline silicon or metal. As for the formation method, after coating the interlayer insulating film, it is sufficient to form a groove in the silicon substrate only on the source side when forming the contact hole. After that,
Aluminum wiring may be formed directly or another buried electrode may be formed.

Next, FIG. 19 shows a p-middle layer 12 that connects the buried p-middle layer 13 and the substrate surface, in addition to the n-middle layer 7 of the source side diffusion layer.
The outside is defined as this p middle layer 12 source n
All you have to do is connect the ten layers to aluminum wiring, etc.
In the embodiment shown in FIGS. 8 and 19, the buried p-middle layer 10
．． Since the connection portion 13 is formed separately, it is not necessary that the source n-type intermediate layer 7 and this p-type intermediate layer 13 are in contact with each other.

In the above embodiments, only n-channel transistors have been shown, but future fine p-channel transistors can also be realized by reversing the conductivity types of the impurity regions.

<Embodiment 11> Finally, an embodiment in which the present invention is applied to a complementary semiconductor device will be described with reference to FIG.

FIG. 20(a) shows a complementary semiconductor device in which three n-channel transistors and three p-channel transistors are arranged as an example. 23 is an n-well in which a p-channel transistor is formed, and 22 is an n-well in which a p-channel transistor is formed. In this figure, each transistor is arranged in the same direction and grouped under a common source-side diffusion layer, and the n-channel side is filled with p+ yW.
J2. O.

On the p-channel side, n÷buried layer 21 is formed.

The cross-sectional view at AA' in Fig. 20(a) is shown in Fig. 20(b).
As shown in FIG. 2, the buried layers may be formed to be large all at once. Thereby, it is possible not only to improve the drain breakdown voltage but also to suppress the latch-ship phenomenon inherent in complementary semiconductor devices.

〔Effect of the invention〕

According to the present invention, the inherent hot carrier effect that occurs in conventional LDD structures does not occur, and short channel effects can also be suppressed. For this reason, future U L S I (U
ltra Large 5cale Integrat
In addition, according to the present invention, the drain breakdown voltage can be improved more than the improvement of the drain structure such as the conventional LDD structure. ULSI (UltraLarge 5) using micron technology
It is very effective as a basic device for cale integration.

[Brief explanation of the drawing]

Figure 1 is a sectional view of a structure showing an embodiment of the present invention, Figure 2 (a) to (c) are sectional views of a conventional structure, and Figures 2(d) to (
f) is a diagram showing the breakdown mechanism due to the parasitic bipolar effect and typical I-V characteristics of the structure of the present invention and the conventional structure. 12-13 are cross-sectional views showing an example of the manufacturing process for forming the structure of the present invention, and FIGS.
FIG. 20 is a diagram showing another embodiment of the present invention. 1... Semiconductor substrate, 2... Buried high concentration layer, 3.
... Gate insulating film, 4... Gate electrode, 5... Low concentration diffusion layer, 6.11... Sidewall insulating film, 7'
High concentration diffusion layer, 10... Medium concentration diffusion layer.

Claims (1)

[Claims] 1. In an MIS field effect transistor formed on a first conductivity type semiconductor substrate and having a single gate electrode with a square cross-sectional shape, the source, the drain, or one of the drains is connected to the gate. A first semiconductor region of a second conductivity type with a low concentration existing only under the electrode, and a second semiconductor region of a second conductivity type with a higher concentration than the first semiconductor region that is in contact with the first semiconductor region and reaches from under the gate electrode to the outside of the gate electrode. and a third semiconductor region having a first conductivity type and a higher concentration than the semiconductor substrate, which is in contact with at least the first semiconductor region inside the substrate. 2. In the semiconductor device according to claim 1,
The impurity concentration of the second semiconductor region is 10^1^9cm^-^
A semiconductor device characterized by having a high concentration of 3 or more. 3. In the semiconductor device according to claim 2,
A semiconductor device characterized in that the diffusion depth of the first semiconductor region is greater than or equal to the diffusion depth of the second semiconductor region. 4. In the semiconductor device according to claim 1,
A semiconductor device comprising a fourth semiconductor region that is in contact with the second semiconductor region, has a second conductivity type, and has a higher concentration than the second semiconductor region. 5. In the semiconductor device according to claim 4,
The concentration of the first semiconductor region is 10^1^3 cm^-^3 or less, and the concentration of the second semiconductor region is 10^1^3 cm^-^3 or more and 10^2^0 cm^-^3 or less. Characteristic semiconductor devices. 6. In the semiconductor device according to claim 5,
A semiconductor device characterized in that the fourth semiconductor region is not directly under the gate electrode. 7. In the semiconductor device according to claim 6,
A semiconductor device characterized in that the diffusion depth of the first semiconductor region is greater than or equal to the diffusion depth of the second semiconductor region. 8. In a MIS field effect transistor formed on a first conductivity type semiconductor substrate, a first conductive region for extracting excess majority carriers in the substrate exists below the source, and a first conductive region exists below the channel of the transistor. A semiconductor device comprising: a second impurity region having a first conductivity type and having a higher concentration than the substrate that is in contact with the source, the drain, and the first conductive region. 9. In the semiconductor device according to claim 8,
A semiconductor device, wherein the first conductive region is in contact with the source, has a first conductivity type, and is an impurity region having a higher concentration than the substrate and the second impurity region. 10. The semiconductor device according to claim 9, wherein at least one of the source and the drain includes a low concentration third impurity region of the second conductivity type partially under the gate electrode, and the third impurity region. A semiconductor device comprising a fourth impurity region of a second conductivity type and a higher concentration than a third impurity region, which is in contact with the region. 11. In a manufacturing method for forming an MIS field effect transistor on the surface of a semiconductor substrate, before or after forming a gate electrode, impurities of the same conductivity type as the substrate are ion-implanted into the substrate to form a third semiconductor region. After forming the gate electrode, a low concentration first semiconductor region for the source and drain is formed using the gate electrode as a mask, and then a sidewall insulating film is formed on the sidewalls of the gate electrode, and then a sidewall insulating film is formed between the gate electrode and the sidewall. A method of manufacturing a semiconductor device, comprising the step of forming a second semiconductor region having a higher impurity concentration than the first semiconductor region and reaching directly below the gate electrode using a film as a mask.