JPH05275693A - Manufacture of mosfet - Google Patents

Abstract

PURPOSE:To enhance a MOSFET provided with a micronized gate electrode in withstand voltage by a method wherein a P-type buried region is formed by obliquely implanting boron ions. CONSTITUTION:A buried region 18 is formed under a gate electrode 16 on a drain side by obliquely implanting baron B into a wafer where the gate electrode 16 has been built from the above. An ion-implanting operation is carried out keeping a source region 21 masked by putting the source region 21 in the shade of the gate electrode 16. Phosphorus ions are vertically implanted into the wafer for the formation of a source region 21 and a drain region 22. By canceling the obliquely implanted Boron and impurities with each other, the drain region 22 is formed into a structure where a depletion layer is easily spread out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOSFET having a buried region of the same conductivity type as a channel.

[0002]

2. Description of the Related Art Generally, a source / drain region of a MOSFET is formed by a self-alignment method using a gate electrode as a mask. However, in various driver devices and high frequency devices, the breakdown voltage (V
It is known that a low-concentration offset region is provided on the drain side in order to increase the _DSS ).

7 and 8 are sectional views showing a method of manufacturing a MOSFET having the above-mentioned offset region. An example of the manufacturing method will be described with reference to the drawings. First, a gate electrode (3) made of a polysilicon layer having a gate length of 4 μ or more and a thickness of about 1.0 μ is formed on a P-type silicon substrate (1) through a gate oxide film (2) of about several hundred liters, Phosphorus (P) that forms the offset region (4) is ion-implanted using the gate electrode (3) as a part of the mask (FIG. 7).

Next, a part of the gate electrode (3) and a region to be an offset region (4) are covered with a resist pattern (5), and phosphorus (P) ions which form source / drain regions (6) are formed again from above. Inject (FIG. 8). After that, the resist pattern (5) is removed, and a heat treatment is applied to the entire substrate (1), whereby an N-type offset region (4) is formed on the drain side.
To form an N-N ⁺ structure. A MOSFET structure having an NN ⁺ structure is disclosed in, for example, Japanese Unexamined Patent Publication No. 02-82627.
No.

[0005]

However, the MOS
The high frequency characteristics of the FET are mainly largely influenced by the effective channel length immediately below the gate electrode (3), and miniaturization of the gate electrode (3) is indispensable for improving the high frequency characteristics. Then, in the step of covering a part of the gate electrode (3) with the resist pattern (5) (FIG. 8), there is a drawback that it becomes difficult to align the gate electrode (3) and the resist pattern (5). Further, as the gate electrode (3) is miniaturized, the depletion layer extending from the offset region (4) easily reaches the source region (6).

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and comprises the steps of forming a gate electrode on a silicon substrate and performing ion implantation from a diagonal direction to a wafer. , A step of selectively forming a P-type buried region on the drain side, a step of ion-implanting an N-type impurity in a direction perpendicular to the wafer, and a heat treatment to add a P-type buried region near the drain of the channel portion And a step of forming an offset region in which the P-type impurity and the N-type impurity are offset and the drain region is made to have a lower concentration than the source region, while forming a region by diffusion. It provides a method.

[0007]

According to the present invention, since the channel region on the drain side has the P-type buried region (18), the depletion layer extending from the PN junction between the N-type drain region (22) and the substrate (11) extends. To prevent punch-through between the source and drain peculiar to the short channel MOSFET. Further, by canceling the P-type impurity and the N-type impurity, the substantial impurity concentration of the drain region (22) can be made lower than that of the source region (21). Therefore, the depletion layer easily spreads to the drain region (22) side.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An n-channel MO according to an embodiment of the present invention will be described below.
The SFET will be described in detail as an example. 1 to 6 are cross-sectional views sequentially showing main steps for explaining the manufacturing method. First, referring to FIG. 1, P having a P ⁺ layer on the back surface
A P ⁺ type annular ring layer (12) surrounding the peripheral portion of the chip is formed on the surface of the type silicon substrate (11) by a well-known diffusion technique, and then an N ⁺⁺ type contact region (13) is similarly formed. .. (14) is an oxide film.

Referring to FIG. 2, the oxide film (14) in the portion which becomes the active region on the substrate (11) is removed, and the exposed silicon surface is thermally oxidized to form a gate oxide film having a thickness of several hundred Å. A film (15) is formed. Ions are implanted for controlling the threshold voltage (Vt), and a polysilicon layer having a thickness of 1.0 to 2.0 μ is deposited by CVD on the gate oxide film (15). The polysilicon layer is doped with impurities, and the polysilicon layer is patterned by a well-known photolithography process to form a gate electrode (16).

Referring to FIG. 3, the source and the drain are S-
First, the gate electrode (16) is formed to be formed alternately with D-S.
A photoresist layer (17) is formed by a conventional photolithography technique so as to cover one side. Then, boron (B) is ion-implanted obliquely from above the wafer. In this step, the drain side is implanted with boron (B) to form a buried region (18) extending to the lower part of the gate electrode (16), and the source side is a shadow of the gate electrode (16). Boron (B) is not injected. In this embodiment, the angle of boron (B) ion implantation is 20 to 40 ° with respect to the vertical direction of the wafer, and 30 to 40 keV and 10 ¹³ c.
The dose was about m ^-2 . The acceleration voltage is adjusted so that boron (B) penetrates the gate oxide film (15) and is implanted near the surface of silicon. In the oblique ion implantation, there is a difference in impurity concentration even if boron (B) is implanted in the contact region (13).
There is no particular problem (for example, barrier formation with the Al electrode).

Referring to FIG. 4, a photoresist layer (17)
Is removed and the other side of the gate electrode (16) is covered with a photoresist layer (19) this time, and boron (B) is ion-implanted in an oblique direction opposite to the previous step to form a buried region (18). To do. The implantation angle, the acceleration voltage, and the dose amount are the same as those in the previous step. Referring to FIG. 5, a photoresist layer (1
9) is modified to form a photoresist layer (20) covering the area other than the active region, and phosphorus (P) is ion-implanted in the vertical direction to form source / drain regions (21) (22). The condition is 60 to 100 keV, and the dose amount is about 10 ¹³ cm ^-2 so that the above-mentioned boron (B) can be offset. Since the boron (B) is in the oblique direction, but the ion implantation of phosphorus (P) is in the vertical direction, the buried region (18) below the gate electrode (16) is not offset. The ion implantation in this step is performed at an accelerating voltage that penetrates the gate oxide film (15) and is implanted deeper than boron (B).

Referring to FIG. 6, a photoresist layer (20).
Then, the entire surface is covered with a CVD oxide film, and activation and diffusion of the ion-implanted impurities are performed while also baking the CVD oxide film. Due to this diffusion, an N type source region (21) and a drain region (22) are formed on both sides of the gate electrode (16).
And a P-type buried region (18) is formed under the gate electrode (16) so as to be in contact with the drain region (22). The drain region (22) is diffused to be equal to or slightly deeper than the obliquely implanted boron (B), and cancels impurities to reverse the conductivity type to the N-type diffusion region. As a result of the cancellation, the impurity concentration of the drain region (22) becomes lower than that of the source region (21), and the depletion layer becomes a region in which it easily expands. The offset region has the same function as the so-called conventional offset region.

Thereafter, contact holes are opened in the CVD oxide film, and each electrode is formed by vapor deposition of aluminum and photoetching. The source electrode (23) makes ohmic contact with both the source side contact region (13) and the annular ring region (12) to apply a substrate bias,
The drain electrode (24) contacts the contact region (13) on the drain side.

According to the manufacturing method of the present invention described above, first, a transistor structure structurally having a P-type buried region (18) near the drain under the gate electrode (16) can be provided. The buried region (18) is formed on the substrate (1
1) because it has a higher impurity concentration than the drain region (2
2) The expansion of the depletion layer caused by the PN junction between the substrate (11) and the substrate (11) is suppressed. Therefore, the depletion layer is the source region (2
Since the punch-through phenomenon reaching 1) can be suppressed and the breakdown voltage can be increased, the amount can contribute to the miniaturization of the gate electrode (16).

Further, since boron (B) is ion-implanted so as to overlap the drain region (22), the P-type impurity cancels the N-type impurity and the substantial impurity concentration of the drain region (22) is reduced. .. Therefore, the depletion layer is easily expanded to the drain region (22) side, and the breakdown voltage (V _DSS ) of the MOSFET can be increased. In terms of the manufacturing method, the use of oblique ion implantation does not require a resist mask, so that the gate electrode (1 μm or less) is miniaturized.
Even in the case of 6), the buried region (18) can be formed in a self-aligned manner.

[0016]

As described above, according to the present invention,
By providing the P-type buried region (18) below the drain side gate electrode (16), the punch-through phenomenon of the depletion layer can be suppressed and the breakdown voltage can be increased.
It has the advantage of being compatible with the miniaturization of. In addition, since the impurity concentration of the drain region (22) is canceled by the impurities for forming the buried region (18), the depletion layer becomes the drain region (2).
The structure easily spreads to the 2) side, the source-drain breakdown voltage can be increased, and the source-drain capacitance can be reduced. In addition, since the junction depth of the drain region (22) can be made shallower by offsetting, the lateral diffusion can be reduced and the gate.
The capacitance due to the overlap between the drains can be reduced, and the mirror effect can be reduced. Further, since the photomask for forming the buried region (18) can be reduced by the ion implantation in the oblique direction, it also has an advantage that it can sufficiently correspond to the miniaturized gate electrode (16).

[Brief description of drawings]

FIG. 1 is a first sectional view for explaining the present invention.

FIG. 2 is a second cross-sectional view for explaining the present invention.

FIG. 3 is a third sectional view for explaining the present invention.

FIG. 4 is a fourth sectional view for explaining the present invention.

FIG. 5 is a fifth cross-sectional view for explaining the present invention.

FIG. 6 is a sixth sectional view for explaining the present invention.

FIG. 7 is a first cross-sectional view for explaining a conventional example.

FIG. 8 is a second cross-sectional view for explaining a conventional example.

Claims (2)

[Claims] 1. A step of forming a gate electrode on a channel region of a one-conductivity-type semiconductor substrate with a gate insulating film interposed between the gate electrode and a diagonal direction so that the source side from above the gate electrode is blocked by the shoulder portion of the gate electrode. Implanting an impurity of one conductivity type into the drain side and the vicinity of the drain of the channel portion by ion implantation into the drain, and an impurity of an opposite conductivity type forming a source / drain region in a vertical direction from above the gate electrode. And ion-implanting the entire substrate to form a buried region of one conductivity type in the vicinity of the drain of the channel region by the impurities ion-implanted in the oblique direction, and at the same time, the impurity of one conductivity type and the MOS type characterized in that the impurity concentration of the drain region is made lower than the impurity concentration of the source region by canceling out impurities of the opposite conductivity type. Method of manufacturing FET. 2. The diffusion depth of the drain region and the diffusion depth of the buried region are equal to each other.
A method for manufacturing the described MOS FET.